JP2616214B2 - Panel display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device that controls display of a panel display having a display timing different from that of a CRT display by an application program created for the CRT display. ,
In particular, the present invention relates to a panel display control device that controls a single-drive panel display divided into two screens.

[Prior Art] In recent years, with the miniaturization of various OA devices such as personal computers and word processors, displays used for these devices have been replaced by panel-type devices such as liquid crystal displays and plasma displays instead of conventional CRT displays. Things have come to be heavily used.

In addition, as shown in FIG. 5, the panel 21 is divided into, for example, two upper and lower screens, and each screen is divided into A two-sided single-drive LCD panel display driven by 23 has also been developed. In this display, as shown in the display timing diagram of FIG.
The line panel display data PDA and the panel display data PDA of 241 to 480 lines constituting the lower divided screen are alternately supplied line by line.

On the other hand, the display timing of a panel type display and a CRT display are usually different.
Therefore, in order to drive the above-described conventional two-panel single-drive panel display with an application program created for a CRT display, the following method has conventionally been adopted.

That is, the content of the timing control register of the existing CRT controller is set to the same timing as the panel timing according to the initial setting program.

Then, the display memory (V
Access to RAM) is performed alternately on the upper and lower two screens. Therefore, a memory address generating circuit for that purpose is provided for two screens, upper and lower.

[Problem to be Solved by the Invention] However, as described above, when the content of the control register is set to match the timing of the panel display, and when the display mode is changed by the application program, Since the contents of the timing control register are rewritten, the set timing for the panel is impaired, and there is a problem that the display operation is hindered. Therefore, in this case, a calculation means such as a local CPU for converting the contents of the register set for the CRT into the timing data for the panel is required, and there is a problem that the parts cost is increased.

Further, in the above method, since the memory addresses of the upper and lower two screens are generated alternately, there is also a problem that a special address generation circuit including two counters having different preset values is required.

The present invention has been made in order to solve such a problem, and a two-screen panel display can be used without difficulty by timing data set for a CRT display without causing a significant increase in parts cost. It is an object of the present invention to provide a panel display control device which can perform display control and has excellent compatibility.

[Means for Solving the Problems] A panel display control device according to the present invention includes: a clock supply unit that supplies a basic clock that is a basis of display timing of a two-screen divided single drive type panel display to be display-controlled; And a display timing signal and display data of the panel display are output to the outside based on the basic clock and a wait signal externally supplied. Possible
A CRT controller, a panel data conversion circuit for converting display data output from the CRT controller into display data for a panel, and a half frame of the panel display data output from the panel data conversion circuit are stored. 1
/ 2 frame buffer, the basic clock and the CR
The wait signal for interrupting the output operation of the display timing signal and the display data in the CRT controller for a period during which the display data can be output for one line based on the input of the display timing signal from the T controller. A panel timing controller that outputs to the CRT controller and outputs a panel up / down switching signal synchronized with the wait signal, and controls read / write to the 1/2 frame buffer based on the panel up / down switching signal, During a period in which one line of the display data for the panel is being output from the panel data conversion circuit, the one line of the display data is written into the 1/2 frame buffer.
A frame buffer interface that reads display data of a line that is a half frame apart from the display data written immediately before the RT data is suspended from the half frame buffer during a period in which the operation of the RT controller is interrupted by the wait signal; A data control for alternately selecting display data output from the panel data conversion circuit and display data output from the 1/2 frame buffer line by line in accordance with the panel up / down switching signal, and outputting the data to the panel display. And a circuit.

According to the present invention, the CRT controller operates in accordance with the basic clock for the panel and repeats the wait operation in accordance with the wait signal output from the panel timing controller, thereby forcibly synchronizing with the panel timing. Will be Further, according to the present invention, a half screen buffer is provided, and the display data supplied from the CRT controller and the display data read from the half frame buffer are alternately selected, whereby a two-screen split type is provided. Data can be supplied in an order that matches the panel display of FIG.

Therefore, according to the present invention, without manipulating the order of the display data output from the CRT controller,
The display control of the two-screen split type panel display can be performed according to the application program for the CRT display without changing the timing data set inside the CRT controller at all. Therefore, it is possible to provide a panel display control device having excellent compatibility.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a display controller 1, a display memory (hereinafter referred to as VRAM) 2 and a flat panel display 3 connected thereto according to this embodiment.

The display controller 1 is configured as follows.

That is, C that defines the display timing of the CRT display
The RT clock signal CCK and the panel clock signal PCK that defines the display timing of the panel display are selected by the clock select circuit 11 and supplied to the CRT controller 12 and the panel timing controller 13 as the clock signal CLK. These controllers 12,13
Operates on a CRT clock signal CCK when performing display control on a CRT display (not shown), and operates on a panel clock signal PCK when performing display control on the flat panel display 3.

The CRT controller 12 includes a timing control register (not shown) and an external synchronization circuit 14 therein. The CRT controller 12 outputs a horizontal signal to a CRT controller (not shown) based on timing data set in the internal timing control register. Outputs various timing signals such as a synchronization signal, supplies the display timing signal DTMG to the panel timing controller 13, and applies a weight to the display timing signal DTMG based on the weight signal output from the panel timing controller 13. To the timing for In addition, the CRT controller 12
The display data VDA is sequentially read from the RAM 2 and supplied to the panel data conversion circuit 15 as CRT display data CDA.

On the other hand, based on the timing signal DTMG from the CRT controller 12 and the clock signal CLK from the clock select circuit 11, the panel timing controller 13 outputs a wait signal WT, a panel upper / lower screen switching signal SW, a panel control signal LC, and a shift clock signal SCK. And supplies these signals to the external synchronization circuit 14, frame buffer interface 16, flat panel display 3 and panel data conversion circuit 15, respectively.

The panel data conversion circuit 15 converts the CRT display data CDA supplied from the CRT controller 12 into panel display data PDA1 by performing, for example, a process such as giving gradation.

The frame buffer interface 16 receives a read / write signal R /
W is supplied to the 1/2 frame buffer 17. The display data for the panel output from the panel data conversion circuit 15
The PDA1 is written to the 1/2 frame buffer 17 according to the read / write signal R / W, and is read out as the display data PDA2 from the 1/2 frame buffer 17 according to the read / write signal R / W.

The data controller circuit 18 is a panel data conversion circuit
The display data PDA1 output from 15 and the display data PDA2 read from the 1/2 frame buffer 17 are alternately selected for each line, and the display data PDA is supplied to the flat panel display 3.

Next, the operation of the display controller configured as described above will be described.

First, when performing display control of a CRT display (not shown), the clock select circuit 11 selects a CRT clock signal CCK. As a result, as shown in FIG. 2, the CRT controller 12 sets the horizontal synchronization time and the horizontal synchronization start time set in the internal timing control register.
A horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC for giving a display timing of the CRT display are output based on timing data such as end timing and blanking period start / end timing. The display data VDA read from the VRAM 12 is output from the CRT controller 12 as display data CDA according to the various timing signals. In the figure, the numbers described in the display data CDA indicate the line numbers, and in this example,
A screen of one frame is composed of 480 lines.

On the other hand, when performing display control of the flat panel display 7, the clock signal PCK is selected by the clock select circuit 11 so that not only the panel timing controller 13 but also the CRT controller 12 is controlled by the panel clock signal PCK. It works by. The display timing at this time is shown in FIG. In this figure, the numbers given to the timing charts of the panel data PDA1, PDA2, PDA indicate the line numbers of the flat panel display 3. Flat panel display 3
, Lines 1 to 240 constitute an upper screen, and lines 241 to 480 constitute a lower screen.

As shown in FIG. 3, first, the display timing signal DTMG
Is activated, the display data CDA of the first line constituting the upper screen of the panel is output from the CRT controller 12. The display data CDA is supplied to the panel data conversion circuit 1
5 converts the data into display data PDA1 for a panel. At this time, since the panel upper / lower screen switching signal SW is at the “1” level, the data control circuit 18 displays the display data.
Select PDA1 and output to flat panel display 3.

When the display data of the first line is supplied to the flat panel display 3, the display timing signal DTMG becomes inactive. In response to this, the panel timing controller 13 sends the wait signal WT to the CRT controller 12
Output to As a result, the CRT controller 12 stops operating and holds the state before the generation of the wait signal WT.

During this wait operation, the panel timing controller 13 switches the read / write signal to the 1/2 frame buffer 17 to read the data of the 241st line of the lower screen stored in the 1/2 frame buffer 17. . At this time, since the panel upper / lower screen switching signal SW is at the “0” level, the data control circuit 18 selects the display data PDA2 read from the frame buffer 17 and outputs it to the flat panel display 3.

When the display data of the 241st line is supplied to the flat panel display 3, the panel timing controller
Since the output of the wait signal WT from the controller 13 is stopped, the CRT controller 13 receives the signal, and the display timing signal DTMG
Is activated to restart the operation, and the display operation of the next second line is forcibly started.

Thereafter, by repeating the same procedure, the display data PDA is alternately supplied to the flat panel display 3 from the CRT controller 12 and the 1/2 frame buffer 17.

Here, the CRT controller 12 can be synchronized with the panel timing by setting the pulse interval of the wait signal WT to an appropriate value.

FIG. 4 is a schematic diagram showing a flow of display data PDA supplied from the CRT controller 12 and the 1/2 frame buffer 17 to the flat panel display.

First, when the CRT controller 12 is scanning the upper screen of the panel, as shown in FIG. 4A, the CRT controller 12 sends data to the first line of the flat panel display 3 according to the scanning, At the same time, the data of the first line is stored in the frame buffer 17. 1
When all the data of the line has been scanned, the data of the 241st line already stored in the frame buffer 17 is sent to the lower screen of the flat panel display 3.
Hereinafter, similarly, when the CRT controller 12 scans up to the 240th line of data, the display operation for one frame is completed. At this point, data of 1 to 240 lines is stored in the 1/2 frame buffer 17. In this case, for example, the area where the data of the 241st line is stored is
When writing the data of the line 241, the data of the line 241 may be stored in the line buffer before the writing operation. With this, the display data RD
Display data PD to be read by writing A1
A2 can be prevented from disappearing.

On the other hand, when the CRT controller 12 is scanning the lower screen of the panel, first, as shown in FIG. It is sent to the display 3 and the display operation of the first line is performed. Subsequently, the data of the 241st line is supplied from the CRT controller 12 after the cancellation of the wait to the flat panel display 3, and at the same time,
The data of the 241st line is stored in the frame buffer 17. Next, the data of the second line is stored in the frame buffer 17.
And is supplied to the panel display 3.
When the above operation is repeated and the data of the 480th line is stored in the frame buffer 17, the data of the 241st to 480th lines are stored in the frame buffer 17.

As described above, according to the display controller of this embodiment, the CRT controller 12 is forcibly weighted from the outside to synchronize with the panel timing. Sufficient compatibility can be ensured for application programs.

Also, by sequentially storing the display data in the 1/2 frame buffer 17 and alternately selecting the display data PDA1 output from the panel data conversion circuit 15 and the display data PDA2 output from the CRT controller 12, The display control of the two-screen single drive type flat panel display 3 can be performed without any trouble.

[Effects of the Invention] As described above, according to the present invention, the CRT controller is forcibly weighted by the panel timing controller, so that the synchronization with the panel timing is performed. There is no need to change the values and the like, and complete compatibility can be ensured.

Further, according to the present invention, since a half-frame buffer is provided and the display data supplied from the CRT controller and the display data read from the half-frame buffer are alternately selected, 2 It is possible to supply data in an order that matches a screen display of a screen division type.

According to the present invention, the required buffer capacity is
Since it is sufficient to use a half frame, the amount of hardware does not increase significantly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display controller according to an embodiment of the present invention, and FIG.
FIG. 3 is a timing diagram showing panel display timing by the controller, FIG. 4 is a schematic diagram showing a flow of display data supplied to the panel display, and FIG. FIG. 6 is a block diagram of a drive type panel display, and FIG. 6 is a timing chart showing display timing of the panel display. 1. Display controller, 2. VRAM, 3.
Flat panel display, 11 Clock select circuit, 12 CRT controller, 3 Panel timing controller, 14 External synchronization circuit, 15 Panel data conversion circuit, 16 Frame buffer interface, 17 1/2 frame buffer, 18 data control circuit.

Claims (1)

(57) [Claims] 1. A clock supply means for supplying a basic clock which is a basis of display timing of a two-screen split single drive type panel display to be display-controlled, based on a predetermined clock signal and a timing set value set internally. A CRT controller operable to output a display timing signal and display data of the panel display based on the basic clock and an externally applied wait signal; and a display output from the CRT controller. A panel data conversion circuit for converting data into display data for a panel, a half frame buffer for storing half a frame of display data for a panel output from the panel data conversion circuit, Based on the input of the display timing signal from the CRT controller, The wait signal for interrupting the output operation of the display timing signal and the display data in the CRT controller for a period during which the display data can be output for one line is provided by the CR.
A panel timing controller for outputting to the T controller and outputting a panel up / down switching signal synchronized with the weight signal; and controlling read / write to / from the 1/2 frame buffer based on the panel up / down switching signal. During a period during which one line of display data for the panel is output from the data conversion circuit, the one line of display data is written to the 1/2 frame buffer, and subsequently, the CRT controller responds to the wait signal by the wait signal. In the period during which the operation is suspended, a frame buffer interface that reads display data of a line that is 1/2 frame apart from the display data written immediately before from the 1/2 frame buffer, and according to the panel up / down switching signal Display data output from the panel data conversion circuit Panel display control apparatus characterized by comprising a data control circuit for outputting the display data output from the 1/2 frame buffer selected alternately for each line in the panel display.