JPH0370431B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a pixel density conversion device that enlarges or reduces an image to a predetermined magnification by pixel density conversion, and more specifically, the present invention relates to a pixel density conversion device that enlarges or reduces an image to a predetermined magnification by pixel density conversion, and more specifically, when an original image is projected onto a converted image plane, the center of a pixel of interest on the converted image plane is The present invention relates to a pixel density conversion device that performs pixel density conversion by determining the density of the pixel of interest from the position of a point and the pixel density of the original image near the center point. In facsimile machines and intelligent copying machines with editing functions, images are read and recorded via electrical signals, but when allocating the entire image or part of it to a specific area, it is necessary to use a predetermined magnification. It becomes necessary to enlarge or reduce the entire image or a portion thereof (that is, perform a scaling operation). In addition, in image transmission systems, the size of the original image and the recorded image after transmission may differ due to differences in scanning line density between input and output devices, and pixel density conversion is used to correct this. Needed. As a method for enlarging or reducing an image in such a case, pixel density conversion methods such as the SPC method and the 9-division method have been proposed. However, in the SPC method,
"missing" (missing black pixels) is noticeable in the reduced image,
The 9-division method has drawbacks such as thicker lines in both enlarged and reduced images. Therefore, a new projection method has been proposed, which is pixel density conversion that belongs to so-called geometric mode conversion. In this projection method, the density of the converted image and the original image are almost equal, and there are few changes such as connection or separation of graphic components due to increase or decrease of black pixels, and it can obtain better image quality than the above two methods. It is known. However, even the projection method requires a large amount of calculation processing, and for this reason, conventional devices require a complicated hardware configuration and require a lot of time for calculation processing. In order to solve the problems of the above-mentioned projection method, the applicant published the "Method of enlarging and reducing images by pixel density conversion" dated December 4, 1981 (hereinafter referred to as "high-speed projection The company has filed a patent application for the new law. Furthermore, the company filed a patent application for a ``pixel density conversion device'' on March 5, 1981, as a very effective device for carrying out this scaling method. The present invention is an attempt to further improve the pixel density conversion device disclosed in these patent applications and to simplify the device. The present invention is based on the center point Ro of the transformed pixel in the transformed image.
Four original pixels (A, B,
The original pixel plane surrounded by the center points (Ao, Bo, Co, Do) of C, D) is such that the value of the converted pixel depends on the value of any one of the four original pixels. The four determined areas (first area group) and the four areas
It is divided into four areas (second area group) determined from all the values of the original pixels, and it is determined where the center point Ro of the converted pixel is located in the eight areas, and When the center point Ro is located within the first region group, the value of the converted pixel is converted to the value of the original pixel closest to the center point Ro of the converted pixel, and the center point Ro of the converted pixel is If it is located within the area of the second area group, the value of the converted pixel is calculated using the following logical calculation formula: IR=IH・(IJ+IK+IL)+IJ・IK・IL where IR: Value of the converted pixel IH: Center point of the converted pixel Value of the original pixel closest to Ro IJ.IK.IL: Value of each of the three original pixels excluding the original pixel closest to the center point Ro of the converted pixel Here, IH, IJ, IK, IL are the values mentioned above. Pixels A, B,
It corresponds to any of the values IA, IB, IC, and ID of C and D, and "." indicates logical product, and "+" indicates logical sum. In a pixel density conversion device characterized by converting based on the pixel density conversion magnification m/n (where m: a constant natural number regardless of the conversion magnification,
n: a natural number that is a variable for giving a desired conversion magnification), and a period m indicating in which divided area the center point of a pixel on the converted image plane is located.
a first storage means in which a signal of 1 is written corresponding to each magnification, and a second storage means in which a signal with a period m for selecting a predetermined square area is written in correspondence to each magnification.
storage means, for causing the pixel determination section to select a logical operation formula for calculating converted pixel density based on the output of the first storage means, and further for performing a logical operation based on the output of the second storage means. The present invention is characterized in that a necessary pixel density signal of the original image is supplied to the pixel determination section. Hereinafter, the present invention will be explained in detail using the drawings. The device of the present invention also basically adopts the idea of high-speed projection method, and first, we will take as an example the case of enlargement (including the same magnification) where the conversion magnifications p and q in the horizontal and vertical directions are 1 or more. For this purpose, we will explain the high-speed projection method. Figure 1 shows pixels of the original image (referred to as original pixels in the present invention) A, B, C, and D (Ao, Bo, Co, and Do indicate the center points of original pixels A, B, C, and D, respectively). and a pixel of the converted image (referred to as a converted pixel in the present invention) R
(Ro indicates the center point of the converted pixel R). In the high-speed projection method, in this figure 1, the center point of the converted pixel
Depending on where Ro exists within the square area connecting the center point of the original pixel, Ao, Bo, Co, and Do,
This is to calculate the density of the converted pixel R. Specifically, the square area is divided into eight parts, and for each divided area, the density of the converted pixel R is calculated from the original pixels A, B,
A logical operation formula for calculation from the densities of C and D is prepared in advance, and a predetermined logical operation formula is selected depending on the position of the center point Ro of the converted pixel R. In Fig. 2, an example is shown in which the square area connecting the center points Ao, Bo, Co, and Do is divided into eight parts.
It is shown on the x, y coordinates (here, the center point
The coordinates are determined so that Ao, Bo, Co, and Do exist in the second, third, fourth, and first quadrants, respectively, on the x and y coordinates.) Among the boundaries of these eight divided regions, the boundaries excluding the straight boundaries of X=O and y=O, that is, the divided regions,
The boundaries separating , , and are determined by curves shown by the following equations (a), (b), (c), and (d), respectively. (1/2-px) (1/2+qy)=1/2...(a) (1/2-px)(1/2-qy)=1/2...(b) (1/2+px)(1/ 2-qy)=1/2...(c) (1/2+px)(1/2+qy)=1/2...(d) Also, according to the high-speed projection method, the center point R of the converted pixel R is, for example, When located in the divided area, the density IR of the converted pixel R is given by the logical expression IR=IA・(IB+IC+ID)+IB・IC・ID. However, IA, IB,
IC and ID indicate the density of original pixels A, B, C, and D, respectively, and are 1 in the case of a black pixel and 0 in other cases. Also, . means logical product, and + means logical sum. Table 1 below summarizes the logical operation expressions for each of the eight divided areas.

【table】

[Table] In other words, in the high-speed projection method, the logical operation expressions listed in Table 1 or other logical operation expressions are written in advance in the storage means, and depending on where the center point Ro of the converted pixel R is located, A predetermined logical operation formula is selected to obtain the density IR of the converted pixel. In the apparatus of the present invention, the density determination of the converted pixel is not only performed as described above, but also the conversion magnification is selected to be m/n as described above, thereby simplifying the circuit configuration. To give an example, of the conversion magnification m/n, m=16
and n=8 to 23. In this way, the positional relationship between the converted pixel and the original pixel (thereby,
It is possible to know at which position on the original image plane the original pixels are to be used as the original pixels A, B, C, D, and in which divided area within the square area the center point Ro of the converted pixel R is located) with a period of m. = 16, so this positional relationship can be easily known. Below, this situation will be explained separately for the cases of reduction and enlargement. () When reducing (m=16, n≧17) For example, when the magnification is set to 16/20, the center point (x mark) of the converted pixel (broken line) and the original pixel (solid line) as shown in Figure 3. A shift from the center point (○ mark) will occur. Therefore, in this example, the four original pixels used to calculate the converted pixel density are
(The period is 4, which is smaller than 16, but this is because 16/20 can be reduced to 4/5, so in principle can be considered as period 16). 0001000100010001...(1) Here, 0 means to use four original pixels at a position shifted one position to the right, and 1 means to use four original pixels at a position shifted two positions to the right. Therefore, in this case, the first converted pixel density calculation (at the start of processing) uses the first four original pixels, and the second to fourth converted pixel density calculations shift to the right one by one. The calculation of the converted pixel density for the 5th time uses the original pixels (4 pieces) at the position that was shifted to the right from the 4th time, using the original pixels (4 pieces) at the position further shifted 2 places to the right from the 4th time. The operations from to the fifth time will be repeated. Similarly, the rules for the vertical direction (y direction, ie, sub-scanning direction) are as follows. 0001000100010001...(2) During reduction, the shift amounts corresponding to 0 and 1 of each digit are the same regardless of the conversion magnification. However, the arrangement of 0 and 1 differs depending on the conversion magnification. The shift amount in the case of equal magnification is also the same as in the case of reduction (in this case, all digits become 0). On the other hand, if the divided areas for reduction are formed as shown in FIG. 4, the center points of the converted pixels will be located in the divided areas with periodicity as shown in FIG. () When enlarged (m=16, n≦15) Figure 6 shows the center point (X mark) of the converted pixel (broken line) and the center point (○ point) of the original pixel (solid line) when enlarged to 16/12. The four original pixels to be used are selected according to the following rules. Horizontal direction 0010001000100010 ...(3) Vertical direction 0010001000100010 ...(4) However, unlike when reducing, 1 in each digit means to use the four original pixels used immediately before, and 0 means to use the position shifted by one to the right. This means using the original pixels of Furthermore, if the divided regions in this case are formed as shown in FIG. 7, the center point of the converted pixel will be located in each divided region with periodicity as shown in FIG. In the device of the present invention, the information shown in (1) to (4) and FIGS. 5 and 8 (information about the total magnification) is stored in the ROM.
(read-only memory), etc., and can be output as appropriate, so there is no need to calculate the positional relationship between the converted pixel and the original pixel each time the converted pixel density is calculated. This eliminates the need for an arithmetic circuit for calculating positional relationships and increases processing speed. By the way, the number of bits required to write this information to ROM etc. is m =
In the case of the above example of 16, the conversion magnification for one set of vertical and horizontal directions is 16+16+3×16 ² . However, 16 of the first item
is the number of bits for writing data such as (1) or (3), the second item 16 is the number of bits for writing data such as (2) or (4), and the third item is the number of bits for writing data such as (2) or (4). This is the number of bits for writing the data in the matrix of the divided area shown in Figure 8 (it is multiplied by 3 because 3 bits are required to express ~). Therefore, if 16 different magnifications can be set independently in the horizontal and vertical directions, the number of bits will be 16 ² +16 ² +3×16 ⁴ . Next, a specific embodiment of the present invention will be described using FIG. 9. Here, it is assumed that the original image is composed of a matrix of W pixels in the horizontal direction and L pixels in the vertical direction, and the conversion magnification is p in the main scanning direction and q in the sub-scanning direction, and the converted image is Wout×Lout Suppose that it is given by a pixel matrix of . In this case, Wout and Lout are as follows. () When reducing Wout=[pW], Lout=[qL] () When enlarging Wout=[pW-1-Δ], Lout=[qL-1-Δ] However, the symbol [ ] means truncation of the decimal part. However, Δ refers to a very small number. In FIG. 9, a storage section 311 is provided in the input buffer section 31, and this storage section 311
is three RAM (Random Access Memory)
It is composed of 311A, 311B, and 311C. Furthermore, in the input buffer section 31, these
Input counter 312, which sets the address when writing the original image signal (input data) to RAM;
A read counter 313 that sets the address when reading data from RAM, an input row counter 314 that checks that all rows of data have been input, and a designated
Input counter 312 or read counter 3 to RAM
an address multiplexer 316 that supplies the address signal output from 13, and an input buffer section 31;
A data multiplexer 315 is provided, which constitutes the final stage of the RAM and outputs a signal read from a designated RAM to the next stage. Note that the input counter 312 and read counter 313 are set to W at the start, and the input row counter 314 is set to L. 32 is a pixel determination section that receives the output of the input buffer section 31 via flip-flops F/F1 to F/F4, and 33 is a timing generation circuit that performs various timing controls. This timing generation circuit 33 is connected to an output counter 331 to which the aforementioned Wout is initially set and an output row counter 332 to which Lout is initially set. 34 is an original pixel position output section, and 35 is an area output section. This original pixel position output unit 34 outputs a signal indicating the position of the four original pixels necessary for calculating the converted pixel density, and it outputs a signal indicating the position of the four original pixels necessary for calculating the converted pixel density. ) is written in the ROM 341 corresponding to the conversion magnification in the number corresponding to the type of conversion magnification in the main scanning direction, and information indicating the position in the sub-scanning direction (for example, the data in (2) above) is stored in the ROM 341 in accordance with the type of conversion magnification in the main scanning direction. ROM 342 written in correspondence with the conversion magnification as many as the number according to the type of conversion magnification, and these
It is composed of shift registers 343 and 344 into which the outputs of the ROMs 341 and 342 are input. still,
In this example, the magnification m/n is m=16, n=8~
23, and there are 16 types of conversion magnification, so the signal giving each conversion magnification in the main scanning direction and the sub-scanning direction is composed of 4 bits. and,
Each signal serves as an address input for ROM341, 342, and also serves as an address input for ROM341, 342.
The 16-bit output of 2 is sent to the shift register 343,
The signals are parallel-to-serial converted in step 344, and then input to the timing generation circuit 33 one bit at a time while being rotated. Area output section 3
Reference numeral 5 outputs a signal indicating which of the above regions . In this embodiment, a ROM and a shift register are provided for each bit. That is,
ROM351-353 and shift register 354
~356. 3 ROM351
353, the matrix shown in FIGS. 5 and 8 described above (as described above, each element of this matrix represents a divided area, so its configuration is 3 bits), Each element is decomposed into three matrices represented by one bit: a matrix made up of the most significant bit, a matrix made up of intermediate bits, and a matrix made up of the least significant bit.
The number is written according to the product of the two types of conversion magnification. Since the matrix to be used is specified only after the conversion magnification in the main scanning direction and the sub-scanning direction is given, the signals P and Q of the conversion magnification in the main scanning direction and the sub-scanning direction are input as addresses to the RAMs 351 to 353. constitutes part of. Furthermore, in order to specify which row of the matrix is to be used, the output of a hexadecimal counter 36 that counts the line feed clock CK3 is also given as part of the address input. For this purpose, the address input terminals of the ROMs 351-353 are composed of 12 bits. Shift registers 354 to 356 are ROM3
The outputs of 51 to 353 are subjected to parallel/serial conversion, further rotated, and outputted to the pixel determination section 32 as a 3-bit divided area signal. In addition, the shift register 34
3,354 to 356 are line feed clock signals CK3
and the shift clock signal CK2
The shift register 344 is connected to the timing generation circuit 33 so as to be shifted by the start clock signal CK4, and to be shifted by the line feed clock signal CK3. Furthermore, counter 36 is connected to be reset by start clock signal CK4. In addition, in the case of the above embodiment, the conversion magnification is indicated by 4-bit signals P and Q (16/8 times corresponds to 1111, and 1
6/23 corresponds to 0000. ), when the MSB is set to "1", it is enlarged, and in other cases, it is reduced (including the same size). Therefore, the timing generation circuit 33
is a signal indicating this MSB for expansion/reduction judgment
This is done by inputting PA ₃ and QA ₃ . In addition, from the timing generation circuit 33 to the data multiplexer 315 and the address multiplexer 31
By the select signal (S ₁ , S ₀ ) to
The states that 311A, 311B and 311C take are:
It is as shown in Table 2.

[Table] Prohibited when (S ₁ , S ₀ ) is (1, 1). In addition, the outputs DA, DB and DC of RAM311A, 311B and 311C and data multiplexer 3
The relationship between the outputs D ₁ and D ₂ of No. 15 is as shown in Table 3.

[Table] The operation of the embodiment of the present invention configured as above will be described below. First, the timing generation circuit 33 sends select signals (S ₁ , S ₀ ) to the address multiplexer 315.
are set to (O, O), the ready signal (low active) indicating that the original image signal may be output to an external device is set to "0" (Low), and the input enable signal is set to "1". . Therefore, in this initial state, the RAM 31
1A, pixel data is applied pixel by pixel to each RAM 311A in synchronization with the input strobe signal, and is sequentially written to the RAM 311A in accordance with the write strobe signal.
In addition, for each writing of one pixel, the timing generation circuit 3
3 is a counter 31 that inputs the clock signal WCLK.
2 and counts down by 1, so the information for 1 line (W pixels) is stored in RAM 31.
It is stored from address W to address 1 of 1A. The output of the input counter 312 when one line is input and the count value becomes 0 is detected by the timing generation circuit 33 as a one line input end signal. As a result, the timing generation circuit 33 sets the ready signal to "1", presets the count value of the input counter 312 to W, and also sets the count value of the input row counter 31 to "1".
Subtract 1 from 4. At the same time, (S ₁ , S ₀ ) are set to (0, 1). Therefore, input counter 312
The output of the RAM 311B and the write strobe signal of the timing generation circuit 33 are now applied to the RAM 311B. After this switching, the timing generation circuit 33 sets the ready signal to "0" to enable input of the W pixels in the second row, and transfers the pixel data in the second row to the RAM 311B at the same timing as the pixel data in the first row. Write. When writing of the pixel data on the second row is completed, the timing generation circuit 33 changes (S ₁ , S ₀ ) to (1, 0).
Then, the output of the input counter 312 and the write strobe signal are input to the RAM 311C (however, the ready signal is "1" at this point). Also, at the same time, the start clock CK
4. By line feed clock CK3, ROM341,
The outputs of ROM 342 and ROMR 351 to 353 (since the magnification signals P and Q are address inputs, they correspond to the set magnification),
Shift registers 343, 344 and 354-35
Write in 6. After this, the ready signal becomes "0" and writing of the third row pixel data to the RAM331C starts, and the RAM311A and RAM
Pixel density conversion processing using the first and second row data stored in 311B is started. First, when (S ₁ , S ₀ ) is (1, 0), the output of the read counter 313 is
311B, and the pixel data of the first column of the first and second rows are output from both output terminals DO as output signals DA and DB. this
The DA and DB signals are output from the data multiplexer 315 as D ₁ and D ₂ signals, respectively. Therefore, the timing generation circuit 33 latches the signals D ₁ and D ₂ to the flip-flops F/F1 and F/F2 using the shift clock signal CK1, and
Read counter 3 by outputting clock signal RCLK
1 is subtracted from the count value of 13, and the pixel data of the second column is output from the RAM 311A and RAM 311B. After that, the shift clock is further output to flip-flops F/F1 to F/F4 to transfer and latch the pixel data of the first column to flip-flops F/F3 and F/F4.
Let F1 and F/F2 latch the pixel data of the second column. The pixel data of the first four points are now arranged in the flip-flops F/F1 to F/F4, and this pixel data is input to the pixel determination section 32. The pixel determination circuit 32 includes shift registers 354 to
From the output of step 356, it is determined in which region of the divided regions ~ the center point of the converted pixel is located, and the result of the corresponding calculation in Table 1 is output as the converted pixel value.
This completes the processing of the first converted pixel. The processing of the second converted pixel differs depending on the value of the signal PA ₃ (indicating enlargement/reduction) which is the MSB of the signal P indicating the horizontal magnification and the output IW of the shift register 343. That is, the timing generation circuit 33 takes one of the following operations () to (). ( ) When (PA ₃ , IW)=(0, 0), the pixel data of flip-flops F/F1 to F/F4 are shifted by 1 bit using the clock signal RCLK and the shift clock signal CK1. () When (PA ₃ , IW)=(0, 1), the pixel data of flip-flops F/F1 to F/F4 are shifted by 2 bits using the clock signal RCLK and shift clock signal CK1. () When (PA ₃ , IW) = (1, 1), the clock signal RCLK and shift clock signal CK1 are not output, and therefore the flip-flop F/F1
- Leave the pixel data of F/F4 as is. ( ) When (PA ₃ , IW)=(1, 0), the pixel data of flip-flops F/F1 to F/F4 are shifted by 1 bit using the clock signal RCLK and shift clock signal CK1. The timing generation circuit 33 performs the above () to
After execution of (), shift registers 343, 344, 354 to 356 are shifted by 1 bit by shift clock CK2. The pixel determination unit 32 uses the new pixel data to shift registers 354 to 354.
The calculation is performed according to the output signal of 356, and the second converted pixel value is output. Thereafter, by repeating similar operations, new converted pixel values (first row) can be obtained one after another. By the way, the output counter 331 counts down every time a converted pixel value is output. Therefore, when the output counter 331 becomes 0,
This means that only Wout pixels (for one line) are output. Next, the timing generation circuit 33 decrements the output row counter 332 by 1 when the output of the input counter 312 becomes 0 (one line input completed) and the output counter 331 becomes 0 (one line output completed). The next process is to use the signal Q that indicates the vertical magnification.
It depends on the MSB of QA ₃ (indicating expansion/reduction) and the value of the output IL of the shift register 344. () When (QA ₃ , IL) = (0, 0) (S ₁ ,
S ₀ ) to (0,0), RAM311B,
The pixel data on the 2nd and 3rd rows in the RAM311C can be read out, the ready signal is set to "0", and the pixel data on the 4th row is read out from the RAM311C.
Enable input to 11A. () When (QA ₃ , IL) = (0, 1) (S ₁ ,
S ₀ ) is set to (0, 0), the pixel data of the fourth row is input to the RAM 311A, and then (S ₁ , S ₀ )
(0, 1) and the pixel data in the 5th row
It is made so that it can be input to the RAM 311B, and the pixel data on the third and fourth rows in the RAM 311C and RAM 311A can be read out. () When (QA ₃ , IL) = (1, 1), (S ₁ ,
S ₀ ) is left as is, and the ready signal is also kept at "1".
Allows the pixel data on the second row to be read. () When (QA ₃ , IL) = (1, 0) ()
Perform the same processing as . After executing the above () to (), the line feed clock signal CK3 causes the ROM341, 351 to 353 to
The output of the shift registers 343, 354 to 35
6 and shifts the shift register 344 by 1 bit. Then, the converted pixel values in the second row are determined. Thereafter, as the pixel density conversion is performed in a similar manner, the input row counter 314 becomes 0. At this time, there is no longer any pixel data to be input, but the input enable signal is set to "0" until the converted pixel value output is completed, and 0 is written to RAM311A to 311C as if 0 had been input. Continue writing (however, the ready signal remains “1”). When the output row counter 332 becomes 0, a signal to that effect (output end signal) is input to the timing generation circuit 33, so the timing generation circuit 33 ends all processing. Note that the present invention is not limited to the above embodiments. For example, although the square area is shown divided into eight parts using equations (a) to (d), it may be divided into four parts.
Furthermore, even in the case of eight divisions, a logical operation formula different from those in Table 1 may be adopted. In short, the pixel determination section 32 may be configured with a logic circuit that performs desired logical operations. Further, as the timing generation circuit 33, it is preferable to use a microprocessor. Furthermore, the signals PA ₃ and QA ₃ were taken out from the signals P and Q indicating the conversion magnification and given to the timing generation circuit 33. However, if the configuration is such that it is not possible to determine enlargement/reduction based on the MSB, What is necessary is to separately obtain a signal indicating this and supply it to the timing generation circuit 33. Also, storage unit 3
1 was configured with three RAMs, but it can also be configured with two RAMs. As explained above, in the present invention, the conversion magnification is m/n (m, n; integer), and m is constant. Therefore, since the positional relationship between the converted pixel and the original pixel changes even at a constant (m) period, the configurations of the original pixel position output section, the area output section, etc. can be extremely simplified.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing how four original pixels and converted pixels are overlapped, Figure 2 is an explanatory diagram showing division of a square area, and Figures 3 and 6 are the center point of the original pixel and the center of the converted pixel. Explanatory diagram of the deviation from the point, Figures 4 and 7
The figure is an explanatory diagram showing an example of region division, FIGS. 5 and 8 are explanatory diagrams showing an example of region data, and FIG. 9 is a configuration diagram showing an example of the present invention. 31...Input buffer section, 311...Storage section, 31
1A, 311B, 311C...RAM, 312...Input counter, 313...Reading counter, 314...
Input row counter, 315...Data multiplexer, 316...Address multiplexer, 32...Pixel determination section, 33...Timing generation circuit, 34...Original pixel position output section, 341, 342, 351-35
3...ROM, 35...area output section, 36...counter.

Claims (1)

[Claims] 1. At the center point (Ao, Bo, Co, Do) of four original pixels (A, B, C, D) in the original image surrounding the center point Ro of the converted pixel in the converted image Thus, the original pixel plane surrounded by The center point of the converted pixel is divided into four regions (second region group) determined from all the values of the original pixel.
Determine where Ro is located in the eight regions, and if the center point Ro of the converted pixel is located within the first region group, set the value of the converted pixel to the center point Ro of the converted pixel. When the center point Ro of the converted pixel is located within the area of the second area group, the value of the converted pixel is converted to the value of the nearest original pixel using the following logical operation formula: IR=IH・(IJ+IK+IL) +IJ・IK・IL However, IR: Value of the converted pixel IH: Value of the original pixel closest to the center point Ro of the converted pixel IJ.IK.IL: 3 values excluding the original pixel closest to the center point Ro of the converted pixel Here, IH, IJ, IK, IL are the values of the original pixels A, B,
It corresponds to any of the values IA, IB, IC, and ID of C and D, and "." indicates logical product, and "+" indicates logical sum. In a pixel density conversion device characterized by converting based on pixel density conversion magnification m/n (where m: a constant natural number regardless of the conversion magnification, n: a variable for giving a desired conversion magnification) a first storage means in which a signal with a period m indicating in which divided area the center point of a pixel of the converted image plane is located is written corresponding to each magnification, and a predetermined square; a second storage means in which a signal with period m for selecting an area is written corresponding to each magnification; A pixel density conversion device, characterized in that the pixel density conversion device causes the pixel determination unit to select the pixel density, and further provides the pixel determination unit with a signal of pixel density of the original image necessary for a logical operation based on the output of the second storage means. .