JPS6184963A - Picture element density converting device - Google Patents

Abstract

PURPOSE:To eliminate necessity of many ROMs and shift registers, to reduce the number of parts of a picture density converting device and to miniaturize the device by making reading from a ROM cyclically. CONSTITUTION:RAMs 311A-311C are provided in the memory section 311 of the input buffer section 31 of a picture density converting device and an address for writing input data in the RAMs 311A-311C is set in an input counter 312. Address at the time of reading is set in a reading counter 313, and it is reported by an input line counter 314 that all lines are inputted. An address multiplexer 316 and a data multiplexer 315 are provided respectively for counters 312-314 and RAMs 311A-311C, and multiplexers 315, 316 are controlled by a timing generating circuit 33. FF1-FF4 between the multiplexer 315 and a picture judging device 32 are controlled by the circuit 33. Signals of a ROM36 and counters 34, 35 are inputted to the circuit 33, and reading from the memory section 313 is made cyclically.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pixel density conversion device that enlarges or reduces an image to a predetermined magnification by pixel density conversion. Knowing which divided area on the original pixel the converted pixel corresponds to, calculate the am of the converted pixel using a logical calculation formula for converted pixel density prepared in advance for each divided area, and perform pixel density conversion. The present invention relates to a pixel density conversion device that performs pixel density conversion.

(Prior Art) In facsimile machines and in-rigid copiers with editing functions, images are read and recorded via electrical signals, but the entire image or a part of it is divided into a specific area. If the image is attached, it becomes necessary to enlarge or reduce the entire image or a portion thereof at a predetermined magnification (by tapping the magnification change operation). In addition, in a single image transmission system, the size of the original image and the recorded image after transmission may differ due to differences in scanning line density between input and output devices. Conversion is required.

In such cases, as a method to enlarge or reduce the image,
Pixel density conversion methods such as the SPC method and the 9-division method have been proposed. However, in the SPC method, "missing" (missing black pixels) occurs independently in the reduced image, but in the 9-division method, lines become thicker in both the enlarged image and the reduced image. Therefore, a new projection method has been proposed, which is pixel density conversion that belongs to so-called geometric mode conversion. This projection method is a method in which the density of the converted image and the original M image are approximately equal, and there are few changes such as connection and separation of graphic components due to increase or decrease of black pixels, and it has better image quality than the above two methods. It is known that it can be destroyed.

By the way, this projection method also generally requires a large amount of calculation processing, and therefore requires a complicated hardware configuration and requires a lot of time for calculation processing. Therefore, in order to solve this problem, we selected the conversion magnification as a/b (a: a constant natural number regardless of the conversion magnification, b: a natural number that gives the desired conversion 1g rate, I: the second variable), and The present applicant has already proposed to simplify the process and speed up the processing (Japanese Patent Application No. 145389/1989). This is done by focusing on the fact that by selecting a constant as described above, the position of the divided area corresponding to each successive converted pixel and the original pixel selection rule ill change at a period of a. This configuration uses a shift register to load divided area data and original pixel selection data.

(Problem to be Solved by the Invention) However, in such a configuration, the number of bits necessary to express the divided area plus 2 (for example, the number of divided areas cannot be expressed with 3 bits is 8). Then this number is 5
A ROM and a shift register are required, respectively, and there is a problem that the number of parts increases and the space occupied increases.

The present invention has been made in view of the above problems, and an object thereof is to provide a pixel density conversion device that can reduce the number of parts and save space. .

(Means for Solving the Problems) The present invention that solves the above-mentioned problems is to know which divided area on the original pixel the converted pixel corresponds to when the converted image is projected onto the original image, and to In a pixel density conversion device that calculates the density of the converted pixel using a logical operation formula for calculating the converted pixel density prepared in advance for each pixel and performs one pixel density conversion,
When the pixel density conversion magnification is m/n (-, n are both natural numbers), divided area data with period l indicating which divided area the converted pixel corresponds to and converted pixel density using the logical formula A semiconductor memory that stores original pixel selection data with a cycle m for selecting original pixels necessary for calculation, a first m-ary counter that counts the lock signal for resetting and is reset by the start clock signal, and a shift clock signal. a second m-adic counter that is reset by a lock signal for counting and resetting, the outputs of the first and second counters and the signal indicating the conversion magnification are used as address inputs of the semiconductor memory, and the semiconductor memory This is characterized in that 1q of divided area data and original pixel selection data are stored for each converted pixel by λ412.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

First, before explaining this embodiment, regarding the projection method adopted in this embodiment 1, we will explain the expansion method in which the horizontal and vertical conversion magnifications p and q are 1 or more (including V times). Let me explain using a case as an example.

Figure 3 shows original pixels A, B, C, D (80, BO.

Co and Do indicate the centers of the original pixels A, B, C, and D, respectively) and the converted pixel R (Ro indicates the center point of the converted pixel R) are superimposed, that is, they are projected. ing.

In the projection method in this example, in FIG. 3, the center point Ro of the converted pixel is the center point of the original pixel, Ao, So, Go
, Do is used to calculate the density of the converted pixel R, depending on where it exists in a square area connected to Do. A logical operation formula for ejecting the density of the original pixels A, B, C, and D from the density of the original pixels A, B, C, and D is prepared, and the converted pixel R
A predetermined logical operation formula is selected depending on the position of the center point Ro.

In FIG. 4, an example of dividing the square area connecting the center points Ao, Bo, Co, and DO into eight is shown on the x and y coordinates (here, the center points Ao, Bo, Go, D
The coordinates are determined so that o exists in the second quadrant, third quadrant, fourth quadrant, and first quadrant on the x and y coordinates, respectively).

Within the boundaries of the divided regions of these 8 divided areas
Boundary excluding straight line boundary of Q and y=0, that is, divided area■
and ■.

The boundaries separating ■ and ■, ■ and ■, and ■ and ■ are determined by curves shown by the following equations (a), (b), (c), and (d), respectively.

(1/2-OX)<1/2+QV)=1/2・ (A)
(1・'2-IIX) (1/2-l) -1/2...
・(b) (1/2-z+x) <1/2-ay)-1/
2...(c)(1/2+1)X)(1/2+qy)=
1/2...(d) Also, according to the projection method in this example, when the center point Ro of the converted pixel R is located in the divided area ■, for example, the density IR of the converted pixel R is IR=[△・(IB+ IC+ ID>+IB-IC-
It is given by the logical expression ID. However, IA, (B, I
C and ID are original pixels △ and [3, C, respectively.

It indicates the density of D, which is 1 for a black pixel and O for that pixel. Also, ・is theory I! J+product, -← means logical sum.

The logical equations for determining the direct IR of the converted pixel for each of the eight divided areas are summarized as follows.

If the Ro position is ■; IA If the Ro position is ■;] B If the RO position is ■; IC If the Ro position is ■; ID If the Ro position is ■; IA・(IB+IC+ID) +If the position of IB・IC・IDRo is ■; IB・(IC+ID+rA)+IC・
ID ・ If the IARo position is ■: IC・ (ID + IA - IB) + ID ・
IA・I [If the position of 3Ro is ■; ID・(IA+ IB+ IC>+ IA・IB−IC
That is, in the projection method in this example, the above logical operation formula listed in the table or other logical operation formulas are written in the storage means in advance, and a predetermined logical operation is performed depending on where the center point RO of the converted pixel R is located. Select the formula and convert the density I of the pixel
I'm getting an R.

In the device of this embodiment, not only the temperature determination of the conversion pixel is performed as described above, but also the conversion magnification is selected as <m/n as described above.

For example, let us determine the conversion magnification n+/n.

n is m-16, and n=8 to 23.

In this way, the positional relationship between the converted pixel and the original pixel (thereby, the original pixel at which position on the original image surface is used as the original pixels A, B, C, D, but also the center point of the converted pixel R) R
Which division region 1ii in the square region is o? ) changes at a period of +11=16, so this positional relationship can be easily known.

Below, this situation will be explained separately for the cases of reduction and enlargement.

(I>When reducing (m=16.n≧17) For example, when the magnification is set to 16/20, the solid line between the center point (X mark) of the original pixel (broken line) and the converted pixel as shown in Figure 5. ) and the center point (○ mark). Therefore,
In this example, the four original pixels used to calculate the converted pixel density are changed in the horizontal direction (
x direction, that is, the main scanning direction) according to the next current 1111 (the period is 4, which is smaller than 16, but this means that 16/20 is 415
This is because it can be reduced to , and in principle, it can be considered to have a period of 16).

0001000100010001... (1) Here, 0 means to use the four original pixels at the position shifted one place to the right, and 1 means to use the four original pixels at the position shifted two places to the right. means. Therefore, in this case, 1
The calculation of the converted pixel density for the first time (at the start of processing)
Calculation of the converted pixel density from the second to the fourth time using one original pixel uses the original pixels (four) at positions shifted one by one to the right, and calculates the converted pixel density of the fifth time. The calculation is based on the original pixel (
4), and the second to fifth movements are repeated.

Similarly, the rules for the vertical direction (y direction, ie, sub-scanning direction) are as follows.

0001000100010001... (2) During reduction, the shift amount corresponding to 0.1 of each digit is the same regardless of the conversion magnification.

However, the arrangement of 0.1 differs depending on the conversion magnification. The shift m in the case of equal magnification is also the same as in the case of reduction (in this case, all digits become O).

On the other hand, if the divided regions (■ to ■) at the time of reduction are formed as shown in FIG. 6, the center point of the converted pixel will be as shown in FIG.
It is located in the divided area with a periodicity of 16.

(II) When enlarged (m = 16. n'; -15) Figure 8 shows 16. This shows the positional relationship between the center point (0 mark) of the original pixel (Vi line) and the center point (0 mark) of the converted pixel (solid line) when enlarging /12.The selection of the four original pixels to be used is , according to the following rules.

Horizontal direction 0010001000100010...(3) Vertical direction 0010001000100010...-(4) However,
Unlike during reduction, 1 in each digit means that the four original pixels used immediately before are used, and 0 means that the original pixel at the position shifted by one to the right is used.

Furthermore, if the divisions fA 1 to 2 in this case are formed as shown in FIG. 9, the center point of the converted pixel will be located in each division area with periodicity as shown in FIG.

In this practical reconstruction, the original pixel selection data shown in (1) to (4) etc. and the divided area data (information about the total magnification) shown in Figs. 6 and 9 etc. are allocated to ROM etc. Since the information is stored in advance and can be output as appropriate, there is no need to calculate the positional relationship between the converted pixel and the original pixel each time the converted pixel density is determined. This eliminates the need for a calculation circuit for calculating positional relationships and increases processing speed.

Next, a detailed explanation of the embodiment shown in FIG. 1 will be given.

Here, it is assumed that the original image is composed of W pixel matrices in the horizontal direction and @1 pixel matrix, and the conversion magnification is set to p in the main scanning direction.
, the sub-scanning direction is q, and the image after conversion is wout
Suppose that it is given by a pixel matrix of L out. In this case, Wout and Lout are as follows.

(I) When reducing Wout − [p W], Lout − [q L
] (n) Wout = [pW −1−Δ] at the time of expansion.

Lout - [Q L -1 - Δ1 However, the symbol [] means rounding down the decimal part, and Δ indicates a very small number.

In FIG.
1 is provided, and this storage section 311 stores three RAs.
It is composed of M311Δ, 311B, and 311C.

Further, in the input cover 7 section 31, there are an input counter 312 for setting the address when writing the original image signal (input data) to these RAMs, a read counter 313 for setting the address when reading from the RAM, all rows. An input row counter 314 for knowing that data has been input, an address multiplexer 316 that supplies the address output from the input counter 312 or read counter 313 to a designated RAM, and constitutes the final stage of the input buffer section 31. A data multiplexer 315 is provided for outputting a signal read from a designated RAM to the next stage. Note that the input counter 312 and read counter 313 are set to W at the start, and the input row counter 314 is set to L.

32 inputs the output of the input buffer section 31 to a 7-rip flop F.
/F1 to Pixel determination unit receiving via F/F4, 3
3 is a timing generation circuit that performs various timing controls. This timing generation circuit 33 includes the above-mentioned Wou
An output counter 331 to which t is initialized, and l out
An output row counter 332 is connected to which the output line is initialized.

In addition, in the case of the above embodiment, the conversion rate is the 4-bit signal P.
, denoted by Q (16/8 times corresponds to 1111 and 16/2
3 corresponds to oooo), when 1" is set in the MSB, it will be enlarged, and in other cases, it will be reduced (including the same size). Therefore, the timing generation circuit 33 makes a judgment of enlargement or reduction based on this MSB. By inputting the signal PA3.QA3 indicating the

Note that the RAM 311A is
, 311B and 311C are as follows.

(StSo) 311A 3118 311C (0
,O) Write Read Read 0.1>
Readout Interpretation Readout 1. O) Read Read Write (1, 1) --- However, it is prohibited when (St, So) is (1, 1>).

Also, the output OA of RAM311A, 311B and 311C
, DB and DC and the output D of the data multiplexer 315
The relationship between 1 and D2 is as follows.

(, St, So) DI D2<0,
0) DB DC (0, 1) DCDA (1, O) [)A 08 The operation of the embodiment of the present invention configured as described above will be described below.

First, the timing generation circuit 33 sends a select signal (St, SO> to the address multiplexer 315 as (
0, O), and the ready signal (low active) indicating that the original image signal may be output to an external device is set to O" (L
OW) and set the input enable signal to 1''.

Therefore, in this initial state, data is written into the RAM 311A, and pixel data is applied to each RAM one pixel at a time in synchronization with the input strobe signal, and is sequentially written into the RAM 311A by the write strobe signal.

Note that for each writing of one pixel, the timing generation circuit 33
The clock signal WCLK is applied to the input h-rantaco 312, and it is counted down by 1, so one line (
Information on pixel W) is stored at addresses W to 1 of the RAM 311A. The output of the input counter 312 when one line is input and the count value becomes O is detected by the timing generation circuit 33 as a one line input end signal.

As a result, the timing generation circuit 33 sets the ready signal to "1", presets the count value of the input counter 312 to W, and decrements the input row counter 314 or 61. At the same time, (St , So ) is (0,1>
shall be. Therefore, the output of the input counter 312 and the 11-inclusive strobe signal of the timing generation circuit 33 are now applied to the RAM 311 F3.

After this switching, the timing generation circuit 33 outputs the ready signal.
Set to "O" to enable input of the W pixels in the second row, and write the pixel data in the second row to the RAM 31181.: at the same timing as the pixel data in the first row.

When the writing of the pixel data on the second row is completed, the timing generation circuit 33 sets (St, So) to (1°O) and inputs the output of the J counter 312 and the input/output strobe signal to the RAM 311C. (However, the ready signal is 1' at this point.

). Also, at the same time, the start clock CK4
．． The counters 34 and 35 are reset by the new lock CK3. After this, the ready signal becomes "O" and the pixel data of the third row starts to be loaded into the RAM 331C, and the data of the first and second rows stored in the RAM 311Δ and RAM 311B are used. The pixel density conversion process that was performed is then started.

First, when (S+, So) is (1, 0>), the output GJ of the read counter 313: RAM 311A and [AM
311B, and the pixel data of the 1st row, 271st column, and the 271st column are output from both output terminals Do as output signals OA and DB. From this OA and DB double signal data multiplexer 315, D'1. D
z Output as a low signal.

Therefore, the timing generation circuit 33 uses the shift clock signal CK1 to divide the signals D+ and D2 by 7 rip 70.
It latches into the knobs F/Fl and F/F2, and outputs the input signal @RCLK to make the read counter 313 count 1.
Subtract 1 from the pixel data of the second column and save it to RAM311A.
and output from RAM 311B.

After this, the shift clock signal CK1 is further flipped 70
Output the pixel data of the first column to the knobs F/F1 to F/F4 and flip 70 knobs F/F3. It is transferred to F/F4 and latched, and the flip 70 knob F/F1. Let F/F2 latch the pixel data of the second column. Now the first 4 points of side tree data are 7 lip flops F/Fl~I:,/
Since it is before F4, this pixel data is sent to the pixel determination unit 3.
2.

From the output []ΔD of the ROM 36, the pixel determination circuit 32
It is determined in which region of the divided regions (1) to (2) the center point of the converted pixel is located, and the result of the operation corresponding to the logical formula J is output as the converted pixel value. With this, the processing of the first converted pixel is completed.

The processing of the second converted pixel is the signal @P which indicates the horizontal magnification.
It varies depending on the value of the signal PA3 (indicating enlargement/reduction) which is the MSR of , and the value of the output IW of the ROM 36. That is, the timing generation circuit 33 takes one of the following operations (I) to (rV).

(I>(RAM, IW) = (0,0) limit []
Using the clock signal RCLK and the shift clock signal CK1, the pixel data of the flip 70 blocks F/F1 to F/F4 are shifted by one bit or more.

(II) (RAM, IW>-(0,1>) Using the clock signal RCLK and shift clock signal CK1, change the pixel data of flip-flops F/Fl to F/F4 into 2
Pitsu 1 ~ Shift.

(III) When (PAs, IW) - (1, 1), the clock signal @RCLK and shift clock signal CK1 are not output, and therefore the pixel data of flip-flops F/F1 to F/F4 are left as they are.

(IV) When (RAM, rW) = (1, O), then O
The pixel data of the flip-flops (:2/F1 to F/F4) is shifted by one pit using the clock signal RCLK and the shift clock signal CKI.

After executing steps (I) to (IV) above, the timing generation circuit 33 outputs the shift clock signal CK2 and increments the count value of the counter 35 by one (the ROM 3
6). Pixel determination unit 3
2 is the output D of the ROM 36 using the new pixel data.
Perform the operation i according to AD and output the converted pixel value of No. 2 1.

Thereafter, by repeating similar operations, new converted pixels 1i1T (first row) can be obtained one after another.

Tokorohi, every time a converted pixel value is output, the output counter 3
31 counts down. Therefore, when the output counter 331 becomes O, the wout pixel (for one line)
This means that only Next, timing generation circuit 3
3, when the output of the input counter 312 becomes 0 (one line input completed) and the output of the output power counter 331 becomes O (one line output completed), the output line counter 332 is decremented by one.

The next processing is Q, which is the MSB of the signal Q indicating the vertical magnification.
As (indicates expansion/reduction) and ROM36 output IL
Depends on the value of

(1) (QAs, fL) - (0,0) (7)! :! (
S+, So) to (0, 0>) and RAM311B, R
2nd line in AM311C.

Make it possible to read the pixel data on the third row, set the ready signal to "O'°, and transfer the pixel data on the fourth row to the RAM.
Enable input to 311△.

(II) When (QAa, IL) = (0, 1>) (S+
, So ) are set to (0, O), the pixel data of the fourth row is input to the RAM 311 Δ, and (S+ , So ) is set to (0, 1), the pixel data of the fifth row is input to the RAM 311 Δ.
In addition to making it possible to input to B, RAM311C,R
The pixel data on the third and fourth lines in AM311A can be read out.

When (Il[)(QAx,IL) −(1,1)
s, So) as they are, and the ready signal is also 1"
1st line, 2 in RAM311A, RAM311B
Make it possible to read the pixel data of the row.

([V) (QA3 , [L) - (1,0) (7) when (
Perform the same process as 1).

After executing steps (r) to (IV) above, the timing generation circuit 33 outputs a new lock signal CK3, and the counter 34
The counter 35 is incremented by one and the counter 35 is reset. Converted pixel values for the second row are determined in the same way as for the first row.

The input row counter 314 becomes O as the pixel density conversion is performed in a continuous manner. At this time, there is no more pixel data to be input, but the input enable signal is set to 0'' until the output of the 9-converted pixel value is completed, and the RAM 311A to 31
Continue writing O to 1C (however, the ready signal remains 1''). Then, when the output row counter 332 becomes O,
A signal to that effect (output end signal) is sent to the timing generation circuit 3.
3, the timing generation circuit 33 ends all processing.

Note that the present invention is not limited to the above-mentioned embodiments; for example, the conversion magnification m/n of copper does not need to be constant, and m may be configured to vary depending on the magnification signals P and Q. .

This can be easily constructed by using a binary counter (maximum value of k≧m) and a PLA (Programmatical Logic Array).

FIG. 2 shows this example, where 37.38 is the decimal counter and 39.40 is the PLA. This P LA39.4
0 selects the value of l according to the magnification signals Q and P, respectively, and the k-ary counters 39 and 40 function as . . .-ary counters. That is, when the output of the counters 39 and 40 exceeds m-1, counting starts from O. In addition, the square area was divided into 8 degrees using equations (a) to (d), but 4
It may be divided. Furthermore, even in the case of 8 divisions, a logical operation formula different from the one described above may be adopted (
There is no need to limit the number of reference pixels to 4gl).

In short, the pixel determination section 32 may be configured with a logic circuit that performs desired logical operations. Further, as the timing generation circuit 33, it is preferable to use a microprocessor. Furthermore, it does not indicate the conversion magnification, and from the signals P and Q, the Ig signal P
A3.0A3 was taken out and given to the timing generation circuit 33, but if the configuration is such that expansion/reduction cannot be determined based on the MSB, a signal indicating expansion/reduction is separately provided in advance.
This can be sent to the timing generation circuit 33. Further, although the storage section 31 is configured with three RAMs, it can also be configured with two RAMs.

(Effects of the Invention) As explained above, according to the present invention, reading from a ROM (semiconductor memory) is performed cyclically, so there is no need to use a large number of ROMs and shift registers as in the past, and We were able to reduce the number of points and save space.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing main parts of another embodiment of the present invention, and Fig. 3 is a state in which four original pixels and converted pixels are overlapped. FIG. 4 is an explanatory diagram showing the division of a square area, FIGS. 5 and 8 are explanatory diagrams of the deviation between the center point of the original pixel and the center point of the converted pixel, and FIGS. 6 and ≦) The figure is an explanatory diagram showing an example of region division, and FIGS. 7 and 10 are explanatory diagrams showing examples of region data. 11.12...Shift register 13...Multiplexer 31...Input buffer section 311...Storage section 311Δ, 31 1B, 31 1C...RA M31
2...Input counter 313...Reading counter 314...-Manual row counter 315...Data multiplexer 316...Address multiplexer 32...Pixel determination unit 33...Timing generation circuit 34.35. 37.38...Counter 36・ROM
39.40・PI-A Patent Requester Roku Konishi Photo Industry Co., Ltd. Agent Patent Attorney I
Shima Fuji Jigai 1 figure 3 figure Δ Hanging 4 figure 5 figure 6 figure - 11111 horizontal direction 1 5841 584158415B41 58415
B415841 584 Figure 8 Fragment 9 Bile Lateral Procedure Amendment Form (Method) % Formula % 1. Indication of the Case Name of Patent Application No. 207393 filed in 1982 Relationship with the Case of Person Who Operates a Pixel Density Conversion Device Patent Issue Chin Address 1-26-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Name (127) Representative of Konishi Rokushamo Kogyo Co., Ltd. Megumi Ide, 1.1 years old, 5 years old, date of amendment order Showa January 9, 1986 (Delivery date: January 29, 1985) 6. Column 7 of Detailed Description of the Invention 2 of the specification to be amended, Contents of the amendment (1) Page 2, line 4 of the specification (2) Delete “3. Detailed description of the invention” in the second page of the specification between the fourth and fifth lines.
, "Detailed Description of the Invention". that's all

Claims (1)

[Claims] When the converted image is projected onto the original image, it is known which divided area on the original pixel the converted pixel corresponds to, and the conversion is performed using a logical operation formula for calculating the converted pixel density prepared in advance for each divided area. In a pixel density conversion device that calculates pixel density and performs pixel density conversion, the pixel density conversion magnification is m/n (m,
n is a natural number), divided area data with a cycle m indicating which divided area the converted pixel corresponds to, and a cycle for selecting original pixels necessary for calculating the converted pixel density using the logical operation formula. a semiconductor memory that stores m original pixel selection data, a first m-ary counter that counts the lock signal to be changed and is reset by the start clock signal, and a first m-ary counter that counts the shift clock signal and is reset by the lock signal to be changed. 2 m-ary counters, the outputs of the first and second counters and the signal indicating the conversion magnification are used as address inputs of the semiconductor memory, and the divided area data and original data corresponding to each converted pixel are transmitted from the semiconductor memory. A pixel density conversion device characterized in that pixel selection data is obtained.