JPS61152162A - Picture enlarging and reducing circuit - Google Patents

Abstract

PURPOSE:To obtain enlarged or reduced images having high quality without the generating of moires by changing the number of processing bits on the basis of a picture element size and an enlargement or reduction rate which respect to spurious half tone data. CONSTITUTION:The reduction or enlargement rate is set to a register 19, and an initial value '0' is set to a register 20. In case of reduction in the main scanning direction of the spurious half tone data, a sequencer 18 generates m-number of clocks at every respective one clock of shift clock signals 15 and 16 when a carry signal 24 is generated. When the signal 24 is not generated, the sequencer 18 generates m-number of clocks of only the signal 15. In case of enlargement of the spurious half tone data, the sequencer 18 outputs m- number of clocks of each of clock signals 15 and 16 to transfer and copy m-bit contents of the resister to a register 13 when the signal 24 is not generated. When the signal 24 is generated, the m-bit contents of the register are shifted to the register 13, and the same contents are inputted to the register 13 again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image enlarging/reducing circuit that prevents deterioration in image quality caused by moiré when enlarging or reducing pseudo-halftone data.

[Conventional technology]

Conventional image enlargement/reduction circuits, for example, convert image information such as the contents of a document read by a COD image sensor into a binary digital signal and store it in an image memory, and then enlarge or reduce the stored digital image data. There is a method that enlarges or reduces the data of the target part by adding or deleting 1 bit data every few bits.

When adding or deleting 1-bit data in this case, the oPC method, 9-division method, high-speed projection method, etc. are used.

[Problem that the invention seeks to solve]

However, conventional image enlargement/reduction circuits have a problem in that when pseudo halftone data is enlarged or reduced, moiré occurs, resulting in poor image quality.

[Configuration and means for solving the problem 3 The present invention was made in view of the above. Binary data is processed in the conventional manner, and pseudo halftone data is processed by adjusting the pixel size and The present invention provides an image enlargement/reduction circuit that changes the number of processing bits based on the enlargement/reduction ratio.

〔Example〕

The image enlargement/reduction circuit according to the present invention will be explained in detail below.

FIG. 2 shows an image processing system in which the image enlargement/reduction circuit according to the present invention is used, and shows image memories 1 and 2 that store image information as black and white binary data, and the image memory l.
and 2, an MPU 3 that transfers digital image data from an input device, etc., an image processing section 4 that performs processing such as enlargement, reduction, or rotation on image data stored in the image memory 1 or 2, and an image processing section 4 that transfers image information from the outside. An image input device 5 for transferring to the system, a printer 6 for hard copying the processing results in the image processing section 4, a display device 7 for displaying processing contents, data contents, etc., and a coordinate input device 8 for specifying a position during image processing. It is composed of an external storage device 9 such as a magnetic disk for storing digital image data, and a bus 10 that connects each of the above-mentioned members.

FIG. 1 shows an embodiment of the present invention, which is provided in the image processing unit 4 shown in FIG. A register 12 and a shift register 1 on the shift register 1 to which the enlarged or reduced results are input.
3, a data selector 14 that selects the shift register 12 or 13 by a data selector signal 17, a sequencer 18 that controls mutual timing of each register, and a register 1 in which the expansion/reduction ratio is set as an initial value.
9, a register 20 that stores data to be added to the contents of the register 19, an adder circuit 21 that adds the contents of the register 20 and the contents of the register 19, and outputs a carry signal to the sequencer 18; It is composed of a launch circuit 22 that holds the contents of the adder circuit 21 and transfers the contents to the register 20. The adder 21 inputs the contents of registers 19 and 20 (the last two digits of the expansion/reduction ratio are set,
For example, 70% is set as 70, 120% is set as 20, and O is set as the initial value in register 20).When the addition result reaches the third digit, there is a carry. Generate a signal.

In the above configuration, first, the reduction processing of binary data in the main scanning direction will be explained based on the timing chart of FIG. 3. The data selector 14 selects the shift register 12 using the sequencer 18. 0'' is set in the register 20, the reduction rate is set as an initial value in the register 19 with a two-digit number, and the first data of the image data to be reduced is transferred from the image memory 1 to the shift register 12. In such a state, the sequencer 18 checks the presence or absence of the carry signal 24, which is output when the registers 19 and 20 add up to 3 digits.If the carry signal 24 is generated, the sequencer 18 checks the presence or absence of the carry signal 24, which is output when the registers 19 and 20 add up to three digits. Only one clock is output to the shift register 13, and if there is no carry signal 24, the shift clock signal 16 is not generated.
8 issues a load signal 23 to the register 20, and the adder 21
The result is loaded into the register 20 via the launch circuit 22, and the loaded value and the contents of the register 19 are added. Furthermore, after shifting the shift register 12 by 1 bit to the MSB side, the sequencer 18 checks the carry signal 24 again, and if a carry signal 24 is generated, performs six or more operations to shift the shift register 13 by 1 bit for one line of the original. The operation is repeated sequentially until the end of the minute, and when the contents of the shift register 12 become empty on the way, the next data is loaded from the source memory side. Furthermore, when the shift register 13 becomes full, its contents are transferred to the destination memory (image memory 2).

On the other hand, for reduction in the sub-scanning direction, the same reduction rate calculation as in the main scanning direction is performed for each line, and the next line is selected when a carry signal is generated, so that no carry signal is generated. In this case, the next line is skipped without being adopted, and zero or more operations for adopting the next line are repeated and executed for one page of data.

Next, processing for enlarging binary data in the main scanning direction will be described. This process is the same as the process for reduction, except that the method of generating the shift clock 16 is different as shown in FIG. Every time the signal 24 is output, the data input to the shift register 13 is re-inputted and enlarged. When the shift register 13 is full, the shift register 13 is stored in the destination memory.
When the shift register 12 becomes empty, the next data is loaded from the source memory (image memory l). Enlargement in the sub-scanning direction can be achieved by employing the next line twice when the carry signal 24 is not generated, and repeating this for one page of data, as in the case of reduction.

FIG. 5 shows how data decreases and increases when binary data is reduced and enlarged in the sub-scanning direction. Figure 5 (a
l indicates the original image, fbl indicates reduction, and (C1 indicates enlargement).

Next, the enlargement and reduction processing of pseudo-image halftone data will be explained. During reduction in the main scanning direction, the selector 14 selects the soft register 12 by the sequencer 18 . The reduction ratio is set in the register 19, and the initial value "0" is set in the register 20. The sequencer 18 checks the carry signal 24, and if it is present, generates each of the shift clock signals 15 and 16 m times (where m is the pixel size) by one clock. FIG. 6 is a timing chart showing a process of 0 or more in which only the shift clock signal 15 is generated m times when the signal 24 is not generated. shift register 1
When the shift register 13 becomes empty, the next data is transferred from the source memory to the register 12, and when the shift register 13 becomes full, the data is transferred to the destination memory.
The process of storing the contents of 0 or more is repeatedly executed for one line of data in the main scanning direction.

For reduction in the sub-scanning direction, the same addition calculation as in the main scanning direction is performed every m lines, and if the carry signal 24 is not generated, the next m547 worth of data is skipped and the carry signal 24 is generated. If so, the next m547 worth of data is used to perform the reduction.

Next, a process for enlarging pseudo halftone data will be described.

The data selector 14 selects the shift register 12 based on the data selector signal output from the sequencer 18. The enlargement ratio is set in the register 19, and the initial value "0" is set in the register 20. The first data to be enlarged is input to the shift register 12 from the image memory l.

In this state, the sequencer 18 uses the carry signal 24
If the signal 24 is not generated, m shift clocks 15 and 16 are outputted, and the contents of m bits of the shift register 12 are transferred to the shift register 13 and copied. When the carry signal 24 is generated, the contents of the m bits of the shift register 12 are shifted to the shift register 13, and then the data selector 14 is selected to select the m-th bit of the shift register 13, and the contents of the m bits of the shift register 13 are transferred to the shift register 13. is input to the shift register 13 again. Upon completion of this input, the sequencer 18 sends the data selector signal 17 to the data selector 14, and when a series of processes of 0 or more to select the shift register 12 again is completed, the sequencer 18 sends the contents of the adder 21 via the launch circuit 22. register 20
Let him load. Next, the contents of the register 20 and the contents of the register 19 are added, and the carry signal 24 is checked to see if it is null. Thereafter, the process is repeated for one line of data in the same way.

In the enlargement process in the sub-scanning direction, an addition calculation of the enlargement ratio is performed for every m lines as in the case of the main scanning direction.

When the carry signal 24 is not generated, the data for m547 is used once, and when the carry signal 24 is generated, the data for m547 is used twice for expansion.

FIG. 7 is a timing chart for enlarging pseudo halftone data in the main scanning direction.

In addition, Figure 8 shows the increase and decrease of pixels due to enlargement and reduction of pseudo halftone data, Figure +81 is the pixel arrangement of the original image, (Figure b1 is the result of reduction, Figure (C) is the result of enlargement. are shown respectively.

FIG. 9 shows a modification of the embodiment shown in FIG. 1, in which shift registers 12, 13 and data selectors 14 are each connected in parallel in t stages. In such a configuration, shift registers 121-12. 2,547 minutes of data can be stored in advance, and the 2,547 minutes of data can be expanded and reduced at once. This enables high-speed processing.

In the above explanation, the initial value of the register 20 is set to O, but it can take any value depending on whether or not the first data is adopted.

〔Effect of the invention〕

As explained above, according to the image enlargement/reduction circuit of the present invention,
Data shift 1 is changed by the pixel size depending on whether the binary data is pseudo-halftone data and whether the mode is enlarged or reduced, so it is possible to obtain enlarged or reduced images with high N'f without moiré. be able to. Moreover, since the same circuit can perform the enlargement and reduction processing without providing dedicated circuits for processing each of binary data and pseudo-halftone data, the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of an image processing system to which the present invention is applied, FIG. 3 is a timing chart of reduction processing for binary data in the present invention, and FIG. Figure 4 is a timing chart of enlargement processing for binary data in the present invention, and Figure 5 (al.
~ (cl is a reduction in the sub-scanning direction for binary data in the present invention) Figures 6 and 7
The figure is a timing chart of reduction and enlargement processing for pseudo-halftone data in the present invention, and FIG.
1 is an explanatory diagram of increase/decrease in pixels due to enlargement/reduction of pseudo halftone data in the present invention, and FIG. 9 is a block diagram showing a modification of the embodiment of the present invention. Explanation of symbols 1.2...Image memory, 3.-1--
...MPU, 4... Image processing unit, 12, 12. ~12 13.13+~131-- Shift register, 14, 14. ~14 L------
Data selector, 18--Sequencer, 19.2
0---------Register, 21---Adder,
22.--Latch circuit. Patent applicant Agent: Fuji Xerox Co., Ltd.
Patent Attorneys Shin Matsubara 2 Same Seiji Muraki Same Tadao Hirata Same Same Jun Ueshima - Same Lead powder Hitoshi 1 Figure 2 Figure 3 Figure 4 J Uh. , 7ta
17 Figure 5 (a) lb)
(c) 6th section, 7th figure, te'wo, L7
/
/'Figure 8 tσノ
(b) (C) Figure 9

Claims (1)

[Scope of Claims] An image processing apparatus that converts each pixel of an image into a digital signal and stores it in an image memory, and processes the stored image information for enlarging or reducing the data of a predetermined length to be processed from the image memory. A first shift register to which is input, a second shift register that shifts a predetermined bit from the register at a predetermined timing, and a shift timing that sequentially adds the reduction rate or enlargement rate and generates a carry signal at the time of a carry. and a control unit that changes the amount of data shifted from the first shift register to the second shift register according to the type of carry signal and image data output from the calculation unit. Characteristic image scaling circuit.