JPH11289438A - Digital image processor, digital image processing method and image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a memory access speed, to reduce the cost, to make the system operation stable and to allow the image processor to conduct more complicated image processing. SOLUTION: Write data WD1 of a current N-line are given to a serial/ parallel conversion section 16, 1-line data are converted into parallel data consisting of even numbered pixel data and odd numbered pixel data, and the even numbered pixel data are written in a line memory 12a and the odd numbered pixel data are written in a line memory 12b. In the case of reading the pixel data having already been written in the line memories, data are read simultaneously from the line memories 12a, 12b by 2-bit, and a parallel/serial conversion section 14 synthesizes alternately even numbered pixels and odd numbered pixels via an MUX 3 and read image data. A memory conversion section 20 individually controls the line memories 12a, 12b to use them image processing of the image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus, a digital image processing method, and an image reading apparatus, and more particularly to multi-valued image data of the number of main scanning pixels read at a predetermined reading line density. The present invention relates to a digital image processing apparatus and a digital image processing method for sequentially processing line data using a line memory, and an image reading apparatus using the same.

[0002]

2. Description of the Related Art In recent years, an image reading section such as a facsimile machine, a digital copying machine, or an image scanner sequentially reads an image to be read in a main scanning direction, and sequentially processes digital image data of each read line. Digital image processing devices are used. For example, FIG. 5 shows a block diagram of a conventional digital image processing system 50. The entire digital image processing system 50 shown in FIG. 5 processes digital image data in synchronization with a system pixel clock f supplied from a clock generator (not shown). That is, pixel data constituting image data is processed by one pixel during one cycle of the system pixel clock. In FIG. 5, a document image signal in units of main scanning lines read by the line image sensor 60 is input to the pre-processing unit 62 in synchronization with the system pixel clock f. The pre-processing unit 62 converts the input image signal into an A / A signal in synchronization with the system pixel clock f.
The digital image data obtained by the D conversion is subjected to processing such as shading correction and output. Pre-processing unit 6
The image data output from 2 is further processed by the next-stage processing unit 72 that performs resolution conversion processing and the like, but before that, the MTF correction processing is performed by the MTF correction unit 68.
In the MTF correction unit 68, a 3 × 3 matrix register 64
, 3 × 3 pixel data A, B, C, D, E,
A product-sum operation between F, G, H and I and the correction coefficients a, b, c, d, e, f, g, h and i stored in the correction coefficient matrix 70 as follows: aA + bB + cC + dD + eE + fF + gG + hH + i
I is performed, and the value obtained here is input to the next-stage processing unit 72 as new pixel data of the target pixel E after correction.

The 3 × 3 referred to by the MTF correction unit 68
Image data for each main scanning line from the pre-processing unit 62 is sequentially input to the lower register G of the matrix register 64 as the current (N) line in synchronization with the system pixel clock f. The registers G, H and I constitute a shift register, and the pixel data of the register G is shifted to the register H and the pixel data of the register H is shifted to the register I in synchronization with the system pixel clock f. The pixel data of the register I is written in the line memory 52. In the middle register D of the 3 × 3 matrix register 64, the image data of the main scanning line read from the line memory 52 is sequentially input as the previous (N−1) line in synchronization with the system pixel clock f. Is done. The registers D, E and F constitute a shift register, and the registers D, E and F are synchronized with the system pixel clock f.
Is shifted to the register E, and the pixel data of the register E is shifted to the register F. In the line memory 54,
The pixel data of the register F is written. Also, 3 × 3
The image data for each main scanning line read from the line memory 54 is sequentially input to the register A in the upper stage of the matrix register 64 as the (N−2) -th line immediately before the system pixel clock f. Also, register A,
B and C constitute a shift register, and the pixel data of the register A is shifted to the register B and the pixel data of the register B is shifted to the register C in synchronization with the system pixel clock f. The line memory 52 includes a line memory 52
, The image data of the previous (N-1) line is written.

That is, the line memory 52 stores the current (N)
The image data for the line is written into the line memory 52.
Is read out as image data for the previous (N-1) line.
Further, the image data of the previous (N-1) line is written in the line memory 54, and the image data of the previous (N-1) line written in the line memory 54 is (N-
2) It is read out as image data for a line. The line image sensor 60 is, for example, as shown in FIG.
.., (2n−1), (2n), (2
n + 1),..., (2n_max), the system when the (2n) -th pixel data of the current (N) line is input to the register G from the pre-processing unit 62 In the cycle of the pixel clock f, the register D stores the (2N) -th pixel data of the previous (N-1) line, and the register A stores the previous (N) th pixel data.
-2) If the (2n) th pixel data of the line is not input, a 3 × 3 pixel matrix cannot be formed correctly. Therefore, within one cycle of the system pixel clock f, the operation of reading out, for example, the (2n) th pixel data of the previous (N-1) line from the line memory 52 and the operation of reading the (2n) th pixel data of the current (N) line And writing the pixel data of the pixel data to the line memory 52. In addition, within one cycle of the system pixel clock f, (N−
2) It is necessary to perform an operation of reading the (2n) th pixel data of the line from the line memory 54 and an operation of writing the (2n) th pixel data of the previous (N-1) line into the line memory 54. . Switching between read data and write data for this purpose is performed by the multiplexers MUX1 and MUX2 which are switched by a timing signal from the timing signal generator 58.

[0005] Write data WD to line memory 52
1, that is, the image data of the current (N) line is input to the MUX 1 in synchronization with the system pixel clock f, and the read data RD1 from the line memory 52, that is, the image data of the previous (N-1) line is The signal is output from the MUX 1 in synchronization with the system pixel clock f. Therefore,
MUX1 has a frequency 2 which is twice the system pixel clock f.
The input / output data MD1 from the MUX 1 to the line memory 52 has a frequency 2f which is twice as high as the system pixel clock f.
Otherwise, the entire image processing system cannot process pixel data synchronized with the system pixel clock f. The same applies to the line memory 54. The write data WD2 to the line memory 54, that is, the image data of the previous (N-1) line is synchronized with the system pixel clock f by the MU.
X2, the read data RD2 from the line memory 54, that is, the image data of the (N-2) th line before the previous line is output from the MUX2 in synchronization with the system pixel clock f. Therefore, the MUX 2 synchronizes with the frequency 2 f twice the frequency of the pixel clock f to synchronize with the timing signal generator 58.
If the input / output data MD2 from the MUX 2 to the line memory 54 is not synchronized with the frequency 2f twice as high as the pixel clock f, the entire image processing system cannot process the pixel data synchronized with the pixel clock f. Therefore, a frequency 2f twice the pixel clock f is input from the memory control unit 56 as the operation clock CK to the line memory 52 composed of the synchronous SRAM, and the write enable signal WEB synchronized with the system pixel clock f is input. Further, the address signal AD is input at a frequency 2f which is twice the system pixel clock f.

The write enable signal WEB is a signal having a duty ratio of 50%. The first H level period is a read enable period, and the second L level period is a write enable period. The address signal AD is output to the memory control unit 5
Reference numeral 6 is generated to use the line memory 52 as a FIFO (first in first out) memory. The operation clock CK and the write enable signal WEB similar to those input to the line memory 52 are output from the memory control unit 56.
And an address signal AD are input to the line memory 54. Here, the read / write operation of the line memories 52 and 54 controlled by the memory control unit 56 will be briefly described with reference to FIG. The memory control unit 56 in FIG. 5 holds a write pointer and a read pointer (not shown) for the line memories 52 and 54, respectively.
When the write data WD1, which is the image data of the current (N) line, is written to the line memory 52,
The data is written to the address indicated by the write pointer. Also, read data RD1, which is the image data of the previous (N-1) line, is read from the line memory 52,
When input to the register D of the 3 × 3 matrix register 64, the data is read from the address indicated by the read pointer. Similarly, a 3 × 3 matrix register 6
When the write data WD2 which is the image data of the previous (N-1) line from the register F of No. 4 is written to the line memory 54, it is written to the address pointed to by the write pointer. When the read data RD2, which is the image data of the (N−2) th line before, is read from the line memory 54 and input to the register A of the 3 × 3 matrix register 64, the read pointer points. Read from address. Note that the write pointer and the read pointer held by the memory control unit 56
It changes every time data for one pixel is written or read, and the line memories 52 and 54 operate as FIFO memories.

As described above, the input / output operation of the pixel data with respect to the line memories 52 and 54 is 3 × 3
Independently of the matrix register 64, the 3 × 3 matrix register 64 merely receives pixel data input to and output from the line memory 52 and the line memory 54 in parallel. The input / output operation of pixel data to / from the line memory 52 and the input / output operation of pixel data to / from the line memory 54 are input to the line memory 52 as pixel data of the current (N) line. The output is the pixel data of the previous (N-1) line, while the input to the line memory 54 is the pixel data of the previous (N-1) line, and the output from the line memory 54 is the previous. Only the difference is that each pixel data is the (N-2) line, the previous (N-1) line is considered as the current line for the line memory 54, and the last (N-2) line is regarded as the current line data for the line memory 54. Considering the previous line, it can be said that exactly the same input / output operation is performed.

FIG. 6 shows a timing chart in the conventional digital image processing system 50 shown in FIG. In FIG. 6, the system pixel clock f is half the frequency 2f of the operation clock CK supplied to the line memories 52 and 54, and the operation clock CK is
It is assumed that the operable upper limit frequencies of the line memories 52 and 54 are set. That is, the entire digital image processing system 50 uses a system pixel clock f of a frequency half of the operable upper limit frequency of the line memories 52 and 54.
It is operating in synchronization with. Image data of the current (N) line as input data is input in pixel units in synchronization with the system pixel clock f. Memory control unit 5
As the address signal AD output by 6, a read address is output in the first half of the system pixel clock f, and a write address is output in the second half of the system pixel clock f. Correspondingly, the write enable signal WEB is output as an H level indicating read enable when a read address is output, and as an L level indicating write enable when a write address is output.
Write data WD1 and read data R to and from the line memory 52 input / output in synchronization with the system pixel clock f.
D1 is switched by the MUX1 at a frequency of 2f, and is written to or read from the line memory 52.
Further, the write data WD2 and read data RD2 to and from the line memory 54 input and output in synchronization with the system pixel clock f are switched at a frequency of 2f by the MUX 2 to be written or read to the line memory 54. Then, the image data of the previous (N-1) line after correction output from the MTF correction unit 68 is output in synchronization with the system pixel clock f. As a conventional digital image processing system, as shown in FIG.
After passing through the matrix register 64, the line memory 5
In addition to the configuration for writing to 2 or 54, as shown in FIG.
There is a configuration in which image data is written to the line memory 52 or 54 without passing through the × 3 matrix register 64. When comparing the digital image processing system of FIG. 5 with that of FIG. 7, there is a difference that the pixel data of FIG. 5 is delayed by the amount of passing through the 3 × 3 matrix register 64 compared to FIG. The access speed is the same. As a conventional memory access method, a high-speed access is realized by performing a plurality of accesses during one cycle.
It is disclosed in, for example, Japanese Patent No. 233667.

[0009]

However, in such a conventional digital image processing method, for example,
If pixel data for one pixel is processed during one cycle of the system pixel clock f, it is necessary to access the line memory twice for write processing and read processing. In the case of 2f, the system can be operated only at half the clock frequency f, and there is a problem that the image processing speed is limited by the access speed of the line memory. In a facsimile apparatus that performs digital image processing, a filtering operation using a matrix of 5 pixels × 3 lines or a matrix of 3 pixels × 3 lines is normally repeated for each functional unit by using a plurality of line memories. Therefore, many image line memories are used. Conventionally, this image processing unit is constituted by an ASIC or the like, and a general-purpose high-speed SRAM or a dual-port FIFO memory is generally attached externally.
A memory access must be performed a plurality of times during a cycle. If such a high-speed product is used, the cost increases, the operating frequency increases, and radiation occurs when many transistors are turned on / off at the same time. There has been a problem that noise increases and system operation becomes unstable. The present invention has been made in view of the problems of the related art, and a first object of the present invention is to reduce the cost by increasing the memory access speed without improving the memory performance of the line memory. It is an object of the present invention to provide a digital image processing apparatus and a digital image processing method capable of lowering an operating frequency to reduce radiation noise to stabilize a system operation and performing more complicated image processing. A second object of the present invention is to be able to read image data at different reading line densities without changing access timing to a line memory,
An object of the present invention is to provide an image reading apparatus capable of minimizing the deterioration of an image even when reading with a lower reading linear density.

[0010]

According to a first aspect of the present invention, there is provided a digital image processing method for sequentially processing line data consisting of multi-valued image data of the number of main scanning pixels read at a predetermined reading line density using a line memory. In the processing device, serial / parallel conversion means for converting serial one-line data consisting of multi-valued image data of the number of main scanning pixels into parallel data sequentially allocated to k groups for each pixel, and k-group allocation K line memories for respectively storing the obtained parallel data, data writing means for sequentially writing the k pieces of parallel data to the respective line memories within k pixel cycles, and Data reading means for reading stored parallel data within k pixel cycles; Parallel / serial conversion means for converting parallel data read from the memory into serial data, and individually controlling each of the line memories, and converting the k line memories into one pixel line according to the read line density. Or a line memory control means for controlling a data write operation and a data read operation with respect to each of the line memories by regarding each pixel line as a plurality of pixel lines independent of each other. According to the present invention, one line data of the number of main scanning pixels is sequentially divided into k groups by one pixel by the serial / parallel conversion means and converted into parallel data, and the data is written into the k line memories by the data writing means. Writing and storing the parallel data, reading the parallel data already stored in each line memory by the data reading means, and converting the parallel data read from the line memory into serial data by the parallel / serial conversion means; While individually controlling each line memory by the line memory control means, the k line memories are regarded as one pixel line or as a plurality of pixel lines independent of each other according to the read line density, and Controls data write and read operations It is way. Therefore, as k is set to 2, 3, 4,..., The access speed of the memory can be increased twice, three times, four times,. The speed can be increased, the cost can be reduced, the radiation noise can be reduced, the system operation can be stabilized, and more complicated image processing can be performed. For example, when k is set to 2, one line of serial data is converted into parallel data of even-numbered pixels and odd-numbered pixels using two line memories, and each pixel data is written to the line memory. When these are read, since they are read from two line memories and converted into serial data,
The apparent memory access time can be reduced by half (the access speed is doubled).

According to a second aspect of the present invention, there is provided a digital image processing method for sequentially processing line data comprising multi-valued image data of the number of main scanning pixels read at a predetermined reading line density using a line memory. A step of converting serial one-line data consisting of multi-valued image data of the number of pixels into parallel data sequentially allocated to k groups by one pixel, and converting the parallel data allocated to k groups into k pixel cycles a step of sequentially writing and storing the data in the k line memories, a step of reading parallel data already distributed and stored in the k line memories within a k pixel cycle, and a step of reading out the parallel data from the k line memories. Converting the parallel data into serial data, and individually controlling the k line memories, Controlling the writing operation and the reading operation of image data with respect to the line memory by regarding the k line memories as one pixel line or as a plurality of pixel lines independent of each other according to the read / write line density; And According to the invention,
Serial one-line data consisting of multi-valued image data having the number of main scanning pixels is sequentially sorted into k groups for each pixel, converted into parallel data, and k parallel data are converted into k data.
The line data is sequentially written and stored in the line memories, the parallel data stored in the k line memories is read, and the parallel data is converted into serial data.
While individually controlling each of the line memories, k line memories are stored in one pixel line according to the read line density.
Alternatively, control is performed such that the writing operation and the reading operation of the image data are performed assuming a plurality of pixel lines independent of each other. Also in this case, k is 2, 3,
According to 4, ..., it is possible to increase the memory access speed (2 times, 3 times, 4 times, ...) at a low operating frequency without using expensive high-speed products for the line memory. The cost can be reduced, the radiation noise can be reduced, the system operation can be stabilized, and more complicated image processing can be performed using the extra memory.

According to a third aspect of the present invention, in the image reading apparatus for reading an image to be read at an arbitrary reading linear density and performing data processing using the digital image processing apparatus according to the first aspect, While controlling the writing operation and reading operation of the image data using the number of lines of the line memory suitable for the reading linear density for reading an image, the extra memory area of the line memory is used to reduce the reading linear density. There is provided control means for controlling so as to select and execute appropriate image processing. According to the present invention, the writing operation and the reading operation of the image data are performed by the control means using the number of lines of the line memory suitable for the read line density of the read image, and the extra memory area of the line memory is used. Then, image processing suitable for the read line density is selected and executed. Therefore, the apparent memory access speed can be increased without changing the memory access timing, so that the memory cost can be reduced. Further, when the read line density is roughened or low-speed processing is sufficient, image deterioration can be compensated for by performing image processing using the surplus line memory area. According to a fourth aspect of the present invention, in the image reading apparatus according to the third aspect, the control unit performs any one of filtering, error diffusion, isolated point removal, and pictogram separation as image processing suitable for the read line density. Is controlled to be selected and executed. According to the present invention, as image processing according to the read line density, filtering processing, error diffusion processing,
Since either the isolated point removal processing or the pictograph separation processing is selected, even if the read line density becomes rough, the image processing can be performed to prevent image deterioration.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a line memory device portion that writes / reads digital image data read by a digital image processing system 10 (an overall configuration diagram is omitted) according to the present embodiment to / from a line memory. It is shown. In the present embodiment, as an overall configuration diagram of the digital image processing system omitted in FIG. 1, for example, the block A in FIG. 5 is replaced with the block B in FIG. A case where the present invention is applied to a reading unit will be described. Therefore, the line memories 12a and 12b in FIG.
This corresponds to the line memory 52 shown in FIG.
However, the operable upper limit frequency is 2f in FIG.
ECK (hereinafter referred to as 2f), but in FIG. 1 f ECK
(Hereinafter, referred to as f), and the operation clock CK, the write enable signal WEB, and the address signal AD supplied from the memory control unit 20 to the line memories 12a and 12b, respectively, have frequencies of f, f / 2, and f, respectively. The frequency of the memory data MD1a and MD1b input to and output from the line memories 12a and 12b is also f, which is 1/2 of 2f of the memory data MD1 input to and output from the line memory 52. On the other hand, the image data of the current (N) line inputted as write data from the register I of the 3 × 3 matrix register 64 to the line memory device of the block B in FIG.
, And the image data of the (N-1) th line before being output as read data from the line memory device is output in synchronization with the frequency f. That is, the digital image processing system 10 according to the present embodiment operates in synchronization with the system pixel clock f having the same frequency as the operable upper limit frequency f of the line memories 12a and 12b.

Therefore, in the case of the conventional line memory device of the block A in FIG. 5, the line memories 52 and 54 have to be operated at an access speed of 2f which is twice the system pixel clock f. However, in the line memory device of the present embodiment, as shown in FIG. 1, the write data WD1 of the current (N) line is replaced with the even-numbered write pixel data WD1a and the odd-numbered write pixel data WD1b.
And the serial / parallel conversion unit 16 that performs serial / parallel conversion on the first and second read-out pixel data RD1a and the odd-numbered readout pixel data RD1b on the previous (N-1) line. ) Since the parallel / serial conversion unit 14 for restoring the line read data RD1 is provided, the line memories 12a and 1
The access speed of the image processing system when viewed from 2b is reduced to half f from 2f of the related art. The even-numbered write pixel data WD1a and the odd-numbered write pixel data WD1b output from the serial / parallel converter 16 in synchronization with the frequency f are respectively switched and input to the line memories 12a and 12b by the multiplexer MUX3. Line memories 12a and 12b
The even-numbered read pixel data RD1a and the odd-numbered read pixel data RD1b from the multiplexer MUX3
, And is input to the parallel / serial conversion unit 14. The timing signal generator 18 supplies a timing signal for conversion and switching to the parallel / serial converter 14, the serial / parallel converter 14, and the multiplexer MUX3.

Thus, the even-numbered pixel data of the current (N) line is written into the line memory 12a, and the even-numbered pixel data of the previous (N-1) line is read from the line memory 12a. The odd-numbered pixel data of the current (N) line is written into the line memory 1b, and the odd-numbered pixel data of the previous (N-1) line is read from the line memory 12b. Here, the read / write operation of the line memories 12a and 12b controlled by the memory control unit 20 will be described. The memory control unit 20 includes a line memory 12a
And 12b hold a write pointer and a read pointer (not shown). When the even-numbered pixel data of the current (N) line is output from the register I of the 3 × 3 matrix register and is written to the line memory 12a, the address AD indicated by the write pointer is used.
Is written to. Further, even-numbered pixel data corresponding to specific even-numbered pixel data of the current (N) line written in the line memory 12a of the previous (N-1) line is read out from the line memory 12a, and 3 × 3 When input to the register D of the matrix register, the data is read from the address AD indicated by the read pointer.

Similarly, when the odd-numbered pixel data of the current (N) line is output from the register I of the 3 × 3 matrix register and written into the line memory 12b,
The data is written to the address AD indicated by the write pointer. The odd-numbered pixel data corresponding to the specific odd-numbered pixel data of the current (N) line written in the line memory 12b of the previous (N-1) line is read out from the line memory 12b, and 3 × 3 When input to the register D of the matrix register, the data is read from the address AD indicated by the read pointer. The above-mentioned read pointer and write pointer change each time data for one pixel is written or read, and the line memory 12a, 1
2b operates as a FIFO memory.

FIG. 2 shows a timing chart in the digital image processing system 10 including the line memory device of the present embodiment shown in FIG. In FIG. 2, the system pixel clock f is the same frequency as the frequency f of the operation clock CK supplied to the line memories 12a and 12b, and here, the operation clock CK is set to the operable upper limit frequency of the line memories 12a and 12b. It is assumed that That is, the entire digital image processing system 10 includes the line memories 12a and 12b.
Can operate at the same frequency as the operable upper limit frequency, and can be used up to twice as high as the conventional frequency. Image data of the current (N) line as input data is input in pixel units in synchronization with the system pixel clock f. As the address signal AD output by the memory control unit 20, a read address is output in the first half of a period corresponding to two pixel cycles of the system pixel clock f, and a write address is output in the second half. Correspondingly, the write enable signal WEB is output as an H level indicating read enable when a read address is output, and as an L level indicating write enable when a write address is output.

The image data of the current (N) line as write data WD1 to the line memory 12a or 12b which is input in synchronization with the system pixel clock f is half of the system pixel clock f by the serial / parallel converter 16. Is divided into even-numbered write pixel data WD1a and odd-numbered write pixel data WD1b synchronized with a clock having a frequency of f / 2, and 2bi in the latter half of the two-pixel cycle.
t is written. Further, the line memory 1 is synchronized with a clock having a frequency f / 2 which is half of the system pixel clock f.
Even-numbered readout pixel data RD1a and odd-numbered readout pixel data RD1b output from 2a or 12b
Are read out simultaneously by 2 bits in the first half of the two-pixel cycle, RD1a is alternately converted into serial data first by the parallel / serial conversion unit 14, and is read out as the read data RD1 synchronized with the system pixel clock f.
1) It is combined with the image data of the line. The MTF correction unit (not shown in FIG. 1) (the MTF correction unit 6 in FIG. 5)
8) (after MTF correction) (N-1)
The image data of the line is output in synchronization with the system pixel clock f.

As described above, a line memory for buffering one line of image data is prepared for each of the even-numbered pixel data and the odd-numbered pixel data which appear alternately, and the digital image processing system 10 , The one-line image data input in synchronization with the system pixel clock f is separated into even-numbered pixel data and odd-numbered pixel data in synchronization with a clock having a frequency f / 2, which is half of the system pixel clock f. 1 is written to or read from the separate line memories 12a and 12b, so that the line memory device shown in the block B of FIG. 1 is １ ／ of the conventional line memory device (see block A of FIG. 5). Digital image processing system while using a memory having an access speed as the line memory 12a or 12b The body can be operated in synchronism with the conventional double frequency with the system pixel clock f (because it to the operating limit frequency it).

In the line memory device according to the above-described embodiment, even-numbered pixel data and odd-numbered pixel data are separately written using the two line memories 12a and 12b, and simultaneously read and synthesized.
The access speed of the line memory has been improved. For this reason, the present invention is not limited to the above example, and the input image data is divided into k (for example, k = 3 or k = 4) pixel groups, and the first to A line memory in which the k-th pixel can be written is prepared, and the serial / parallel converter 16 shown in FIG. Separate into pixel data sequentially, multiplexer M
While writing to the line memories for the first to k-th pixels via the UX3, the first for the previous line already written to the line memories for the first to k-th pixels, respectively. The multiplexer M
The reading may be performed via the UX3, and the parallel / serial conversion unit 14 may convert the data into serial data. With this configuration, the system pixel clock f that determines the operation speed of the digital image processing system
Is constant, a lower-speed memory (operable upper limit frequency is f × 2 / k) can be used as the line memory. If the operable upper limit frequency f of the line memory is fixed, the digital image processing system can be used. The frequency of the system pixel clock that determines the operation speed can be increased to (f × k / 2).

Further, in the above embodiment, the plurality of line memories can be individually controlled by the memory control unit 20. For example, as shown in FIG. 3, the reading mode in a facsimile apparatus or the like is set to 400 dp.
In the case of a photograph of i (reading line density), the image data is processed using the maximum memory. Also, as in the case where the reading mode is a character of 200 dpi, the number of data processes (number of pixels) per line shown in FIG.
If the capacity of the line memory 12a is sufficient and the system pixel clock f can be low speed, one memory access control is performed between the block C and the line memory 12a. By combining another block D configured as described above with the line memory 12b, it is possible to use an additional memory. As described above, by switching the memory according to the application, for example, in the case of the above-described reading mode, high-speed operation can be performed by using the memory during the copy reading operation. In the case of the reading mode, the operation speed is low, but image area separation and various binarization processing functions as shown in FIG. 3 can be added. Becomes possible. In addition, in FIG. 3, in addition to the above-described reading mode, 400 dpi characters or 200 dpi
The memory can be switched and used according to the pictogram or the like.

FIG. 4 is a flowchart showing a case where the memory is switched according to the application as shown in FIG. As shown in FIG. 4, analog image data read by a line image sensor is converted into digital image data by an A / D converter, and 5K ×
Performs dark correction with a memory capacity of 6 bits, 5K x 7 bits
5K × 8b
Main scanning magnification change is performed with a memory capacity of it × 2 lines.
In this main scanning magnification change, if the system configuration is very simple, it is possible to perform only reduction by performing thinning-out magnification without using the line memory. Needs to be processed using a line memory having the above memory capacity. In this manner, the main scanning magnification is changed, the γ correction A is performed with a memory capacity of 256 × 8 bits, and then an arithmetic processing is performed using a spatial filter which is a matrix register. Here, a matrix of 5 pixels × 3 lines is used, and processing is performed using a memory capacity of 5 / 2.5K × 6 bits × 2 lines. The image data processed by the spatial filter is processed by an MTF correction unit or the like while selecting processing such as MTF correction I or MTF correction II, smoothing, or vermilion detection in accordance with the intended use. After processing into character image data, photographic image data, pictogram edge judgment data, or pictogram white background judgment data suitable for the image data, comprehensive judgment is performed and output as image data. As described above, in the present embodiment, since the operable upper limit frequency in the digital image processing system can be increased without increasing the access speed of the line memory, the digital image processing can perform high-speed image processing at low cost. An image processing system can be configured. Also,
By switching the number of lines of the line memory to be used according to the application, it is possible to effectively use the memory resources.

In the above-described embodiment, the case where the reading linear density is selected from 400 dpi and 200 dpi has been described.
Alternatively, other reading linear densities can be selected,
The configuration may be such that it is possible to appropriately select whether to give priority to the image processing speed or to perform image processing suitable for various reading line densities. Further, in the above embodiment, in order to perform image processing such as MTF processing, it is possible to connect and use line memory devices by the number of stages corresponding to the size of the matrix register formed in the digital image processing system. is there. That is, the size of the matrix register is 5 pixels × 5
In the case of a line, a four-stage line memory device may be connected and used. In the above embodiment, the buffering of binary image data composed of one bit per pixel is not limited to two bits or more per pixel (usually, 6 bits or 8 bits are often used). For buffering of multi-valued image data to be configured, unlike a general-purpose memory in which the number of bits per address of the line memories 12a and 12b is determined to be, for example, 8 bits, the line memory device performs digital image processing. When formed together with the system as an LSI such as an ASIC in the same chip, the number of bits per address can be set arbitrarily, so that the surplus bits are not wasted and the memory resources are effectively used. Now you can do it. Further, in the above embodiment, a synchronous SRAM generally used in an ASIC or the like as a line memory is used.
Has been described as an example, but the present invention is not limited to this, and the same can be applied to a case where an asynchronous RAM is used as a line memory.

[0024]

As described above, according to the first and second aspects of the present invention, it is possible to increase the memory access speed at a low operating frequency without using an expensive high-speed line memory. This makes it possible to reduce costs, reduce radiation noise, stabilize system operation, and perform more complex image processing. Claim 3
According to the inventions described in (4) and (4), the memory access speed can be increased without changing the memory access timing, the cost can be reduced, the read line density can be reduced, and low-speed processing can be performed. Image processing can be performed to prevent image deterioration.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a line memory device portion that performs a process of writing / reading digital image data read by a digital image processing system according to the present embodiment to / from a line memory.

FIG. 2 is a timing chart in the digital image processing system including the line memory device of the present embodiment shown in FIG.

FIG. 3 is a diagram showing a switching specification of a memory to be used by switching the number of lines of a line memory to be used according to an application.

FIG. 4 is a diagram showing a flowchart for performing image processing by switching memories according to applications.

FIG. 5 is a block diagram of a conventional digital image processing system.

FIG. 6 is a timing chart in the digital image processing system of FIG. 5;

FIG. 7 is a block diagram of another conventional digital image processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Digital image processing apparatus 12a, 12b Line memory 14 Parallel / serial conversion part 16 Serial / parallel conversion part 18 Timing signal generation part 20 Memory control part MUX3 Multiplexer

Claims (4)

[Claims] 1. A digital image processing apparatus for sequentially processing line data composed of multi-valued image data of the number of main scanning pixels read at a predetermined reading line density using a line memory, comprising: And serial / parallel converting means for converting serial one-line data into parallel data which is sequentially allocated to k groups for each pixel, and k line memories for storing the parallel data allocated to k groups, respectively. Data writing means for sequentially writing the parallel data allocated to the k groups to each of the line memories in k pixel cycles, and reading the parallel data already stored in each of the line memories in k pixel cycles Data reading means; and parallel data read from the line memory. A serial / parallel conversion means for converting each of the line memories into individual data, and controlling the k line memories as one pixel line according to the read line density or independent of each other. A digital image processing apparatus comprising: a line memory control unit configured to control a data write operation and a data read operation with respect to each of the line memories as a plurality of pixel lines. 2. A digital image processing method for sequentially processing line data composed of multi-valued image data of the number of main scanning pixels read at a predetermined reading line density by using a line memory, comprising the steps of: Converting the serial one-line data consisting of the data into parallel data sequentially allocated to k groups by one pixel, and sequentially converting the parallel data allocated to the k groups to k line memories in k pixel cycles A step of writing and storing; a step of reading parallel data already distributed and stored in the k line memories in a k pixel cycle; and converting the parallel data read from the k line memories into serial data. Converting, and individually controlling the k line memories to obtain the read line density. Controlling the writing operation and the reading operation of image data with respect to the line memory by regarding the k line memories as one pixel line or as a plurality of pixel lines independent of each other. A digital image processing method comprising: 3. An image reading apparatus which reads an image to be read at an arbitrary reading line density and performs data processing using the digital image processing apparatus according to claim 1, wherein the reading line density at which the image to be read is read is adjusted. While controlling the writing operation and the reading operation of the image data using the suitable number of lines of the line memory, selecting the image processing suitable for the reading line density using the extra memory area of the line memory. An image reading apparatus, comprising: a control unit that controls to execute the image reading. 4. The image processing apparatus according to claim 1, wherein the control unit selects and executes any one of filtering, error diffusion, isolated point removal, and pictograph separation as image processing suitable for the read line density. The image reading device according to claim 3.