JP3529208B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a facsimile machine, a copying machine, etc., and has a plurality of output channels.
The present invention relates to an image processing device that processes image data that a three-dimensional image sensor reads a document image and outputs.

[0002]

2. Description of the Related Art Generally, in order to increase the reading speed of an image sensor, it is sufficient to shorten the accumulation time, which is the time required for a photoelectric conversion element forming each pixel of the image sensor to read an original. S / N is deteriorated due to lack. On the other hand, if the amount of light is sufficient, the storage time can be shortened while maintaining S / N, but in a one-dimensional image sensor that has to sequentially output the image data of all pixels as serial image data within the storage time. , If the time required to output the image data of a certain pixel to the output of the image data of the next pixel is not shortened, that is,
Unless the transfer rate of the image data is increased, the time required to output all the image data for one line cannot be shortened, and as a result, the accumulation time cannot be shortened.

Among one-dimensional image sensors, CCD (C
The charge coupled device (image sensor) operates at a relatively high speed because it is integrated into an IC,
Although it is possible to shorten the accumulation time to increase the transfer rate of image data, even if the transfer time of image data is set to the maximum by shortening the accumulation time as much as possible, the image output from the image sensor The processing speed of the image processing apparatus at the subsequent stage for processing data is usually slower than the maximum transfer speed of the image sensor. Therefore, the processing speed of the image processing apparatus is limited by its own processing speed, and the transfer rate of the image data of the image sensor rarely determines the processing speed of the image processing apparatus.

On the other hand, in the image sensor of the type in which the photoelectric conversion element is arranged on the substrate with the same width as the width of the original, such as a contact (actual size) image sensor, the circuit delay is CCD.
The storage time is relatively large compared to that of the CCD, and the storage time cannot be made so short as that of the CCD.

Therefore, in the contact image sensor, the processing speed of the image processing apparatus in the subsequent stage tends to be limited due to the limit of the transfer speed of the image data, and the accumulation time cannot be shortened even if the sufficient light amount can be secured. Therefore, it cannot operate at high speed, resulting in a problem that the reading speed cannot be increased.

This problem essentially occurs because the transfer speed of the image data of the image sensor is lower than the processing speed of the image processing apparatus in the subsequent stage, and is not limited to the contact image sensor. In other image sensors such as CCDs, the same problem may occur if the transfer speed of the image data becomes lower than the processing speed of the image processing apparatus in the subsequent stage.

To solve this problem, Japanese Patent Laid-Open No. 56-
As can be seen in Japanese Patent No. 65565, an image sensor is composed of sensor regions of a plurality of channels, and an image for one line is divided and read by those sensor regions,
By simultaneously processing the image data output in parallel from the sensor area of each channel, even if the transfer rate of the image data of the sensor area of each channel is low, one line of image is converted into one image. Compared to the case of reading by the sensor, the photoelectric conversion elements included in each sensor area can be reduced by the amount of dividing the sensor area into a plurality of channels, so that the time required to read the image data for one line as a whole of the image sensor is reduced. Some can be shortened.

As described above, a plurality of image signals simultaneously output in parallel from the image sensor constituted by a plurality of sensor regions are either analog signals or converted into digital signals by an A / D converter. A general configuration is that after being multiplexed and converted into serial image data, it is processed by an image processing device at a subsequent stage.

In this configuration, the arrangement of pixel-based data (pixel data) forming the serial image data obtained by multiplexing is the same as the arrangement order in the image sensor of the photoelectric conversion elements that output the pixel data. Are different.

To be more specific, it is assumed that the image sensor is composed of two channel sensor regions of channel X and channel Y, and an image for one line is read by these two channels. In that case, channel X
Photoelectric conversion elements (elements x1 to xn) that configure the
Are spatially arranged in the order of x1, x2, ..., Xn, and similarly, the n photoelectric conversion elements (elements y1 to yn) forming the channel Y are spatially arranged as y1, y2. ,
..., yn are arranged in this order. Therefore, pixel x
If the pixel data output by k or the pixel yk (k is an integer of 1 to n) is Xk or Yk, respectively, the serial image data output from the conventional image sensor that does not divide into regions is X1, X2, ..., X
n, Y1, Y2, ..., Yn are output in this order, and the output order matches the spatial arrangement of the photoelectric conversion elements that output the pixel data. On the other hand, when reading images for one line in parallel on two channels, X, Y
Since image data is output simultaneously from both channels,
The array of serial image data obtained by multiplexing those image data is X1, Y1, X2, Y2, ...
, Xn, and Yn, which do not match the spatial arrangement of the photoelectric conversion elements that output those pixel data.

When serial image data in an order that does not match the spatial arrangement of the photoelectric conversion elements is input to the image processing circuit in the subsequent stage of the image sensor, it becomes difficult to form a spatial correction filter such as MTF correction, and very complicated processing is performed. A circuit is needed. Further, the serial image data output from the image sensor in an order that does not match the spatial arrangement of the photoelectric conversion elements is finally recorded by a predetermined recording method. In some cases, it is not possible to handle image data in an order that does not match the spatial arrangement of the elements.

Therefore, serial image data in an order that does not match the spatial arrangement of the photoelectric conversion elements is referred to in the above example so that the order matches the spatial arrangement of the photoelectric conversion elements prior to image processing. Then X1, Y1, X2,
The serial image data obtained in the order of Y2, ..., Xn, Yn are X1, X2, ..., Xn, Y1, Y2, ...
.., Yn are rearranged in this order, so-called sorting processing is required.

As a sorting method, some methods have been used conventionally, but the most general method is that the serial image data is once AD-converted and then stored in a memory and then stored at the time of reading. There is a method of sorting by controlling the addresses to read in different orders.

In practice, the image sensor outputs serial image data for each line while continuously reading the main scanning line while being sub-scanned. Therefore, a buffer having a capacity capable of storing image data for a plurality of lines. Have memory,
The serial image data for the main scanning line currently being read is stored in the buffer memory, and at the same time, the image data for the main scanning line read before the main scanning line currently being read and stored in the buffer memory. By performing a so-called toggle operation for reading the next main scanning line, the next main scanning line can be read without waiting for the image data of the previous main scanning line to be read from the buffer memory, and continuous sub-scanning can be performed. There are advantages. But,
For this reason, the memory capacity required for sorting image data requires, for example, 10 KB or more in the case of an image sensor that reads an A3 width at a density of 400 dpi, and a large chip area in the case of integrating an image processing circuit. Occupy, which is disadvantageous in terms of cost.

On the other hand, the sorted image data, which is sorted by the address control at the time of reading from the buffer memory and is sequentially output in synchronization with a predetermined clock, is directly processed by an image processing circuit in a subsequent stage to reduce an image. If image processing is performed, the processed image data obtained after the processing may be a series of intermittent data that is not synchronized with the predetermined clock, and the entire circuit may be synchronized with the predetermined clock. become unable. That is,
The entire circuit cannot be a synchronous circuit.

As is generally known, the advantage of the synchronous circuit is that the steps of a large-scale circuit can be perfectly aligned, the circuit design and analysis can be performed in order, and another LSI process can be performed. It can be easily deployed (transplanted) into Conversely, if the image processing is directly performed on the sorted serial image data, those advantages cannot be obtained.

Therefore, in order to perform the image processing on the image data while maintaining the synchronism of the entire circuit, the sorted serial image data which is sorted and output by the address control at the time of reading from the buffer memory is further lined. It is necessary to store the image data in the memory so that the image data subjected to the image processing can be continuously read by performing the image processing under the address control at the time of reading from the line memory.

Further, in the enlargement processing of the image, it is difficult to deal with the serial image data, and it is necessary to temporarily store and read it in the line memory to perform the enlargement processing. Further, many processes require a line memory for image editing / adjustment functions.

[0019]

As described above,
In a conventional image processing device, serial image data output from an image sensor including a plurality of sensor areas is temporarily stored in a buffer memory, and a read address of the image data stored in the buffer memory is controlled to sort the image data. Output as sorted serial image data, the output sorted serial image data is further stored in a line memory for image processing while maintaining circuit synchronization, and the image data stored in the line memory is read out. Since the image processing is performed by controlling the address, it is necessary to further provide a line memory different from the buffer memory for the sorting processing for the image processing, which causes a problem that the circuit scale is increased and the cost is increased. there were.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an image processing apparatus capable of performing image processing while maintaining circuit synchronism without adding a memory for image processing. To do.

[0021]

In order to achieve the above object, an image processing apparatus according to claim 1 is arranged such that an image of one line is divided and read by each of the channels of an image sensor which is divided by a plurality of sensor areas. In an image processing apparatus for processing serial image data obtained by sequentially switching the pixel data output by outputting the memory, the memory for storing the serial image data, and each pixel data forming the serial image data, Image data rearranging means for writing in the memory by matching the order of the addresses for storing the pixel data and the arrangement of the photoelectric conversion elements that output the pixel data in the image sensor, and the read address of the pixel data stored in the memory. Image scaling means for controlling image scanning and outputting image data that has undergone image scaling in the main scanning direction. Characterized in that was.

An image processing apparatus according to a second aspect is obtained by sequentially switching pixel data output in parallel from each of the channels of an image sensor that reads an image for one line by dividing an image of one line by a plurality of sensor areas. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data In the main scanning direction, the image data rearranging unit that writes the output photoelectric conversion elements in the image sensor in agreement with each other in the image sensor and the read address of the pixel data stored in the memory is skipped according to the scaling ratio. Image reduction means for outputting the image data reduced in size is provided.

An image processing apparatus according to a third aspect of the present invention is obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line by dividing an image of one line by a sensor area of a plurality of channels. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data Linear density conversion was performed in the main scanning direction by skipping the image data rearranging means that writes the photoelectric conversion elements in the image sensor in the same arrangement as the output photoelectric conversion elements in the memory, and the read address of the pixel data stored in the memory. And a linear density conversion means for outputting image data.

An image processing apparatus according to a fourth aspect of the present invention can be obtained by sequentially switching pixel data output in parallel from each of the channels of an image sensor that reads an image for one line by dividing the image of one line by a plurality of sensor areas. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data Image data rearranging means for writing in the memory by matching the output photoelectric conversion elements with the array in the image sensor and the read address of the pixel data stored in the memory to control the image of the same address according to the scaling ratio. An image in which data is read redundantly and image data enlarged in the main scanning direction is output. Characterized in that a large unit.

An image processing apparatus according to a fifth aspect is obtained by sequentially switching pixel data output in parallel from each of the channels of an image sensor for reading an image for one line by dividing the image of one line by a plurality of sensor areas. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data The image data rearranging means for writing the output photoelectric conversion elements in the image sensor in alignment with each other and the read address of the pixel data stored in the memory are controlled to output the image edited image data. And an image editing means.

An image processing apparatus according to a sixth aspect of the present invention is obtained by sequentially switching pixel data output in parallel from each of the channels of an image sensor for reading an image for one line by dividing an image for one line by a sensor area of a plurality of channels. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data Image data rearranging means that matches the output photoelectric conversion elements in the image sensor and writes the same in the memory, and the read address of the pixel data stored in the memory are controlled to reverse the image data from the final image data. And an image inverting means for reading out the image data and outputting the image data in which the image is inverted in the main scanning direction. Characterized by comprising.

An image processing apparatus according to a seventh aspect is obtained by sequentially switching pixel data output in parallel from each of the channels of the image sensor for reading an image for one line by dividing the image of one line by the sensor regions of a plurality of channels. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data Image data rearranging means that writes the photoelectric conversion elements in the image sensor in alignment with the output photoelectric conversion elements, and controls the read address of the pixel data stored in the memory to sequentially shift the read start address line by line. And italic processing means for outputting image data subjected to italic processing And it features.

The image processing apparatus according to the present invention can be obtained by sequentially switching pixel data output in parallel from each of the channels of the image sensor for reading an image of one line divided by the sensor regions of a plurality of channels. In an image processing device for processing serial image data, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the pixel data Image data rearranging means that writes the output photoelectric conversion elements in the image sensor in agreement with the array of the photoelectric conversion elements, and image data from the read start address set by controlling the read address of the pixel data stored in the memory And an effective image range output means for reading and outputting To.

[0029]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
Embodiments of the present invention will be described in detail.

FIG. 1 shows an image processing apparatus according to the present invention,
The block structure of the image sensor which inputs serial image data into the image processing apparatus is shown. The image processing apparatus is provided in the copying machine and performs various kinds of image processing described later according to an instruction from the copying machine main body.

In the figure, the one-dimensional image sensor 1
Reads an image for one line of main scanning divided by the sensor regions of four channels of A, B, C and D, and each channel is generated by the clock source 2 based on the pixel clock which is the basic clock. The serial image data Sa, Sb, Sc and Sd synchronized with the generated clock are output in parallel. The one-dimensional image sensor 1 sequentially reads the main scanning lines while being relatively moved in the sub-scanning direction with respect to the read document by a sub-scanning driving unit (not shown).

The one-dimensional image sensor 1 is composed of 4864 photoelectric conversion elements arranged in a line in order to read a document of maximum A3 size at 400 dpi.
The 64 photoelectric conversion elements are allocated to each of the four channel sensor areas of the A, B, C, and D channels by a quarter, that is, by 1216. Here, the sensor region of the A channel is the photoelectric conversion element a1,
, a1216 are arranged in order, and similarly, the B channel has photoelectric conversion elements b1, b2, ..., B1.
216 are arranged in order, the C channel is composed of photoelectric conversion elements c1, c2, ..., C1216 arranged in order, and the D channel is composed of photoelectric conversion elements d1, d.
, ..., d1216 are arranged in this order, and the photoelectric conversion element a1,
a2, ..., a1216, b1, b2, ..., b1216,
c1, c2, ..., c1216, d1, d2, ..., d12
They are arranged in a line in the order of 16. Further, pixel data output from those photoelectric conversion elements ak, bk, ck, or dk (k is an integer of 1 to 1216) is respectively pixel data Ak, Bk, Ck, or Dk (k is 1
Through 1216).

Therefore, the serial image data Sa, Sb, Sc and S output from the sensor area of each channel.
d is pixel data A1, A2, ..., A121, respectively.
6, pixel data B1, B2, ..., B1216, pixel data C1, C2, ..., C1216, and pixel data D
1, D2, ..., D1216 are connected.

FIG. 2 shows the serial image data Sa,
The output signals of Sb, Sc and Sd are shown. In the figure, each serial signal is composed of a pixel signal synchronized with a clock having a cycle of four times the pixel clock, and each serial signal has a clock having a cycle of four times the pixel clock in the order of Sa, Sb, Sc, and Sd. Phase shifted by a quarter cycle,
In other words, the output is performed with a phase shifted by one pixel clock.

In other words, regarding the sensor area of each channel, pixel data can be output only in a cycle four times as long as the pixel clock, but after the pixel data from a photoelectric conversion element having a specific channel is output, While the pixel data is output from the photoelectric conversion element adjacent to the conversion element, each of the other three channel sensor areas can output the pixel data, and the one-dimensional image sensor 1 as a whole has a cycle of four times the pixel clock. 4 pixel data in between,
In other words, one pixel data can be output with one pixel clock, and an image for one line can be read at a speed four times faster than when the one-dimensional image sensor 1 is not divided into channels. .

In this way, the serial image data output from the sensor area of each channel with their phases shifted from each other is
The respective impedances are converted by the buffer amplifiers 3a, 3b, 3c and 3d and then input to the analog multiplexer 4. It is also possible to output the serial image data in the same phase without shifting the phase and output the same, and after the output, to shift the phase by the sample and hold circuit.

In FIG. 1, the analog multiplexer 4
Is synchronized with the pixel clocks (1, 1) provided from the frequency-dividing circuit 2a and the frequency-dividing circuit 2b that divide the pixel clock output from the clock source 2 by 2 and 4, respectively (1, 1), By a 2-bit selection signal that is cyclically generated in the order of (0,1), (1,0), (0,0),
Input serial image data Sa, Sb, Sc or S
As shown in FIG. 2, d is cyclically switched and output in the order of A, B, C, D, A, B channels ... In synchronization with the pixel clock.

The serial image signal Sma output from the analog multiplex 4 is quantized into digital data by the AD converter 5 and output as serial image data Smd. As shown in FIG. 2, the order of the pixel data forming the serial image data Smb is A1, B2,
The order is C1, D1, A2, ..., Which does not match the arrangement of the photoelectric conversion elements outputting those pixel data in the one-dimensional image sensor.

The serial image data Smd is stored in the pair of buffer memories 6a or 6b. The pair of buffer memories 6a receives serial image data Sm for a specific line on one side in response to a control signal from the address controller 7.
In parallel with writing d, the image data for the main scanning line which is one line before the specific line is read from the other. Specifically, each of the buffer memories 6a and 6b is provided with a CE signal input for enabling access to each memory, and an access control signal is input from the address control unit 7 to these CE signal inputs. ing.

As a result, the address control section 7 outputs a signal synchronized with the pixel clock supplied from the clock source 2 as an access control signal, so that the signal level is H (High) in the first half of one clock cycle and in the latter half. L (L
When the signal level of the pixel clock that becomes ow) is H, the access control signal to the buffer memory 6a is set to H to enable access to the buffer memory 6a, and when the signal level is L, access control to the buffer memory 6b is performed. The signal can be set to H to enable access to the buffer memory 6b and vice versa.

Further, each of the buffer memories 6a and 6b has an R / W signal input for setting whether to be in a read mode for reading image data from each memory or in a write mode for writing image data in each memory. Is equipped with. The address control unit 7 is connected to the R / W signal inputs.
The read / write control signal from is commonly input. If the read / write control signal is H, the read mode is set, and if it is L, the write mode is set.

By combining the CE signal input and the R / W signal input, the image data is read from one of the pair of buffer memories in the first half of the pixel clock, and the image data is written in the other in the second half. It becomes possible.

When writing the serial image data Smd to the buffer memory 6a or 6b, the storage address of the pixel data forming the serial image data Smd is determined by the address output from the address control unit 7.
In the present embodiment, as will be described later, the address control unit 7
2 by the address control, the order of the addresses of the buffer memory that stores each pixel data forming the serial image data Smd and the pixel data are output, as in the array of sorted pixel data shown in FIG. Match the arrangement of the photoelectric conversion elements in the one-dimensional image sensor 1 (hereinafter, this processing is referred to as sorting processing),
Write to the buffer memory 6a or 6b.

FIG. 3 conceptually shows the memory layout of the pixel data sorted and stored in the buffer memory 6a or 6b. In the figure, from address 0000h to 04BFh, pixel data from the A channel is stored from A1 to A1216 in the order of arrangement of the photoelectric conversion elements. At addresses 04C0h to 097Fh, pixel data from the B channel is stored from B1 to B1216 in the arrangement order of the photoelectric conversion elements. At addresses 0980h to 0E3Fh, pixel data from the C channel is stored from C1 to C1216 in the arrangement order of the photoelectric conversion elements. At addresses 0E40h to 12FFh, pixel data from the D channel are stored from D1 to D1216 in the order of arrangement of the photoelectric conversion elements. By storing the pixel data from each channel as described above, the corresponding pixel data is stored at the address in the arrangement order of the photoelectric conversion elements of the entire one-dimensional image sensor 1.

Next, write address control in the address control unit 7 when the serial image data Smd is sorted and written in the buffer memory 6a or 6b, and
The read address control will be described in detail below.

FIG. 4 shows a schematic block configuration of the address generator of the address controller 7. In the figure, the address generation unit includes a read address generation unit 8, a write address generation unit 9, and a multiplexer 10 that alternately outputs the read address and the write address output from each of the address generation units. It is configured. A pixel clock is input to them as a common clock and operates in synchronization with the pixel clock.

The multiplexer 10 sets the pixel clock to 1
As a bit selection signal, the read address is output in the first half H period of the one cycle, and the write address is output in the second half L period.

Further, the read address generator 8 receives a reset signal, an initial value setting signal, a line sync signal, an up / down selection signal, an italic selection signal and a clock thinning request signal from the main body of the copying machine.

FIG. 5 shows an example of address generation by the address generator of the address controller 7, which will be described in detail later. In the figure, the sorting process is performed to perform the buffer memory 6a or 6
The case where the image data written in b is simply read in the order of addresses is shown. That is, the case where the image data is output as it is without performing any image processing is shown.

In the figure, the read address output from the read address generation unit 8 and the write address output from the write address generation unit 9 are output independently of each other in synchronization with the pixel clock.

The write address is A1, B1, C1, D
0h, 04C for the serial image data Smd input to the buffer memory 6a or 6b in the order of 1, A1, ...
The serial image data Smd generated in the order of 0h, 0980h, 0E40h, 1h are subjected to a sorting process.

On the other hand, the read address is 0h, 1h, 2 when reading the sorted pixel data in order.
It is generated in the order of h, 3h, 4h, ....

The write address and the read address are the multiplexer 1 using the pixel clock as the selection signal.
It is cyclically switched by 0, output as an address, and given to the buffer memories 6a and 6b.

A common address is given to the buffer memories 6a and 6b, but since these buffer memories are simultaneously controlled by the CE signal and the read / write control signal as described above, a problem occurs. Absent. As a result, the serial image data Smd is written in one buffer memory while being sorted, while the image data is cyclically read out from the other buffer memory, thereby enabling stagnation-free sub-scanning.

FIG. 6 shows the detailed structure of the write address generator 9. In the figure, the write address generation unit 9 is provided with up counters 11A to 11D corresponding to the sensor areas of the A, B, C and D channels that constitute the one-dimensional image sensor 1, and these up counters are respectively provided. 0h, 04C0h, 098 as initial value
0h. 0E40h is set, and the count value outputs of those up counters are flip-flops 12A using the pixel clock divided by 4 by the divide-by-4 circuit 13 as a trigger signal.
Through 12D, the latched count value becomes an input value of each up counter, and each up counter adds 1 to the input value and outputs it.

Therefore, the output count value of each flip-flop is incremented by 1 every four cycles of the pixel clock, and the initial value set in the corresponding up counter is added, and the output count value of the flip-flop 12A is 0000.
h, 0001h, 0002h, 0003h, 0004
The output count value of the flip-flop 12B is 04C0.
h, 04C1h, 04C2h, 04C3h, 04C4
h, ... The output count value of the flip-flop 12C is 0980.
h, 0981h, 0982h, 0983h, 0984
The output count value of the flip-flop 12D is 0E40.
h, 0E41h, 0E42h, 0E43h, 0E44
From each initial value, 1 every 4 cycles of the pixel clock.
Just increase.

The count value output from each of these flip-flops is input to the multiplexer 14. The multiplexer 14 divides the pixel clock into two and four, respectively.
In synchronization with the pixel clocks given from the frequency-dividing circuit 15 and the frequency-dividing circuit 13 for frequency division, (1, 1), (0,
1), (1, 0), (0, 0) are cyclically generated in the order of 2 bits, and the count value output from each of the flip-flops is synchronized with the pixel clock by 12 A, 12B, 12C, and 12D are cyclically switched and output.

As a result, the write address output from the multiplexer 14 is 0000h, 04C0h, 0.
980h, 0E40h, 0001h, 04C1h, 09
81h, 0E41h, ... will be generated in that order,
Buffer memory 6 at the address indicated by the write address
Serial image data Smd sequentially stored in a or 6b
Are sorted by being written in the buffer memory 6a or 6b. Therefore, by controlling the read address from the buffer memory 6a or 6b, image processing in synchronization with the pixel clock becomes possible.

FIG. 7 shows a detailed configuration of the read address generator 8 having a configuration for performing various image processes by controlling the read address.

In the figure, the up / down counter 16
Uses the output from the multiplexer 17 as an initial value and selects a count increase / decrease value from (+1, +2, +3, -1) in accordance with an input up / down selection signal to count up or down. . The count value output of the up / down counter 16 is latched by a flip-flop 19 that uses the pixel clock as a trigger signal through the thinning circuit 18 for thinning the pixel clock in response to the clock thinning request signal, and the latched cant value is It becomes the input value of the up / down counter 16. Therefore,
The up / down counter 16 adds or subtracts the count increase / decrease value set by the up / down selection signal to the input value and outputs the value.

Therefore, the output count value of the flip-flop 19 for latching the output of the up / down counter 16, that is, the read address is the up / down counter 1
With the initial value set to 6 as the initial value, the thinning circuit 18
In the step S1, the increase / decrease is set by the increase / decrease value set for each cycle of the pixel clocks to be thinned out.

The initial value set in the up / down counter 16 is the output value of the multiplexer 17 as described above, but the multiplexer 17 switches one of the two inputs and outputs it according to the italic selection signal. To do.

The two inputs of the multiplexer 17 are the outputs of the flip-flops 20 and 21, respectively. The flip-flop 20 latches the input initial value using the line sync signal as a trigger signal, and always latches the input initial value and outputs it as a fixed initial value.

On the other hand, the flip-flop 21 latches the output of the up counter 22 with the line sync signal as a trigger signal. The up counter 22 is
The flip-flop 21 with the input initial value as the initial value
The output value from is incremented by one.
Therefore, the output count value of the flip-flop 21 is, every time a line sync signal is input, with the initial value input to the up counter 22 as an initial value until the reset signal is input to the up counter 22, that is,
Each time one main scanning line is read, it is incremented by one.

Next, some of the processing examples in which the read address generating unit 8 configured as described above controls the read address according to an instruction from the copying machine main body to perform various image processing will be described in order. explain. In the image processing example described below, the processing of sorting the serial image data Smd into the buffer memory 6a or 6b and inserting the serial image data Smd into each is common processing, and thus the description thereof is omitted.

First, a case will be described in which normal read address control for reading the sorted image data written in the buffer memory as shown in FIG.

In this case, 0h is selected as the initial value for the up counter 22 and the flip-flop 20 of the read address generator 8 and the input of the multiplexer 17 is
The italic selection signal as the selection signal is set so that italic is not selected (normal), so that the flip-flop 2
It is switched to the 0 side. As a result, a constant initial value (0h) is input as the initial value input to the up / down counter 16.
Is selected. In addition, +1 is set as the up / down selection signal input to the up / down counter 16, and the pixel clock thinning request signal is not generated.

With the above settings, the read address generator 8 generates a read address that is incremented by 1 from the initial value 0h, and the buffer memory 6a or 6b outputs image data of the same size in synchronization with the pixel clock. The image data of the same size is processed by an image recording unit in the subsequent stage (not shown) and recorded and output as an image as it is read by the one-dimensional image sensor 1.

Next, address control for reading the reduced image data by skip-accessing the read address of the image data stored in the buffer memory 6a or 6b will be described with reference to the timing chart of FIG.

In the case of performing the read address control shown in the figure, 0h is selected as the initial value for the up counter 22 of the read address generator 8 and the multiplexer 17
The input of is switched to the flip-flop 20 side when the italic selection signal as the selection signal is set so that italic is not selected (normal). As a result, a constant initial value (0h) is selected as the initial value input to the up / down counter 16. Further, the thinning request signal for the pixel clock is not generated.

The up / down selection signal input to the up / down counter 16 is initially set to +1 and, for example, when the read address is incremented to 0h and 1h, the up / down selection signal is set to +2 to read. Address skips to 3h. Then, the up / down selection signal is returned to +1 again, and when the address becomes 4h, the up / down selection signal is set to +2 again to skip the address to 6h. By this operation, the image data stored at the addresses 2h and 5h can be thinned out, and the image data can be continuously read in synchronization with the pixel clock.

When the scaling ratio of reduction is in the range of 50% to 100%, the up / down selection signal is increased by +1 according to the scaling ratio.
By switching between +2, it is possible to reduce at any magnification. That is, the up / down selection signal is +
If it is fixed to 1, the scaling factor is 100%, and if the up-down selection signal is fixed to +2, the scaling factor is 50%. Therefore, any scaling factor in the meantime is the ratio between +1 and +2 of the up-down selection signal. It can be realized by changing. Similarly, a scaling factor of 33% to 50%
In the range, the up / down selection signal can be switched between +2 and +3 in accordance with the scaling factor to enable reduction at any scaling factor.

Next, address control for reading out the image data whose line density has been converted by skip-accessing the read address of the image data stored in the buffer memory 6a or 6b will be described with reference to the timing chart of FIG.

When performing the read address control shown in the figure, 0h is selected as an initial value for the up-counter 22 and the flip-flop 20 of the read address generator 8, and the input of the multiplexer 17 serves as its selection signal. The italic selection signal is switched to the flip-flop 20 side by setting the italic to not select (normal). As a result, a constant initial value (0h) is selected as the initial value input to the up / down counter 16. Further, the thinning request signal for the pixel clock is not generated.

The up / down selection signal input to the up / down counter 16 is set to +2. As a result, the read addresses are 0h, 2h, 4h, 6h, 8
The image data at the odd-numbered addresses generated in the order of h ... Are thinned out, and the image data converted into the linear density image ½ can be read in synchronization with the pixel clock.

Next, regarding the address control for reading the enlarged image data by stopping the increment of the read address of the image data stored in the buffer memory 6a or 6b at the appropriate time and reading the image data of the same address in duplicate, the timing chart of FIG. Will be described with reference to.

When performing the read address control shown in the figure, 0h is selected as an initial value for the up counter 22 and the flip-flop 20 of the read address generator 8 and the input of the multiplexer 17 is used as a selection signal thereof. The italic selection signal is switched to the flip-flop 20 side by setting the italic to not select (normal). As a result, a constant initial value (0h) is selected as the initial value input to the up / down counter 16. The setting of the up / down selection signal input to the up / down counter 16 is fixed to +1.

In order to stop the advance of the read address, the thinning-out circuit 18 thins out the rising edge of the pixel clock by setting the clock thinning-out request signal to the H level in accordance with the enlargement ratio, and the thinning-out circuit 18 thins out the pixel clock. By holding the read address that is the output of the flip-flop 19 that uses as a trigger signal, the advance of the read address is stopped. For example, if the image data of the same address is read twice, it will be expanded by 200%.
As shown in, if every other image data is read twice,
It is a 50% expansion. As a result, the enlarged image data can be read in synchronization with the pixel clock.

Next, regarding the address control for reading out the image data subjected to the image inversion (mirroring) by decrementing the read address of the image data stored in the buffer memory 6a or 6b and reading from the last pixel data of the line, FIG. This will be described with reference to the timing chart.

When performing the read address control shown in the figure, the up counter 22 and the flip-flop 20 of the read address generator 8 are not 0h as an initial value but an address (12F) at which the final pixel data is stored.
F) is set. The input of the multiplexer 17 is switched to the flip-flop 20 side when the italic selection signal as the selection signal is set so as not to select italics (normal). As a result, the up / down counter 1
Constant initial value (12FFh) as the initial value input to 6
Is selected. Further, -1 is set as the up / down selection signal input to the up / down counter 16, and the pixel clock thinning request signal is not generated.

As a result, the final pixel data (address 12
The image data can be read while decrementing the read address from (FFh), and as shown in FIG. 12, the image data obtained by mirroring the image read by the one-dimensional image sensor 1 is continuously synchronized with the pixel clock. Can be read.

Next, address control for reading the image data subjected to italic processing by shifting the initial value of the read address of the image data stored in the buffer memory 6a or 6b in line units will be described with reference to FIG.

When performing the read address control shown in the figure, 0h is selected as an initial value for the up counter 22 and the flip-flop 20 of the read address generator 8, and the input of the multiplexer 17 is used as its selection signal. When the italic selection signal is set to select italic, it is switched to the flip-flop 21 side. As a result, the output value of the flip-flop 21 is selected as the initial value input to the up / down counter 16. Further, the thinning request signal for the pixel clock is not generated.

The output value of the flip-flop 21 is obtained by latching the output of the up counter 22 by the line sync signal, and the up counter 22 increments the output value of the flip-flop 21 from the initial value (0h). Therefore, the read address output by the read address generation unit 8 is such that the start address is incremented by 1 each time the main scanning line advances, and the image data read in synchronization with the pixel clock by the read address is As shown in FIG. 14, the image read by the one-dimensional image sensor 1 is subjected to italic processing. If the increment width of the up counter 22 can be selected to be +2, +3, -1, or the like,
The angle of italics will be selectable. Further, if a white pixel area between lines of a read character original is detected and reset input is made to the up counter 22 for each character line, the entire image is not italicized but the start position of each character line is determined. It is also possible to italicize only the character while keeping it constant.

Further, by arbitrarily setting the initial value input to the up counter 22 and the flip-flop 20, it becomes possible to read the image data with the set initial value as the start address of the effective image range, which is unnecessary. The image data excluding a large image range can be obtained in synchronization with the pixel clock.

In the embodiment described above, the buffer memories 6a and 6b for two lines each having a capacity for one main scanning line are read and written alternately on a line-by-line basis. Although the present invention has been applied, the present invention is not limited in its application by the number of lines in the buffer memory.

Further, in the embodiment described above, the contact image sensor is assumed as the one-dimensional image sensor 1, but the present invention is not limited to this, and a CCD image sensor or the like having a similar output configuration is also applicable. The same applies.

[0088]

According to the first aspect of the invention, serial image data obtained by dividing and reading an image for one line by the sensor regions of a plurality of channels is sorted and read by controlling the write address to the memory. Since the image scaling processing in the main scanning direction is performed by controlling the address, it is possible to perform the image scaling processing that maintains the circuit synchronism without adding a new memory for the image scaling processing.

According to the second aspect of the invention, the serial image data obtained by dividing the image of one line by the sensor regions of a plurality of channels and reading the image is sorted by controlling the write address to the memory, and the read address is set. Since the image reduction processing in the main scanning direction is performed by skipping, it is possible to perform the image reduction processing that maintains the circuit synchronism without adding a new memory for the image reduction processing.

According to the third aspect of the invention, the serial image data obtained by dividing the image of one line by the sensor regions of a plurality of channels and reading the image is sorted by controlling the write address to the memory, and the read address is set. By skipping, the line density conversion process in the main scanning direction is performed by thinning out the image data, so it is possible to perform the line density conversion process that maintains circuit synchronism without adding a new memory for the line density conversion process. Become.

According to the fourth aspect of the invention, the serial image data obtained by dividing the image of one line by the sensor areas of a plurality of channels and reading the image is sorted by controlling the write address to the memory, and the read address of the read address is stored. An image that retains circuit synchronism without adding a new memory for image enlargement processing because image enlargement processing in the main scanning direction is performed by reading out image data at the same address redundantly by stopping the increment Enlargement processing becomes possible.

According to the invention of claim 5, serial image data obtained by dividing an image of one line by the sensor regions of a plurality of channels and reading the image is sorted by controlling the write address to the memory, and the read address of the read address is stored. Since the image editing process is performed by the control, it is possible to perform the image editing process maintaining the synchronism of the circuit without adding a new memory for the image editing process.

According to the sixth aspect of the invention, serial image data obtained by dividing and reading an image for one line by the sensor regions of a plurality of channels is sorted by controlling the write address to the memory, and the read address of the serial address is read. Since the image data is read out from the final image data in the reverse direction by the control and the image inversion processing is performed, the image inversion processing with circuit synchronism can be performed without adding a new memory for the image inversion processing.

According to the invention of claim 7, serial image data obtained by dividing an image of one line by the sensor regions of a plurality of channels and reading the image is sorted by controlling the write address to the memory, and the read address is read. Since the italic processing is performed by sequentially shifting the read start address for each line under the control, it is possible to perform the italic processing while maintaining the circuit synchronism without adding a new memory for the italic processing.

According to the eighth aspect of the invention, serial image data obtained by dividing an image of one line by the sensor regions of a plurality of channels and reading the sorted image data is sorted by controlling the write address to the memory, and the read address is read. Since the image data of only the effective image range is output by reading and outputting the image data from the read start address set by the control, the circuit synchronism can be achieved without adding a new memory for the effective image range output processing. It becomes possible to output the effective image range that holds.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an image processing apparatus according to an embodiment of the present invention and a one-dimensional image sensor that inputs serial image data thereto.

FIG. 2 is a schematic timing chart showing serial image signals and the like output from the sensor area of each channel.

FIG. 3 is a schematic diagram showing a storage order of pixel data stored in a buffer memory.

FIG. 4 is a block configuration diagram of an address control unit.

FIG. 5 is a timing chart of addresses generated in normal address control.

FIG. 6 is a block configuration diagram of a write address generation unit.

FIG. 7 is a block configuration diagram of a read address generation unit.

FIG. 8 is a timing chart of addresses generated in reduction address control.

FIG. 9 is a timing chart of addresses generated in address control for linear density conversion.

FIG. 10 is a timing chart of addresses generated in enlarged address control.

FIG. 11 is a timing chart of addresses generated in address control of mirroring.

FIG. 12 is a schematic diagram showing a comparison between an image before the mirroring process and an image after the mirroring process.

FIG. 13 is a timing chart of addresses generated in address control of italic processing.

FIG. 14 is a schematic diagram showing a comparison between an image before italic processing and an image after italic processing.

[Explanation of symbols]

1 one-dimensional image sensor 2 clock sources 3a, 3b, 3c, 3d buffer amplifier 4 multiplexer 5 A / D converter 6a, 6b buffer memory 7 Address control section 8 Read address generator 9 Write address generator 10 multiplexer 11a, 11b, 11c, 11d up counter 12a, 12b, 12c, 12d flip-flops 13 4 divider circuit 14 Multiplexer 15 2 frequency divider 16 up-down counter 17 Multiplexer 18 thinning circuit 19, 20, 21 flip-flops 22 up counter

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 1/21 H04N 1/04 102

Claims (8)

(57) [Claims] 1. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line by dividing the image of one line by a sensor region of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means that matches the arrangement in the sensor and writes it in the memory, and image scaling that outputs the image data that has been image scaled in the main scanning direction by controlling the read address of the pixel data stored in the memory. And an image processing apparatus. 2. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line by dividing the image of one line by a sensor region of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing the data in the memory while matching the arrangement in the sensor, and skipping the read address of the pixel data stored in the memory according to the scaling ratio, and outputting the image data reduced in the main scanning direction. An image processing device comprising: 3. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image of one line divided by a sensor area of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing in the memory while matching the arrangement in the sensor, and linear density conversion for skipping the read address of the pixel data stored in the memory and outputting the image data subjected to the linear density conversion in the main scanning direction. And an image processing apparatus. 4. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line by dividing the image of one line by a sensor region of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing the data in the memory while matching the arrangement in the sensor, and the read address of the pixel data stored in the memory are controlled to duplicately read the image data of the same address according to the scaling ratio, and main scanning is performed. Image enlargement means for outputting image data in which the image is enlarged in the direction The image processing apparatus. 5. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line by dividing the image of one line by a sensor area of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing the data in the memory in conformity with the array in the sensor, and image editing means for controlling the read address of the pixel data stored in the memory and outputting the image-edited image data An image processing device characterized by: 6. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image for one line divided by a sensor area of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means that matches the arrangement in the sensor and writes the image data in the memory, and the read address of the pixel data stored in the memory is controlled to read the image data in the reverse direction from the final image data to form the image in the main scanning direction. An image comprising: an image inverting means for outputting the inverted image data. Management apparatus. 7. Image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image of one line divided by a sensor region of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing the data in the memory while matching the array in the sensor, and controlling the read address of the pixel data stored in the memory to sequentially shift the read start address line by line to display the image data subjected to italic processing. An image processing apparatus comprising: italic processing means for outputting. 8. An image processing for processing serial image data obtained by sequentially switching pixel data output in parallel from each channel of an image sensor for reading an image of one line divided by a sensor region of a plurality of channels. In the apparatus, a memory for storing the serial image data, each pixel data forming the serial image data, an order of addresses for storing the pixel data, and the image of the photoelectric conversion element that outputs the pixel data. Image data rearranging means for writing the data in the memory while matching the array in the sensor, and an effective image range for reading and outputting the image data from the read start address set by controlling the read address of the pixel data stored in the memory An image processing apparatus comprising: an output unit.