JP2887840B2 - Image reading device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus that reads an original image by using a plurality of photoelectric conversion elements and overlapping areas to be read by adjacent photoelectric conversion elements.

[Conventional technology]

2. Description of the Related Art In a digital copying machine, a facsimile, or the like, it is generally known to read a document image by using a plurality of photoelectric conversion elements and overlapping the read areas of adjacent photoelectric conversion elements.

[Problems to be solved by the invention]

In the above prior art, when a plurality of photoelectric conversion elements are used to read a halftone original having a certain density, the read image data values are not the same due to the difference in sensitivity between the photoelectric conversion elements. There are various methods for adjusting the sensitivity to obtain the same value, but all of them involve complicated work or an increase in development costs, and despite this, it is almost impossible to completely match them. If halftone processing, for example, a dither method, is performed while the read image data values are different, a difference in density occurs at the boundary of the read image switching position of the final output image due to a difference in dither texture, giving a sense of incongruity. Also, when performing character processing, such as MTF correction,
Depending on the magnitude of the density difference, black streaks, white streaks, and the like appear, and there is a problem that a sense of incongruity occurs as in the case of halftone.

Further, when three or more photoelectric conversion elements are used, the read data of each photoelectric conversion element is processed collectively into one line data, so that the processing speed is slow.

The present invention has been made in view of such a point, and an object of the present invention is to improve processing speed and improve image quality in an image reading apparatus that reads one-line data using three or more photoelectric conversion elements. It is an object of the present invention to provide an image reading apparatus that can improve both.

[Means for solving the problem]

In order to achieve the above object, a first means is an image reading apparatus that reads original image information by using three or more photoelectric conversion elements to overlap areas read by adjacent photoelectric conversion elements. And a combining / separating means for combining and separating the document image information output from each of the photoelectric conversion elements during the scan synchronization period by dividing into two right and left from the median value of the photoelectric conversion elements. Means for storing image information output from the storage means, read / write control means for controlling reading and writing of the storage means, and an area where read image information of adjacent photoelectric conversion elements read from the storage means overlaps And an interpolating means for interpolating an adjacent pixel at a switching position of read image information of an adjacent photoelectric conversion element. To.

The second means is a smoothing means according to the first means, wherein the interpolation means is replaced with a smoothing means for smoothing an adjacent pixel at a switching position of read image information of an adjacent photoelectric conversion element. And

[Action]

According to the above means, the document image information output from each of the photoelectric conversion elements during the scan synchronization period is divided into two parts from the center value of the maximum document width and the document image information is output from the central part in the main scanning direction of the document in the down direction and the up direction At the same time, and writing and reading are alternately performed from the storage device and processed as one line of information. At this time, the overlapping portion between the adjacent photoelectric conversion elements is subjected to an interpolation process or a smoothing process to improve the image quality.

〔Example〕

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a circuit diagram showing an embodiment of an image reading apparatus according to the present invention, wherein 51 to 54 are 3-state buffers, 55 to 58 are toggle rams, 59 to 61 are selectors, and 62 is an interpolation circuit.

It is easier to understand the detailed description of FIG. 1 while explaining the other components, and the description will be made in order below.

FIG. 2 is a schematic configuration diagram illustrating an image reading apparatus using the present invention. In the drawing, reference numerals 1 to 4 denote conveying rollers, 5 denotes an illumination device, 6 denotes an optical lens, and 7 denotes a CCD (photoelectric conversion element) constituting an image sensor. In this configuration, a document is fed in the direction of the arrow in the figure and is transported by transport rollers 1-4. During this conveyance, the original image illuminated by the illumination device 5 is formed on the CCD 7 by the optical lens 6.

In this case, since the number of effective reading pixels per CCD7 is determined, the width of the original that can be read is determined if the original reading density is determined, but if the original is wider than the original width that can be read by the CCD, Multiple CCDs must be used.

In the above embodiment, it is assumed that the effective read pixels per CCD 7 are 5000 pixels, the maximum document width of the document to be read is 917 mm, and the document reading density is 16 pixels / mm. Here, the number of CCD7 used is the maximum document width of 917 mm above,
Maximum reading pixel number is 1 from document reading density of 16 pixels / mm
Since 4672 pixels are required, and the number of effective read pixels per CCD7 is 5,000 as described above, three pixels are required.

FIG. 3 and FIG. 4 are schematic diagrams for explaining the relationship when the above-mentioned three CCDs 7 are used. D is the maximum original width, 6a ~
6c denotes an optical lens, 7a to 7c denote CCDs, and OR, X, Y denote the overlapping of the CCD reading areas. In FIG. 3, three image sensors (CCDs) 7a to 7c are used to read the maximum document width D. Each CCD is formed by an optical lens 6a to 6c,
The read areas of the CD overlap as indicated by the OR. The overlapping area amount is set to (15000−14672) 6722 = 164 pixels or less, and is adjusted so as to satisfy the maximum reading original width D.

Original images formed on the CCDs 7a to 7c are output from these CCDs 7a to 7c as analog signals, but since these signals are extremely small, these outputs must be amplified.

FIG. 5 is a block diagram schematically showing a circuit for processing an original image output from a CCD. In the figure, 7a to 7c are CCDs, 8a to 8
c is an amplifier, 9a to 9d are analog / digital conversion (A / D) circuits, and 10a and 10b are synthesis / separation circuits. In FIG. 5, C
Outputs of the CDs 7a to 7c are amplified by amplifiers 8a to 8c. Amplifier 8a
8c are converted from analog image signals into multi-valued (for example, 64 gradation) digital image signals for each pixel in A / D conversion circuits 9a to 9c. The digital image signal after A / D conversion is noise of the original image, unevenness of light intensity, dirt on the contact glass, CCD
Noise appears in the regular image data due to sensitivity unevenness of the image.
Therefore, as a countermeasure against this noise, shading correction has been conventionally performed in the A / D conversion circuit. As described above, the outputs from the respective CCDs are amplified, subjected to shading correction and A / D converted, and input to the combining / separating circuits 10a and 10b as multi-valued data.

FIGS. 6 and 7 are time charts in which the CCDs are simultaneously scanned and output pixel data at the same time. This timing is determined by the scanning synchronization signal C (LSYNC) as shown in the time chart of FIG.
7c is synchronized in the main scanning direction, and valid data from the CCDs 7a to 7c is controlled by an input control signal D (IN LGATE).

In the sub-scanning direction (insertion speed) of the document, it is assumed that LSYNC outputs a control signal 16 times per 1 mm of sub-scanning. Therefore, the sub-scanning density is also 16 pixels / mm, and the main scanning density is 1 pixel.
It is equal to 6 pixels / mm. The scan synchronization signal is output at regular intervals in order to make the charge accumulation time of the CCD constant.

At present, the image data from the three CCDs 7a to 7c are analog-processed in parallel between the scan synchronization signals. However, as described above, the correction of the amount of overlap between the CCD images, the digital processing unit after the analog processing [ For example, scaling processing, MTF (modulation transfer function) processing, smoothing processing, etc.) also require three CCs due to the need to process data during the period of the scan synchronization signal.
The output data from D is made into one line, and the amount of overlap is corrected. However, if the output data of the three CCDs 7a to 7c is combined into one line during the period of the scan synchronization signal, the processing speed of image data per pixel is tripled.

In the present invention, the CCD1
When processing 5,000 pixels per pixel, the processing time per pixel is 62.5 ns / 1 pixel, but when 3 CCD data are combined into one line during 312.5 μs, it becomes 20.8 ns / 1 pixel, processing Time is three times faster. However, the present invention
Instead of collecting the output data of three CCDs on one line, the median value of the maximum document width D (here, 2 of CCD7b in FIG. 3)
(The 449th pixel is defined as the center pixel), and data of 7,500 pixels is processed during the scanning synchronization signal period.

For this reason, the processing time is reduced to half compared to the case where the output data of the CCD is collected on one line.

FIG. 4 shows the amount of overlap between CCDs. X is CCD7b, 7
c is the overlap amount, and Y is the overlap amount of the CCDs 7a and 7b.

As described above with reference to FIGS. 6 and 7, the scanning synchronization signal (LS
YNC) Image data from the three CCDs 7a, 7b, 7c during the period
The signal is input from the analog processing unit to the synthesis / separation processing circuit in parallel.

The valid data area of the image data is determined by the input control signal (IN LGATE).

The input data 7b and 7c are input to the synthesizing / separating up circuit from the 0th to the 4999th in an effective data amount of 5000 pixels, and
At this time, the image data (output data 1) output from the synthesizing / separating up circuit is first output from the 2500th pixel of the input data 7b to the (4999−overlapping amount X ÷ 2) th pixel. 7c to the (X + 4835) th pixel from the (overlapping amount X ÷ 2) th pixel. By outputting in this manner, the input data 7b and 7c are corrected for the amount of overlap, are combined as one line data, and 7336 pixels, half of the effective data amount of 14672 pixels, can be output from the center of the original reading width. . The control timing of the output data 1 is E, X.

Similarly, input data 7a and 7b are similarly input to the synthesizing / separating down circuit from the 0th to the 4999th in an effective data amount of 5000 pixels, and image data (output data 2) output from the synthesizing / separating down circuit is input first. The data from the (164-overlap amount Y) -th pixel of the data 7a to the (4999-overlap amount Y ÷ 2) -th pixel is output, and then the (overlap amount Y ÷) of the input data 7b is output.
2) Output from the 2nd pixel to the 2499th pixel.

By outputting in this way, the input data 7a and 7b are corrected for the amount of overlap, are collected as one line data, and 7336 pixels, which is half of the effective data amount of 14672 pixels, can be output from the center of the document reading width. . The control timing of the output data 2 is E, X, W.

Here, the output data of the combining / separating up circuit 10b is in the main scanning direction, image data is output at 3/2 times the speed of the input data, and the output data of the combining / separating down circuit 10a is also in the main scanning direction. Image data is output at 3/2 times the speed of the input data.

Here, the image data of the center CCD 7b is valid up to 5000 pixels, and the image data of the left and right CCDs 7a and 7c is maximum.
4836 pixels. The overlap amount between CCD7b and CCD7c is X,
The overlap amount between the CCD 7b and the CCD 7a is defined as Y, and X, Y
Is within 164 pixels as described above.

8 and 9 show the synthesizing / separating up circuit 10 of FIG.
FIG. 3B is a block diagram showing a combination / separation down circuit 10a. These figures will be described with reference to FIG. In the figure, 20 is a depth switch, 21 and 77 are logics that output a half of the input using a sum (hereinafter referred to as 1/2 frequency dividers), 22 and 23 are inverters, and 24, 27 and 28 are sums, 25,26,29,3
2,35,36,41,42,59,60,61,72,78,80 are data selectors, 3
0, 31, 37, 38, 70 are address counters, 33, 34, 39, 40, 71 are comparators, 43, 44, 45, 46, 50, 74, 75 are flip-flops, 48, 49 are AND gates, 47 are Delay element, 55, 56, 57, 58
Is toggle RAM (random access memory), 51, 52, 5
3, 54, 76 and 79 are three-state buffers having a data latch function.

The operation of the circuit having the above configuration will be described below with reference to FIGS.
This will be described with reference to the time chart in the figure.

1. In case of combining / separating up circuit Input data 7b and 7c are latched by three-state buffers 53, 54 and 51, 52 having data and latch functions, respectively, and toggled.
Data is selectively output to the RAM 57 or 58 and the toggle RAM 55 or 56. The selection signal is controlled by the Q output and the output (toggle mode) of the flip-flop 44 (the seventh mode).
Control signals F, G in the figure). The three-state buffers 51, 52, 53, 54 having a latch function output data when the selection signal is L.

The write / read control of the toggle RAMs 55 to 58 is controlled by the CS and WE signals, and the CS controls the write timing by AND gates 48 and 49 (I and J in FIG. 7), and the read timing by CS and WE. (FIGS. 7F, G, I, J). The I and J signals of FIG. 7 which are CS control signals are obtained by shifting the CLK1 of the B signal by the delay element 47 and the toggle mode signals F and G of the flip-flop 44.
It is the one with AND.

The clock input to the flip-flop 44 is obtained by latching the above-mentioned LSYNC and C signals with CLK1. The flip-flop 44 outputs signals F and G based on the signal. The clock of the 3-state buffers 51 and 53 having the latch function is CLK1, the input data is latched by CLK1, the G signal of the flip-flop 44 is used as a control signal, and the data is transferred to the toggle RAMs 55 and 57 during the period of "L". The clocks of the three-state buffers 52 and 54 having a latch function are also CLK1, the input data is latched by CLK1, the F signal of the flip-flop 44 is used as a control signal, and the toggle RAM 56 , 58 to output the data.

Further, the address counters of the toggle RAMs 55 to 58 are connected to the address counters 30, 31, 37, and 38, respectively.
Toggle RAM means that while one RAM is in the write operation, the other RAM is in the read operation.Here, the currently input data is written in one, and the other RAM stores the data input in the previous stage. Reading.

The data selectors 59 and 60 select and output the read data of the toggle RAM. This selection signal is controlled by the F signal of the flip-flop 44.

The address counters 37, 38 of the toggle RAMs 57, 58 for reading and writing the data 7b are preset counters that can be preset, and include count up clock, count start,
It is controlled by an end control signal and an initial count signal. The clock of the counter is controlled by CLK1 and CLK2, and as described above, the clock CLK1 is 5,000 during the LSYNC period.
A clock capable of processing pixels, and a clock CLK2 is a clock capable of processing 7,500 pixels during the LSYNC period.

First, when the counter 37 controls the write address of the RAM 57, the R signal of the data selector 41 is input to the clock of the counter 37, which is the clock of the B signal. The initial count value of the preset at that time is 0, because the fixed value 3 is 0 in the data selectors 35 and 36, and the 0 output becomes the preset value of the counter by the selection signal F. The count start end signal is the O signal of the data selector 41 and the D signal (IN LGATE) of the flip-flop 45 described above.
Latch signal). Accordingly, the data of 5000 pixels of the input data 7b is written to the RAM 57 from addresses 0 to 4999.

RAM57 is writing, RAM58 is reading, and the counter is
When the RAM 38 controls the read address of the RAM 58, the clock of the counter 38 receives the V signal of the data selector 42, which is the clock of the A signal. At that time, the initial value of the preset becomes 2500, which is the fixed value 9 by the data selector 32.
The selection signal Z2 is switched between "L" and "H" by a jumper wire or a dip switch, and is output to the data selectors 36 and 35. Further, the selection signal G signal of the data selector 36 (inversion of the F signal) ) By 2500
This is because the output becomes the preset value of the counter. The count start / end signal is the S signal of the data selector 42,
This is a signal E obtained by latching the output control signal (OUT LGATE), which determines the output effective area of the data of 7,500 pixels during the LSYNC period, with the aforementioned A. At this time, the signal from the comparator 40 is output from the data selector 41 at the (4999−X / 2) count.
The flip-flop 50 outputs a signal X and ends counting. The operation of the RAMs 57 and 58 repeats the above operation.

Here, (4999−X / 2) is the overlap amount X transferred from the CPU and latched by the flip-flop 20, calculated by X / 2 by the 1/2 frequency divider 21.
In addition, −X / 2 is obtained by the inverter 22 and the sum is 27
That is, the sum of the fixed value 6 = 4999, that is, (4999−X / 2) is input to the comparison values of the comparators 40 and 39.

When the counter 37 is in the read operation, the signal from the comparator 39 becomes the signal of the output Q of the data selector 41, the flip-flop 50 outputs the signal X, and the counting ends.

In addition, the reason why the address starts from 2500 at the time of reading is that the data of the central CCD 7b is divided at the center.

The address counters 30, 31 of the RAMs 55, 56 for reading and writing the input data 7c are preset up counters, and are controlled by a count up clock, a control signal for starting and ending counting, and an initial count signal. The counting clock is controlled by CLK1 and CLK2.

First, when the counter 30 is in the write address control of the RAM 55, the R signal of the data selector 41 is inputted to the clock of the counter 30, and this becomes the B clock. The initial counter value of the preset at that time is from 0. This is because the fixed value 1 of the data selectors 25 and 26 is 0, and the 0 output becomes the preset value of the counter by the selection signal F. The other input values of the data selectors 25 and 26 are obtained by subtracting the overlap amount X input from the flip-flop 20 from 1 /
The frequency divider 21 is X / 2.

The count start / end signal is the P signal of the data selector 41, and becomes the D signal (IN LGATE latch signal) of the flip-flop 45 described above. Therefore, 5000 of data 7c is stored in RAM55.
Pixel data is written to addresses 0 to 4999.

RAM 55 is writing, RAM 56 is reading, and the counter is
When the RAM 31 is in the read address control of the RAM 56, the V signal of the data selector 42 is input to the clock of the counter 31, and the clock A of CLK2 is used. At this time, the initial value of the preset is the value selected by the data selector 26 (fixed value 1 is 0), and X / 2 is selected by the selection signal G (= F).
Is the preset value of the counter. The count start / end signal is the T signal of the data selector 42, and the count value is (X + 48) from the X signal of the flip-flop 50 described above.
35), the L signal of the comparator 34 is output to the flip-flop 50 via the data selector 42,
The processing is terminated by the X signal of the flip-flop 50. Here, (X + 4835) is the sum of 24 and the sum of the overlap amount X input from the flip-flop 20 and the fixed value 5 = 4835, that is, (X + 4835).
4835) and is output to the data selector 29. In the data selector 29, the fixed value 8 is set to 2499, and a switching means such as a jumper line or a dip switch is used.
Switching the selection signal Z1 (X + 4835) is the data selector 29
The data is output to the comparators 33 and 34.
The output X signal of the flip-flop 50 is connected to the selection signal input of the data selector 61 by a switching means such as a jumper line or a dip switch, and the output data is controlled by the data selector 61. RAM55,
The operation 56 repeats the above operation.

In FIG. 1, the data 1 output from the selector 59 is, as shown in the timing chart of FIG.
The (X / 2) to (4835 + X) th data are read. In addition, the selector 60 outputs (2500) to (49)
The 99th data is read.

In the interpolation circuit 62, the data 1, 2 and 1 described above, that is, CLK
2 and n of the E signal are input. The configuration of the embodiment of the interpolation circuit 62 is as shown in FIG. Hereinafter, the description will be continued with reference to FIG.

The counter 70 uses CLK1 of 1 as a count up clock, and further uses n, that is, the E signal as a count start control signal (counts when "H"). Here, the preset value of the counter 70 becomes a value output from the selector 72, which is determined by selectively switching between the fixed value 10 and the fixed value 11. The synthesis / separation up circuit is executed by switching the switching signal Z4 with a jumper line or the like so that the fixed value 10 is selected. Here, the fixed value 10 is set to 2500. Therefore, the counter 70 performs counting using 2500 as a preset value. The comparator 71 compares with the fixed value 12. The fixed value 12 is set to (4999−X / 2). Here, X is the amount of overlap input from the depth switch 20, and Y corresponds in the synthesis / separation down circuit. The signal output from the comparator 71 is latched by the flip-flop 74, and then the Y signal is output as a switching signal of the selector 78 using the preset clear function of the flip-flop 75. The Y signal is (49) of data 2.
It becomes “H” when the (99−X / 2) th data and the (X / 2) th data of the data 1 are read. Data 2 is latched in flip flop 76. The selectors 78 and 80 use the Y signal as a selection signal and flip-flops 76 and 7 when the Y signal is "L".
The data 2, 1 latched in 9 is selected, and when "H", the value output by the 1/2 frequency divider 77, that is, the (4999-X / 2) th data 2 is read out. A half of the sum of the read data and the (X / 2) -th read data of data 1 (indicated by α in FIG. 6) is output. Therefore, the last read data of the data 2 and the first read data of the data 1 are interpolated, the data is changed to the interpolated value, and sent to the next selector 61 in FIG. .

The selector 61 uses the X signal as a selection signal and corrects the amount of overlap between the data read by the CCDs 7c and 7b at the timing of the output data 1.

2. In the case of the combining / separating down circuit In the combining / separating down circuit, the overlap amount input from the dip switch 20 is Y. Also, input data 7b, 7a
As shown in the brackets shown in FIG. 1, input data 7b is supplied to three-state buffers 51 and 52 having a latch function.
a is output to three-state buffers 53 and 54 having a latch function.

In the case of data 7c, the RAM 57 is
58 is being read, and when the counter 38 controls the read address of the RAM 58, the clock of the counter 38 is set to the data selector 42.
Is input, and this is the clock of A. At this time, the initial value of the preset is (164-Y). The overlap amount Y input from the dip switch 20 is set to -Y by the inverter 23 and output to the sum 28. The fixed value 7 of the sum 28 is 164 (164-Y), but is output to the data selector 32 from the sum 28. In the synthesis / separation up circuit, the selection signal Z4 is switched by a jumper line or the like to 2500 outputs. In the synthesis / separation down circuit, the selection signal Z4 is jumpered so that the other input (164-Y) is output. Switching is performed by a line or the like (“L” and “H” switching). Thus, (164-Y) becomes the preset value of the counter.

The count start / end signal is the S signal of the data selector 42 and the E signal (OUT LGAT) of the flip-flop 46 described above.
E clock A latch signal). At this time (4999−Y
/ 2) At the count, the signal from the comparator 40 becomes the Q signal of the data selector 41, and the flip-flop 50 outputs the signal X.
Is output. The RAMs 57 and 58 repeat the above operation. Here, (4999−Y / 2) is the sum of the Y input from the flip-flop 20 and the sum 27 (fixed value 6) of the 1/2 frequency divider 21 and the inverter 22.
= 4999) is obtained from (4999-Y / 2). This is input to the comparison values of the comparators 40 and 39. When the counter 37 performs a read operation, the signal from the comparator 39 becomes the output Q signal of the data selector 41, and the flip-flop 50 outputs the signal X. In the case of the data 7b, similarly, when the RAM 55 is performing the write operation, the RAM 56 is performing the read operation, and the counter 31 controls the read address of the RAM 56,
The clock of the counter 31 is supplied with the V signal of the data selector 42, which becomes the clock of A. At this time, the initial value of the preset is Y / 2, which is obtained by converting Y input from the flip-flop 20 into Y / 2 by the 1/2 frequency divider 21 and inputting it to the data selector 26. This is because Y / 2 is selectively output and becomes the preset value of the counter. The count start / end signal is the T signal of the data selector 42, and when the count value reaches 2499, the comparator
The signal from 34 becomes the output U signal of the data selector 42,
The flip-flop 50 outputs the signal X and terminates counting. The RAMs 55 and 56 repeat the above operation.

In the synthesizing / separating down circuit, as the data 1 output from the selector 59, (Y / 2) to (2499) th data are read. In addition, the selector 60 sends the data 2 (164
-Y) to (4999) th data are read.

The control and data flow in the interpolation circuit 62 are based on
It is almost the same as the separation up circuit. In the combining / separating down circuit, the preset value of the counter 70 becomes a fixed value 11 by switching the switching signal Z4 of the selector 72 to a jumper line or the like. The fixed value 11 is (164-Y). The comparator 71 makes a comparison with the fixed value 12 (4999−Y / 2), and the flip-flops 74 and 75 output the Y signal as a selection signal of the selector 78.

Accordingly, the (4999−Y / 2) th read data of data 2 is interpolated with the (Y / 2) th read data of data 1 (indicated by β in FIG. 6), and the interpolated value is obtained. The data is changed and sent to the selector 61 in FIG. The selector 61 outputs the output data 2 using the W signal as a selection signal, and corrects the overlap amount of the data read by the CCD 7b and the CCD 7a.

As described above, according to the present embodiment, it is possible to reduce a sense of discomfort at the switching position of read image information due to a difference in sensitivity between the photoelectric conversion elements.

Next, another embodiment of the present invention will be described. This embodiment is the same as the embodiment except that the interpolation circuit 62 shown in FIG. 1 is removed. Therefore, illustration and description are omitted, and a circuit corresponding to the circuit shown in FIG. 9 will be described.

FIG. 10 is a circuit diagram showing a smoothing circuit, where 81 and 87 are selectors, 82 is a counter, 83 is a comparator, 84 and 86 are shift registers, 85 is a flip-flop, and 88 is a fixed value of a coefficient in a matrix. And a processor that performs digital filter operation (hereinafter referred to as a digital filter).

FIG. 11 is an explanatory view showing a digital filter matrix used in the present invention, wherein the filter system is set to 1/5.

FIG. 12 is an explanatory view for explaining a difference in output density occurring at a switching position of read data when the present reading apparatus reads a half tone of a certain density, and FIG. 13 is a view showing the vicinity of the switching position utilizing the present invention. A median filter is provided for each pixel.
It is explanatory drawing which shows the result changed step by step.

FIG. 14 is a time chart for explaining the operation of the smoothing circuit.

Next, with respect to the smoothing circuit of FIG. 10, the description of the timing chart of FIG. 14 will be continued with reference to FIGS. 11, 12, and 13.

First, a description will be given of the case of the synthesis separation up circuit. Data 1 is a value output from the selector 61 in FIG.
1 is CLK2 of the A signal, and m is the E signal. Selector 81
Switches the selection signal Z4 using a jumper line or the like so as to select the fixed value 10. Here, the fixed value 10 is set to 2500. The counter 82 uses CLK2 as a count clock and the E signal as a count valid control signal, and starts counting from a preset value 2500. Next, the comparator
83 generates a signal when the fixed value 12 matches the counter output value, and outputs the signal to the shift register 84 in the next stage. The shift register 84 outputs the one-time latch and the nine-time latch to the clear set terminal of the flip-flop 85, and the flip-flop 85 generates a Y signal. Where the fixed value 12 is
(4996-X / 2).

Next, the data 1 is supplied to the shift register 86 and the digital filter 88. Here, the digital filter 88
A 1 × 5 matrix operation is always performed, and the result is output to the selector 87. The operation coefficient in the 1 × 5 matrix is
The third pixel from the left, that is, the pixel corresponding to the center coefficient is set as the target pixel, and all the operation coefficients are set to 1/25, and median processing is performed.

Here, the calculation coefficient is set to 1/25 with a fixed value of 13. At the same time, the shift register 85 performs latching until the digital filter 88 outputs a calculation output, and matches the phase of each output data.

That is, the same value as the data 1 is output from the shift register 86, and the 1 × 5 median value is output from the digital filter 88 to the selector 87 at the same timing. Here, the matrix set in the digital filter 88 is FIG. 11 described above.

The selector 87 uses the Y signal as a selection signal,
Select the output value of 86 and digital filter 88. Thank you
As shown in FIG. 14 which is a time chart, the selector
From 87, the output data (UP) is output. Here, α ₁ to ₈ have been changed to the median value, and CCD7b and C
Switching position of the read data with CD7c becomes a between alpha ₄ and alpha _5, corrects the density change of the read data such as Fig. 12 in a step change, such as FIG. 13. Therefore, the CC in FIG.
By making the steep density at the read data switching position of D a buffer of a stepwise density change area between eight pixels, various defects and unnaturalness appearing in the final output image are alleviated.

Next, the combining / separating down circuit will be described. Since the synthesis / separation down circuit is almost the same as the up circuit,
The explanation will be focused on different places. The selector 81 connects the selection signal Z4 with a jumper line or the like so as to select the fixed value 11. Here, the fixed value 11 is set to (164−Y), and Y is the overlap amount of the combining / separating down circuit as described above. Comparator as well as up circuit
Fixed value 12 (4996−Y / 2) input to 83 and counter 8
The Y 'signal is generated by the shift register 84 and the flip-flop 85 and is used as a selection signal of the selector 87. Thus, the output data (down) shown in FIG. 14 is obtained in the same manner as in the synthesis / separation up circuit. Here, β ₁ to ₈ have been changed to median values by the digital filter 88. Digital filter even in down circuit
The matrix of 88 is set as shown in FIG. No.
Although FIGS. 12 and 13 show only the combining / separating up circuit, the same applies to the combining / separating down circuit, and the description is omitted.

In the above description, the case where a processor for performing digital filter operation is used has been described. However, an equivalent result can be obtained by a combination of general-purpose logic ICs. Further, it is easy to apply the smoothing process to shift wear.

〔The invention's effect〕

As described above, according to the first and second aspects of the present invention, since the image reading apparatus is configured as described above, an image reading apparatus that reads one-line data using three or more photoelectric conversion elements is provided. It is possible to improve both the processing speed and the image quality. More specifically, the processing time is reduced to one-half that of collecting the output data of the photoelectric conversion elements in one line, and the switching position of the read image information in the final output image is reduced with a simple and inexpensive configuration. Discomfort such as white streaks, black streaks, and density changes can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an image reading apparatus according to the present invention, FIG. 2 is a schematic configuration diagram illustrating an image reading apparatus using the present invention, and FIGS. 3 and 4 are three CCDs. Schematic diagram for explaining the relationship when using the, respectively.
A block diagram showing a processing circuit for the original image output from D,
6 and 7 are time charts, FIGS. 8 and 9 are block diagrams showing the combining / separating up circuit and the combining / separating down circuit of FIG. 5, and FIG. 10 is a smoothing circuit of another embodiment. FIG. 11 is a circuit diagram showing a circuit, FIG. 11 is an explanatory diagram illustrating a digital filter matrix used in another embodiment,
FIG. 12 is an explanatory diagram for explaining a difference in output density occurring at a switching position of read data, FIG. 13 is an explanatory diagram showing a result of stepwise change by a median filter, and FIG. 14 is an operation of a smoothing circuit. It is a time chart to explain. 7, 7a, 7b, 7c: photoelectric conversion element (CCD), 8a, 8b, 8c: amplifier, 9a, 9b, 9c: analog / digital conversion circuit, 10a, 10b
... Synthesis / separation circuit, 20 ... Depth switch, 62 ... Interpolation circuit, 88 ... Digital filter.

Claims (2)

(57) [Claims] An image reading apparatus for reading original image information by using three or more photoelectric conversion elements to overlap the areas read by adjacent photoelectric conversion elements is divided into two parts from the median of the maximum original width. And synthesizing / separating means for synthesizing and separating the document image information output from each of the photoelectric conversion elements during the scan synchronization period, and the synthesizing / separating means stores the image information output from each of the photoelectric conversion elements. A read / write control unit that controls reading and writing of the storage unit; a switching unit that switches read image information of adjacent photoelectric conversion elements read from the storage unit in an overlapping area; Interpolating means for interpolating adjacent pixels at the switching position of the read image information of the combined photoelectric conversion element. Place. 2. An image reading apparatus for reading original image information by using three or more photoelectric conversion elements to overlap an area to be read by an adjacent photoelectric conversion element. And synthesizing / separating means for synthesizing and separating the document image information output from each of the photoelectric conversion elements during the scan synchronization period, and the synthesizing / separating means stores the image information output from each of the photoelectric conversion elements. A read / write control unit that controls reading and writing of the storage unit; a switching unit that switches read image information of adjacent photoelectric conversion elements read from the storage unit in an overlapping area; And a smoothing means for smoothing adjacent pixels at a switching position of the read image information of the combined photoelectric conversion element. Device.