JP2654389B2 - Image reading device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image reading apparatus using a plurality of photoelectric conversion elements.

This type of image reading apparatus is used as a digital copying machine, fax machine, filing, and CAD input device.

(Prior art)

Conventionally, in this type of image reading device, when a plurality of photoelectric conversion elements are combined as one line data, the position where the overlap of the image information between the photoelectric conversion elements is connected is one of the photoelectric conversion elements where the connection position is fixed and the other is fixed. The position of the photoelectric conversion element is changed by adjusting means such as a depth switch according to the amount of overlap, and is set as one-line data.

However, when an image on the original surface is formed on the photoelectric conversion element using a lens, the resolution of the end of the lens is reduced, and the amount of incident light is also reduced. Therefore, the position where the amount of overlap between the photoelectric conversion elements is connected, and if one is fixed, the other may be a position where the resolution is reduced or the amount of incident light is reduced depending on the amount of overlap.

Another problem is that the balance between the resolving power and the amount of incident light of the left and right photoelectric conversion elements is different, which causes a sense of discomfort at a joint portion as an image.

〔Purpose〕

The present invention has been made in view of such a point, and an object of the present invention is to eliminate a sense of discomfort in a portion where adjacent photoelectric conversion elements overlap.

〔Constitution〕

For this purpose, the first means is an image reading apparatus for reading a one-line original image by overlapping a part of adjacent photoelectric conversion elements of a plurality of photoelectric conversion elements. Input means for inputting a desired amount of overlap with respect to the overlapped portion, and distributing the amount of overlap to adjacent photoelectric conversion elements, and valid image data of the adjacent photoelectric conversion elements in accordance with each of the distributed amounts of overlap. And control means for controlling the end position of the image data and the start position of the effective image data.

The second means is the first means, further comprising a storage means for storing image data read by the plurality of photoelectric conversion elements, wherein the control means reads effective image data when reading the image data from the storage means. The end position and the start position of the effective image data are controlled.

The third means is the first or second means,
The input means is an operation panel.

The fourth means is the first to third means,
When the input means has a plurality of overlapping portions of adjacent photoelectric conversion elements of the plurality of photoelectric conversion elements, a plurality of types of desired overlapping amounts can be input.

Fifth means is the first to fourth means,
The control means controls so as to warn when the overlap amount inputted from the input means is out of a predetermined range.

The sixth means is the first to fifth means,
The control means may evenly distribute the overlap amount input from the input means.

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a schematic diagram illustrating an embodiment of an image reading apparatus using the present invention. In the figure, reference numerals 1 to 4 denote conveying rollers, 5 an illumination device, 6 an optical lens, and 7 a CCD (charge coupled device) constituting an image sensor. In this configuration, a document is fed in the direction of the arrow in the figure and is transported by transport rollers 1-4. During this conveyance, the original image illuminated by the illumination device 5 is formed on the CCD 7 by the optical lens 6.

In this case, since the number of effective reading pixels per CCD7 is determined, the width of the original that can be read is determined if the original reading density is determined, but if the original is wider than the original width that can be read by the CCD, Multiple CCDs must be used.

In the above-described embodiment, it is assumed that the number of effective read pixels per CCD 7 is 5000 pixels, the maximum original width of the original to be read is 917 mm, and the original read density is 16 pixels / mm. Here, the number of CCD7 used is the maximum document width of 917m above
From m, the original reading density of 16 pixels / mm, the maximum number of effective reading pixels is 14,672, and the number of effective reading pixels per CCD7 is 5,000, as described above.

FIG. 2 and FIG. 4 are schematic diagrams for explaining the relationship when the above-mentioned three CCDs 7 are used. D is the maximum original width, 6a ~
6c denotes an optical lens, 7a to 7c denote CCDs, and OR, X, Y denote the overlapping of the CCD reading areas. In FIG. 2, three image sensors (CCDs) 7a to 7c are used to read the maximum original width D. Each CCD is formed by an optical lens 6a to 6c, and each CCD is formed.
Are overlapped as indicated by OR. The overlapping area amount is set to (15000−14672) 6722 = 164 pixels or less, and is adjusted so as to satisfy the maximum reading original width D.

Original images formed on the CCDs 7a to 7c are output from these CCDs 7a to 7c as analog signals, but since these signals are extremely small, these outputs must be amplified.

FIG. 3 is a block diagram schematically showing a circuit for processing a document image output from a CCD. In the figure, 7a to 7c are CCDs, 8a to 8
c is an amplifier, 9a to 9d are analog / digital conversion (A / D) circuits, and 10a and 10b are synthesis / separation circuits. In FIG. 3, C
Outputs of the CDs 7a to 7c are amplified by amplifiers 8a to 8c. Amplifier 8a
8c are converted from analog image signals into multi-valued (for example, 64 gradation) digital image signals for each pixel in A / D conversion circuits 9a to 9c. The digital image signal after A / D conversion is noise of the original image, unevenness of light intensity, dirt on the contact glass, CCD
Noise appears in the regular image data due to sensitivity unevenness of the image.
Therefore, as a countermeasure against this noise, shading correction is conventionally performed in an A / D conversion circuit. In this way, the output from each CCD is amplified, subjected to shading correction, A / D converted, and combined as multi-valued data.
The signals are input to the separation circuits 10a and 10b.

In the above case, each CCD is scanned simultaneously and outputs pixel data at the same time. At this timing, as shown in the time chart of FIG. 6 (b), the CCDs 7a to 7c are synchronized in the main scanning direction by the scanning synchronization signal C (LSYNC), and the valid data from the CCDs 7a to 7c is input control signal D ( INL
GATE).

In the sub-scanning direction (insertion speed) of the document, it is assumed that LSYNC outputs a control signal 16 times per 1 mm of sub-scanning. Therefore, the sub-scanning density is also 16 pixels / mm, and the main scanning density is 1 pixel.
It is equal to 6 pixels / mm. The scan synchronization signal is output at regular intervals in order to make the charge accumulation time of the CCD constant.

At present, the image data from the three CCDs 7a to 7c are analog-processed in parallel between the scan synchronization signals. However, as described above, the correction of the amount of overlap between the CCD images, the digital processing unit after the analog processing [ For example, scaling processing, MTF (modulation transfer function) processing, smoothing processing, etc.) also require three CCs due to the need to process data during the period of the scan synchronization signal.
The output data from D is made into one line, and the amount of overlap is corrected. However, if the output data of the three CCDs 7a to 7c is combined into one line during the period of the scan synchronization signal, the processing speed of image data per pixel is tripled.

In the present invention, the CCD1
When processing 5,000 pixels per pixel, the processing time per pixel is 62.5 ns / 1 pixel, but when 3 CCD data are combined into one line during 312.5 μs, it becomes 20.8 ns / 1 pixel, processing Time is three times faster. However, the present invention
Instead of collecting output data of three CCDs on one line, the median value of the maximum original width D (here, 2 of CCD7b in FIG. 2)
(The 449th pixel is defined as the center pixel), and data of 7,500 pixels is processed during the scanning synchronization signal period.

For this reason, the processing time is reduced to half compared to the case where the output data of the CCD is collected on one line.

FIG. 4 shows the amount of overlap between CCDs. X is CCD7b, 7
c is the overlap amount, and Y is the overlap amount of the CCDs 7a and 7b.

Normally, when the amount of overlap between CCDs is corrected to one line data, one of the two CCD image data is fixed, and the other image data is fixed according to the amount of overlap. Determines valid data.

Also, half of the overlap amount X, Y between the CCDs, that is, X / 2, Y / 2
The effective data between the CCDs is determined according to the overlapping amount of.

By not fixing one of the overlapping positions, for example, the resolution of the ends of the lenses 6a, 6b, 6c is reduced, and the image data in which the amount of incident light is reduced is not made effective. Can be eliminated.

FIG. 5 (c) is a block diagram schematically showing a circuit utilizing the contents of the present invention. CPU101 is central processing unit, RO
The M102 stores a program for the CPU 101 to perform a predetermined operation, and data of guidance for warning when the overlap amounts X and Y are erroneously input. The RAM 103 is provided with a memory for the CPU 101 to store temporary data, the I / O 104 and the I / O 107 are provided with input / output elements, and the key input unit 105 is provided with keys necessary for inputting an overlap amount. Combining / separating circuit 106 is CPU 101
Is a correction circuit for connecting read image information to one line based on the overlap amounts X and Y transferred by the. Details will be described later.

Hereinafter, FIG. 5C and a flowchart showing an outline of the operation of the CPU 101 will be described with reference to FIG.

First, when there is an overlap amount change request key input from the key input unit 105, an input of the overlap amount X is awaited.

When the input of the overlap amount X is completed, the CPU 101 executes the above (15000).
It is determined whether or not the overlap amount X is input within the input restriction condition of ÷ 2 = 164 pixels or less and 0 or more. If the restriction condition is not satisfied, the CPU 101 stores the warning guidance data stored in the ROM 102. Is transferred via I / O 107 and the warning display
A predetermined warning guidance is displayed on 108. Here, the warning display section is composed of, for example, a liquid phase display, and the warning guidance data is character information data for informing the liquid crystal display of warning information. Then, the process waits for the input of the overlap amount X again, and is repeated until an appropriate value is input.

Next, in the same manner, input of the overlap amount Y is waited. If the value is an appropriate value, the changed overlap amounts X and Y are written in the RAM 103, and an overlap amount change request or a read start key input wait is performed.
When a reading start key is input, the overlapping amounts X and Y of the RAM 103 are read, and the control signal Z is passed through the combining / separating circuit 106 and the I / O 104.
Transferred with 1, Z2 and start reading.

FIG. 7 is a flowchart illustrating the overlap amount X and the overlap amount Y input from the key input unit 102. The CPU 100 calculates and corrects the overlap amount X and the overlap amount Y. The command is converted into an overlap amount X command and an overlap amount Y command. It is a block diagram which outputs to a synthesis | combination / separation circuit of (b) in parallel.

 The overlap amounts X and Y need to be arithmetically corrected to hexadecimal numbers.

The block diagram of FIG. 7 will be described with reference to the flowchart of FIG.

100 is a CPU (Central Processing Unit), 101 is an IO element for controlling data input / output, 102 is a key input unit, and 104 is equivalent to the combining / separating circuit in FIGS. 5 (a) and 5 (b).

Reference numeral 103 denotes a control signal for determining the command of the overlap amount X on the combining / separating circuit, and is output to Z in FIG. 5A. Reference numeral 105 denotes a similar control signal for determining the command of the overlap amount Y on the combining / separating circuit. Here, there are two circuits (synthesis / separation circuits) shown in FIGS. 5 (a) and 5 (b).

 Details will be described later.

When there is a request for input of the overlap amount from the key input unit 102, for example, the numeric keypad of the operation unit, the CPU 100 waits for the input of the overlap amount X, and then X is input and X is determined. next
The CPU 100 is in a state of waiting for the input of the overlap amount Y, and then Y is input and Y is determined. Next, the CPU 100 performs a hexadecimal correction operation in order to correct the overlap amount X into command data of the overlap amount X. Thereafter, similarly, a hexadecimal correction operation is performed on the overlap amount Y to obtain command data of the overlap amount Y. After that, the commands of the overlap amounts X and Y are output in parallel to the circuits corresponding to FIGS. 5A and 5B via the I / O 101.

FIG. 6C is a timing chart showing the timing at which the CPU transfers data to the synthesis / separation circuit. In FIG. 6A, IN LGATE is a control signal for determining data in the main scanning direction output from each photoelectric conversion element, while FGATE in FIG. 6C is a data line in the sub scanning direction. Is a control signal for determining Data is valid when FGATE is “H”. Therefore, the commands of the overlap amounts X and Y and their control signals (Z1, Z2) must be output and determined before the FGATE rises. Another FG
When the ATE is “H”, the change of the command of the overlap amount X, Y is prohibited by software. As described above, the signal of the overlap amount X determines the command of the overlap amount X at the rising edge, and similarly determines the command of the overlap amount Y.

As described above, the overlap amounts X and Y are output to the separation / combination circuit with an easy and simple configuration.

As described above with reference to FIGS. 6 (a) and 6 (b), the image data from the three CCDs 7a, 7b, 7c are combined and separated from the analog processing unit during the scanning synchronization signal (LSYNC) period. The data is input to the processing circuit in parallel.

The valid data area of the image data is determined by the input control signal (IN LGATE).

The input data 7b and 7c are input to the synthesizing / separating up circuit from the 0th to the 4999th in an effective data amount of 5000 pixels, and
At this time, the image data (output data 1) output from the synthesizing / separating up circuit is first output from the 2500th pixel of the input data 7b to the (4999−overlapping amount X ÷ 2) th pixel. 7c to the (X + 4835) th pixel from the (overlapping amount X ÷ 2) th pixel. By outputting in this manner, the input data 7b and 7c are corrected for the amount of overlap, are combined as one line data, and 7336 pixels, half of the effective data amount of 14672 pixels, can be output from the center of the original reading width. . The control timing of the output data 1 is E, X.

Similarly, input data 7b and 7c are similarly input to the combining / separating down circuit from the 0th to the 4999th in an effective data amount of 5000 pixels, and image data (output data 2) output from the combining / separating down circuit is first input. The data from the (164-overlap amount Y) -th pixel of the data 7a to the (4999-overlap amount Y ÷ 2) -th pixel is output, and then the (overlap amount Y ÷) of the input data 7b is output.
2) Output from the 2nd pixel to the 2499th pixel.

By outputting in this way, the input data 7a and 7b are corrected for the amount of overlap, are collected as one line data, and 7336 pixels, which is half of the effective data amount of 14672 pixels, can be output from the center of the document reading width. . The control timing of the output data 2 is E, X, W.

Here, the output data of the combining / separating up circuit 10b is in the main scanning direction, image data is output at 3/2 times the speed of the input data, and the output data of the combining / separating down circuit 10a is also in the main scanning direction. Image data is output at 3/2 times the speed of the input data.

Here, the image data of the center CCD 7b is valid up to 5000 pixels, and the image data of the left and right CCDs 7a and 7c is maximum.
4836 pixels. The overlap amount between CCD7b and CCD7c is X,
The overlap amount between the CCD 7b and the CCD 7a is defined as Y, and X, Y
Is within 164 pixels as described above.

FIGS. 5A and 5B are block diagrams showing the combining / separating up circuit 10b and the combining / separating down circuit 10a of FIG. In the figure, reference numeral 20 denotes a dip switch or flip-flop, 21 denotes a logic which outputs a half of the input using a sum (hereinafter referred to as a 1/2 frequency divider), 22 and 23 denote inverters 24, 27 and 28, and 25 denotes a sum. , 26,29,32,35,36,41,42,59,60,61
Is a data selector, 30, 31, 37, and 38 are address counters, 3
3, 34, 39, 40 are comparators, 43, 44, 45, 46, 50 are flip-flops, 48, 49 are AND gates, 47 is delay elements, 55, 5
6,57,58 are toggle RAM (random access memory),
Reference numerals 51, 52, 53 and 54 denote three-state buffers having a data latch function.

The operation of the circuit having the above configuration will be described below with reference to the time charts of FIGS. 6 (a) and 6 (b).

1. In case of combining / separating up circuit Input data 7b and 7c are latched by three-state buffers 53, 54 and 51, 52 having data and latch functions, respectively, and toggled.
Data is selectively output to the RAM 57 or 58 and the torque RAM 55 or 56. The selection signal is controlled by the Q output and the output (toggle mode) of the flip-flop 44 (the sixth mode).
(A) Control signals F and G). The three-state buffers 51, 52, 53, 54 having a latch function output data when the selection signal is L.

The write / read control of the toggle RAMs 55 to 58 is controlled by the CS and WE signals. CS controls the write timing by AND gates 48 and 49 (Fig. 6 (b) I and J), and the read timing by CS and WE. (Fig. 6 (a) F, G, I, J). The I and J signals of FIG. 6A, which are CS control signals, are obtained by shifting B1 of CLK1 by the delay element 47 and ANDing the flip-flop 44's toggle mode signals F and G.

The clock of the flip-flop 44 is obtained by latching the above-mentioned LSYNC and C with CLK1B. And flip flop 44 divides the clock by 1/2,
Toggle mode signals F and G are output. The clock of the 3-state buffers 51 and 53 having the latch function is CLK1B,
The input data is latched by CLK1, the G signal of the flip-flop 44 is used as a control signal, data is output to the toggle RAMs 55 and 57 during the period L, and the clocks of the 3-state buffers 52 and 54 having a latch function are CLK1 And the input data is CLK
Latched at 1, the F signal of the flip-flop 44 is used as a control signal, and data is output to the toggle RAMs 56 and 58 during the L period.

Further, the address counters of the toggle RAMs 55 to 58 are connected to the address counters 30, 31, 37, and 38, respectively.
Toggle RAM means that while one RAM is in the write operation, the other RAM is in the read operation.Here, the currently input data is written in one, and the other RAM stores the data input in the previous stage. Reading.

The data selectors 59 and 60 select and output the read data of the toggle RAM. This selection signal is controlled by the F signal of the flip-flop 44.

The address counters 37, 38 of the toggle RAMs 57, 58 for reading and writing the data 7b are preset counters that can be preset, and include count up clock, count start,
It is controlled by an end control signal and an initial count signal. The clock of the counter is controlled by CLK1B and CLK2A. As described above, the clock of B is 500 times during the LSYNC period.
The clock that can process 0 pixels, and the clock of A is a clock that can process 7,500 pixels during the LSYNC period.

First, when the counter 37 controls the write address of the RAM 57, the R signal of the data selector 41 is input to the clock of the counter 37, which becomes the B clock. The initial count value of the preset at that time is 0, because the fixed value 3 is 0 in the data selectors 35 and 36, and the 0 output becomes the preset value of the counter by the selection signal F. The count start / end signal is the O signal of the data selector 41 and becomes the D signal (IN LGATE latch signal) of the flip-flop 45 described above.

Therefore, the data of 5000 pixels of the input data 7b is written to the RAM 57 from addresses 0 to 4999.

RAM57 is writing, RAM58 is reading, and the counter is
When the RAM 38 controls the read address of the RAM 58, the V signal of the data selector 42 is inputted to the clock of the counter 38, which becomes the A clock. Then, the initial value of the preset
2500, which is the data selector 32 and the fixed value 9 is 2500
The selection signal Z4 is switched between L and H by a jumper line or a dip switch, and is output to the data selectors 36 and 35. Further, 2500 outputs are generated by the selection signal G signal of the data selector 36 (inversion of the F signal). This is because it becomes the preset value of the counter. The count start / end signal is the S signal of the data selector 42, which is
During the period, an output effective area for data of 7,500 pixels is determined.
This is a signal E obtained by latching the output control signal (OUT LGATE) with the aforementioned A. At this time, the signal from the comparator 40 becomes the Q signal of the data selector 41 at the (4999-X / 2) th count, and the flip-flop 50 outputs the signal X and ends the counting.

 The operation of the RAMs 57 and 58 repeats the above operation.

Here, (4999−X / 2) is the overlap amount X transferred from the CPU and latched by the flip-flop 20, calculated by X / 2 by the 1/2 frequency divider 21.
In addition, −X / 2 is obtained by the inverter 22 and the sum is 27
That is, the sum of the fixed value 6 = 4999, that is, (4999−X / 2) is input to the comparison values of the comparators 40 and 39.

When the counter 37 is in the read operation, the signal from the comparator 39 becomes the signal of the output Q of the data selector 41, the flip-flop 50 outputs the signal X, and the counting ends.

First, the reason why the address is started from 2500 at the time of reading is that the data of the central CCD 7b is divided at the center.

The address counters 30 and 31 of the RAMs 55 and 56 for reading and writing the input data 7c are upset counters that can be set in the buzzer, and are controlled by a count up clock, a control signal for starting and ending counting, and an initial count signal. The counting clock is controlled by CLK1B and A of CLK2.

First, when the counter 30 is in the write address control of the RAM 55, the R signal of the data selector 41 is inputted to the clock of the counter 30, and this becomes the B clock. The initial counter value of the preset at that time is from 0. This is because the fixed value 1 of the data selectors 25 and 26 is 0, and the 0 output becomes the preset value of the counter by the selection signal F. The other input values of the data selectors 25 and 26 are obtained by subtracting the overlap amount X input from the flip-flop 20 from 1 /
The frequency divider 21 is X / 2.

The count start / end signal is the P signal of the data selector 41, and the D signal (IN LGATE) of the flip-flop 45 described above.
Latch signal). Therefore, the RAM 55 has 500 data of 7c.
Data of 0 pixel is written from address 0 to 4999.

RAM 55 is writing, RAM 56 is reading, and the counter is
When the RAM 31 is in the read address control of the RAM 56, the V signal of the data selector 42 is input to the clock of the counter 31, and the clock A of CLK2 is used. At this time, the initial value of the preset is the value selected by the data selector 26 (fixed value 1 is 0), and X / 2 is selected by the selection signal G (= F).
Is the preset value of the counter. The count start / end signal is the T signal of the data selector 42, and the count value is (X + 48) from the X signal of the flip-flop 50 described above.
35), the L signal of the comparator 34 is output to the flip-flop 50 via the data selector 42,
The processing is terminated by the X signal of the flip-flop 50. Here, (X + 4835) is the sum of 24 and the sum of the overlap amount X input from the flip-flop 20 and the fixed value 5 = 4835, that is, (X + 4835).
4835) and is output to the data selector 29. In the data selector 29, the fixed value 8 is set to 2499, and a switching means such as a jumper line or a dip switch is used.
Switching the selection signal Z3 (X + 4835) is the data selector 29
The data is output to the comparators 33 and 34.
The output X signal of the flip-flop 50 is connected to the selection signal input of the data selector 61 by switching means such as a jumper line or a dip switch. That is, the output data is controlled by the data selector 61. RAM55,
The operation 56 repeats the above operation.

2. In the case of the combining / separating down circuit In the combining / separating down circuit, the overlap amount input from the flip-flop 20 is Y. Also, input data 7b, 7a
The input data 7b is output to three-state buffers 51 and 52 having a latch function, and the input data 7a is output to three-state buffers 53 and 54 having a latch function as shown in the brackets shown in FIG. 5 (b). You.

In the case of data 7c, the RAM 57 is
58 is being read, and when the counter 38 controls the read address of the RAM 58, the clock of the counter 38 is set to the data selector 42.
Is input, and this is the clock of A. At this time, the initial value of the preset is (164-Y). The overlap amount Y input from the flip-flop 20 is set to -Y by the inverter 23 and output to the sum 28. The fixed value 7 of the sum 28 is 164 (164-Y), but is output to the data selector 32 from the sum 28. In the synthesis / separation up circuit, the selection signal Z4 is switched by a jumper line or the like to 2500 outputs. In the synthesis / separation down circuit, the selection signal Z4 is jumpered so that the other input (164-Y) is output. Switch by line etc. (L, H switching).
Thus, (164-Y) becomes the preset value of the counter.

The count start / end signal is the S signal of the data selector 42, and the E signal (OUT LGA) of the flip-flop 46 described above.
TE clock A latch signal). At this time (4999−
At the (Y / 2) th count, the signal from the comparator 40 becomes the Q signal of the data selector 41, and the flip-flop 50 outputs the signal X. The operation of the RAMs 57 and 58 repeats the above operation. Here, (4999−Y / 2) is obtained by adding Y input from the flip-flop 20 to a 1/2 frequency divider 21 and an inverter 22 to obtain a sum 27.
(4999−Y / 2) is obtained from (fixed value 6 = 4999). This is input to the comparison values of the comparators 40 and 39. When the counter 37 is in the read operation, the comparator 37
It becomes the output Q signal of the data selector 41 of the signal from 39,
The flip-flop 50 outputs a signal X.

In the case of the data 7b, similarly, when the RAM 55 is performing the write operation, the RAM 56 is performing the read operation, and when the counter 31 controls the read address of the RAM 56, the V signal of the data selector 42 is input to the clock of the counter 31. Clock. At this time, the initial value of the preset is Y / 2, which is obtained by dividing Y input from the flip-flop 20 by a 1/2 frequency divider 21.
This is because Y / 2 is input to the data selector 26, Y / 2 is selected and output by the selection signal G, and becomes the preset value of the counter. The count start / end signal is the T signal of the data selector 42, and the count value is 2499.
, The signal from the comparator 34 becomes the output U signal of the data selector 42, the flip-flop 50 outputs the signal X, and the counting ends. The operations of the RAMs 55 and 56 repeat the above operations.

The output data is connected by a jumper line or the like so that the W signal of the flip-flop 50 becomes a selection signal of the data selector 61. The output data is output at the timing of the output data 2.

As described above, according to the present invention, the read data of the synthesis / separation up circuit starts from 2500 pixels (4999−X / X) in the input data 7b.
2) Up to the pixel, from X / 2 pixel (4835−
X) pixels. The read data of the synthesis / separation down circuit is from Y / 2 pixels to 2499 pixels for the input data 7b.
The input data 7a ranges from (164-Y) pixels to (4999-Y / 2) pixels.

Therefore, since the reading start position of each of the data 7a, 7b, and 7c is set to be a half of the overlap amount X, Y, a lens for forming an image of the original on the photoelectric conversion element (for example, FIGS.
By not using the image data having the reduced resolution at the end portion 6c) and the image data having the reduced incident light amount as the effective data, the sense of discomfort as an image of the joint between the CCDs is also eliminated.

Further, since (164-Y) is set on the hardware, if the overlap amount is equal to or more than 164 and equal to or less than 0, an error occurs in the read data of the combining / separating circuit. Therefore, by using the present invention, it is possible to easily and reliably input a proper overlapping amount with a simple circuit configuration.

〔effect〕

ADVANTAGE OF THE INVENTION According to this invention, the uncomfortable feeling in the superimposed part of the adjacent photoelectric conversion element can be eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic structural view for explaining an embodiment of an image reading apparatus using the present invention, FIG. 2 is a view showing a reading width of three CCDs, and FIG. 3 is a block diagram showing a processing circuit for an original image. Figure,
FIG. 4 is a diagram showing the same reading width as FIG. 2, FIGS. 5 (a) and 5 (b) are block diagrams showing a synthesizing / separating up / down circuit, and FIG. 6 (a) and 6 (b) are block diagrams of a circuit for prompting the synthesis / separation circuit of FIGS. 6 (a) and 6 (b) to input an appropriate value for outputting a command of the overlap amount X and Y. The time chart of each part, FIG. 7 (c) is a timing chart for the CPU to transfer the commands of the overlap amounts X and Y, and FIG. 7 is the input of the overlap amount and the operation is corrected, and FIG. 5 (a) and FIG. FIG. 8 is a block diagram showing a specific example of a circuit for outputting a command of the overlap amount X, Y to the synthesizing / separating circuit. FIG. 8 shows a case where a command of the overlap amount X, Y is input from a key of the operation unit, and FIG. ), (B) is a flow chart showing the output to the synthesis / separation circuit. FIG. 9 shows the overlap amounts X and Y input from the keys of the operation unit. 5 (a) and 5 (b) are output to the synthesizing / separating circuit, and the input is judged whether the input is appropriate, the appropriateness is promoted, and the flow chart schematically showing the process until the image is actually read. It is. 7a, 7b, 7c: photoelectric conversion element, OR: overlapping amount, 10: combining / separating up / down circuit, 108: warning display section.

Claims (6)

(57) [Claims] 1. An image reading apparatus for reading a one-line original image by superposing a part of adjacent photoelectric conversion elements of a plurality of photoelectric conversion elements, wherein: Input means for inputting a desired overlap amount; distributing the overlap amount to adjacent photoelectric conversion elements; and ending effective image data and an effective image of the effective image data of the adjacent photoelectric conversion elements in accordance with the distributed overlap amounts. Control means for controlling a start position of data; and an image reading device. 2. A storage means for storing image data read by the plurality of photoelectric conversion elements, wherein the control means reads out the image data from the storage means and stores the end position of the effective image data and the end position of the effective image data. The image reading apparatus according to claim 1, wherein the start position is controlled. 3. An image reading apparatus according to claim 1, wherein said input means is an operation panel. 4. The input means is capable of inputting a plurality of desired overlapping amounts when there are a plurality of overlapping portions of adjacent photoelectric conversion elements of the plurality of photoelectric conversion elements. The image reading device according to claim 1. 5. The apparatus according to claim 1, wherein said control means controls so as to warn when the overlap amount input from said input means is out of a predetermined range. An image reading device according to claim 1. 6. An image reading apparatus according to claim 1, wherein said control means equally distributes the overlap amount input from said input means.