JPH0229066A - Picture reader - Google Patents

Abstract

PURPOSE:To improve the service performance and the operability and to simplify the circuit constitution of a synthesis and demultiplex circuit by applying the input of consecutive shot by a key input section such as an operation section at a position at a half the overlapped quantity between photoelectric conversion elements. CONSTITUTION:When the input of an overlapped quantity X is finished, a CPU 101 discriminates whether or not the input of the overlapped quantity X in the input regulation condition, awaits the input of the overlapped quantity Y and writes overlapped quantities X, Y revised in a RAM 103 when the value is proper. A picture data outputted from a synthesis demultiplex increase circuit is outputted from the 2500th picture element of the input data 7b to the (4999- overlapped quantity X divided by 2)th picture element and outputs from the (overlapped quantity X + 2)th picture element of the input data 7c to the (X+4835)th picture element. Thus, the overlapped quantity of the input data 7b, 7c is corrected by the output above and the result is assembled as one line data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image reading device using a plurality of photoelectric conversion elements.

This type of image reading device is used as a digital copying machine, facsimile, filing, and CAD input device.

[Prior art]

Conventionally, in this type of image reading device, when a plurality of photoelectric conversion elements are combined into one line data, the position where the overlap of image information between the photoelectric conversion elements is connected is fixed, and the position where one photoelectric conversion element is connected is fixed, and the position where the overlap of image information between the photoelectric conversion elements is fixed is fixed. The connecting position of the photoelectric conversion elements was varied by an adjustment means such as a dip switch depending on the amount of overlap, and one line data was obtained.

However, when using a lens to form an image of the document surface onto a photoelectric conversion element, the resolving power decreases at the edge of the lens.
The amount of incident light is also reduced. Therefore, if one of the photoelectric conversion elements is fixed at a position where the amount of overlap between the photoelectric conversion elements is connected, the other may become a position where the resolution is lowered or the amount of incident light is reduced depending on the amount of overlap.

Another disadvantage is that the resolution of the left and right photoelectric conversion elements and the balance of the amount of incident light are different, creating a sense of discomfort when connecting images.

〔the purpose〕

The present invention solves the above drawbacks of the prior art, and in an image reading device using a plurality of photoelectric conversion elements, when the read image information output from each photoelectric conversion element is connected to form one line of image information, each It is an object of the present invention to provide a control device for connecting image sensors at a position that is half the amount of overlap between image sensors.

〔composition〕

For this purpose, the present invention provides an image reading device using a plurality of photoelectric conversion elements, including an overlapping amount of image information output from each photoelectric conversion element, a storage means for storing the image information, and a storage means for storing the image information. The apparatus is characterized in that it comprises a reading/writing means for controlling reading/writing, and the reading/writing means reads out the successive position of the image information read from the storage means from half of the overlapping amount.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is a schematic configuration diagram illustrating an embodiment of an image reading apparatus using the present invention. In the figure, 1 to 4 are conveyance rollers, 5 is a lighting device, 6 is an optical lens, and 7 is a CCD (charge coupled device) constituting an image sensor. In this configuration, the original is fed in the direction of the arrow in the figure and is transported by transport rollers 1 to 4. During this transportation, the lighting device 5
The original image illuminated by
7.

In this case, since the number of effective reading pixels per CCD 70 is determined, the document width that can be read is determined by determining the document reading density. However, if the document is larger than the document width that can be read by the CCD, multiple CCD must be used.

In the above embodiment, the number of effective reading pixels per CCD 7 is 5000 pixels, the maximum original width of the original to be read is 917 mm, and the original reading density is 16.
Assume that pixels/mm. Here, the number of CCD7s used is the maximum original width of 917 mm and the original reading density of 16 pixels/
From mm, the maximum number of effective reading pixels is 14,672 pixels, and as mentioned above, the number of effective reading pixels per C0D7 is 5,000 pixels, so three are required.

FIGS. 2 and 4 are schematic diagrams illustrating the relationship when the three CCDs 7 described above are used. D is the maximum document width,
6a to 6c are optical lenses, 7a to 7C are COD, OR,
X and Y indicate the overlap of the reading areas of each COD. Second
In the figure, three image sensors (CCD) 7a to 7C are used to read the maximum document width, each CCD is imaged by an optical lens 6a to 6C, and the reading area of each CCD is as shown by OR. are overlapping. This overlapping page area amount is (15000-14672)÷2=164
It is adjusted to within a pixel and satisfies the maximum document width to be read.

The original images formed on the CCDs 7a to 7C are output as analog signals from these CCDs 7a to 7C,
Since these are extremely small signals, these outputs must be amplified.

FIG. 3 is a block diagram schematically showing a processing circuit for an original image output from the COD. In the figure, 7a to 7C are CCDs.
% 8a to 8c are amplifiers, 9a to 9d are analog/digital conversion (A/D) circuits, and 10a and 10b are synthesis/separation circuits. In FIG. 3, the outputs of CCDs 7a-7C are amplified by amplifiers 83-8C. The outputs of the amplifiers 8a to 8C are converted into analog image signals by A/D conversion circuits 9a to 9C into multivalued (for example, 64 gradations) digital image signals for each pixel. The digital image signal after A/D conversion is free from noise in the original image, uneven light intensity, dirt on the contact glass, and C.
Noise appears in the regular image data due to CD sensitivity unevenness, etc. Therefore, as a measure against this noise, shading correction has conventionally been performed in the A/D conversion circuit. In this way, the output from each CCD is amplified, shading corrected, A/D converted, and input as multivalued data to the synthesis/separation circuits ioa and 10b.

In the above case, each CCD is scanned simultaneously and outputs pixel data simultaneously. At this timing, as shown in the time chart of FIG. 6(b), the CCDs 7a to 7c are synchronized in the main scanning direction by the scanning synchronization signal C (LSYNC), and the valid data from the CCDs 7a to 7C are inputted by the input control signal D ( INLGATE).

Further, in the sub-scanning direction (insertion speed) of the document, it is assumed that LSYNC outputs a control signal 16 times per 1 mm of sub-scanning. Therefore, the sub-scanning density is also 16 pixels/mm, and the main scanning density is 166 pixels/mm, which is a loss. The scanning synchronization signal is output at regular intervals to keep the charge accumulation time of the CCD constant.

Currently, image data from three CCDs 7a to 7c is analog processed in parallel between scanning synchronization signals.
As mentioned above, the amount of overlap between each CCD image is corrected, and the digital processing unit after analog processing [e.g., magnification processing, MT
F (modulation transfer function) processing, smoothing processing, etc.] Because of the need to process data during the scanning synchronization signal period, the output data from three CCDs is usually combined into one line and the amount of overlap is corrected. ing. However, three CCD7a
If the output data of ~7c are combined into one line during the period of the scan synchronization signal, the processing speed per pixel of image data will be tripled.

In the present invention, C during the scan synchronization signal interval of 312.5 μs.
CI) When processing 5000 pixels per one pixel, the processing time per pixel is 62.5 ns / 1 pixel, but if CC03 data is made into one line, the processing time is 312.5μ
Summing up during the period of s, the result is 20.8 n s/1 pixel, and the processing time is three times faster. However, the present invention has 1
Rather than grouping the output data of three CCDs in a line, the median value of the maximum document width (here, CCD7 in Figure 2)
2449th pixel of b is the center pixel) to the left and right 2
The data is divided into 7500 pixels and processed during the scanning synchronization signal period.

Therefore, the processing time is reduced to 1/2 compared to combining COD output data into one line.

Further, FIG. 4 shows the amount of overlap between CCDs. X is CCD
7b and 7c, and Y is the amount of overlap between CCDs 7a and 7b.

Normally, when correcting the amount of overlap between CCDs to create one line data, one of the two COD image data
The image data of D is fixed, and the valid data of the other image data is determined according to the amount of overlap.

Also, half of the amount of overlap x and y between each CCD, that is, X/
2. Effective data between each CCD is determined according to the amount of overlap of Y/2.

By not fixing one of the positions where the amount of overlap connects, for example, the resolution at the ends of the lenses 6a, 6b, and 6c may be reduced, and image data with a reduced amount of incident light may not be effective, thereby reducing the sense of discomfort at the joint. It can be eliminated.

FIG. 5(C) is a block diagram schematically showing a circuit utilizing the contents of the present invention. The CPU 101 is a central processing unit, and the ROM 102 stores a program for the CPU 01 to perform predetermined operations, and data for warning guidance when the overlap amounts X and Y are incorrectly input. R
AM103 is a memory for the CPU 101 to store temporary data, l10104 and 110107 are input/output elements,
The key input unit 105 is provided with keys necessary for inputting the amount of overlap. The synthesis/separation circuit 106 is a CPU1
This is a correction circuit that concatenates read image information into one line based on the overlap amounts X and Y transferred by 0I. Details will be described later.

Hereinafter, a flowchart showing an outline of the operation of the CPU 01 will be explained with reference to FIG. 5(C) and FIG. 9.

First, when there is an overlap amount change request key input from the key input unit 105, the process waits for an input of overlap lx.

After inputting the overlap lx, CPU 01 returns the above (
15000-14672) ÷ 2 = 164 pixels or more, it is determined whether there is an input of overlapping lx within the input regulation conditions of 0 or more, and if the regulation conditions are not satisfied, CPUl0I
transfers the warning guidance data stored in the ROM 102 via 110107, and causes the warning display section 108 to display predetermined warning guidance. Here, the warning display section includes, for example, a liquid crystal display, and the warning guidance data is character information data for causing the liquid crystal display to notify warning information. And again the amount of molding
The system waits for input, and repeats until a valid value is input.

Next, in the same way, the system waits for the input of the overlap amount Y, and if the values are appropriate, the changed overlap amounts X and Y are written in the RAM 103, and the system waits for an overlap amount change request or input of the reading start key, and when the input of the reading start key is input. , the overlap amounts X and Y of the RAM 103 are read, and are transferred to the synthesis/separation circuit 106 via 110104 along with control signals Zl and Z2, and reading starts.

FIG. 7 shows that the overlap amount X and the overlap amount Y input from the key input unit 102 are calculated and corrected by the CPU OO, and are converted into an overlap lx command and an overlap IY command. ) is a block diagram of parallel output to a combining/separating circuit.

It is necessary to calculate and correct the overlap amounts X and Y into hexadecimal numbers.

The block diagram of FIG. 7 will be explained with reference to the flowchart of FIG. 8.

100 is a CPU (central processing unit), 101 is a ■0 element that controls data input/output, 102 is a key input unit,
104 corresponds to the synthesis/separation circuit in FIGS. 5(al) and (b).

Further, 103 is a control signal for determining the overlap lx command on the combining/separating circuit, and is output to Z in FIG. 5(a). Furthermore, 105 is a similar control signal for determining the overlap amount Y command on the combining/separating circuit. Here, FIG. 5(a).

There are two circuits (combining/separating circuits) shown in FIG. 5(b).

Details will be described later.

When there is a request to input the amount of overlap from the key input unit 102, for example, the numeric keypad of the operation unit, the CPU 00 inputs the amount of overlap X.
is in a waiting state for input, then X is input and X is determined. Next, the CPU OO waits for the input of the overlap IY, and then Y is input and Y is determined. Next CPU1
00 performs a hexadecimal correction calculation to correct the overlap lx to the command data of the overlap amount X. Thereafter, a hexadecimal correction calculation is similarly performed for the overlap ilY, resulting in command data of the overlap amount Y. After that, overlap amount X.

The Y command is passed through 110101 in Figure 5 (a), (
Output in parallel to the circuit corresponding to b).

Fig. 6 (C1 is a timing chart showing the timing at which the CPU transfers data to the combining/separating circuit. Fig. 6 (◎IN LGATE in al. In contrast, ■FGATE in FIG. 6(C) is a control signal for determining the data line in the sub-scanning direction. ■When FGATE is "H", the data is valid. .Therefore, the amount of overlap is X.

The Y command and its control signals (Zl, Z2) are the FG of ■
It must be output and confirmed before ATE starts up. Also, when FGATE of ■ is “H”, overlap IX,
Changing the Y command is prohibited in the software. As described above, the signal (2) confirms the command for the overlap lx at the rising edge, and the signal (2) similarly confirms the command for the amount of overlap Y.

As described above, the amount of overlap X can be achieved with an easy and simple configuration.

Y is output to the separation/synthesis circuit.

As described above in FIGS. 6(a) and 6(b), three CCDs 7a are activated during the scanning synchronization signal (LSYNC) period.

The image data from 7b and 7c are input in parallel from the analog processing section to the synthesis/separation processing circuit.

In addition, the valid data area of the image data is the input control signal (I
N LGATE).

The input data 7b and 7c are input to the synthesis/separation up circuit in order from the 0th to the 4999th valid data i15000 pixels, and at this time, the image data (output data 1) output from the synthesis/separation up circuit is first input to the input data 7
From the 2500th pixel of b (4999-overlap amount
÷2)-th pixel, and then input data 7C (
Outputs from the overlap amount X÷2)th pixel to the (X+4835)th pixel. By outputting in this way, the amount of overlap of the input data 7b and 7c is corrected and combined as one line data, and the effective data amount is 14
Half of 672 pixels, 7336 pixels, can be output from the center of the document reading width. The control timings of output data 1 are E and X.

Similarly, the input data 7b and 7c are input to the synthesis/separation down circuit in sequence from the 0th to the 4999th valid data 1500.
The image data (output data 2) that is input from the 0 pixel and output from the synthesis/separation down circuit is first input from the (164-overlap ff1Y) pixel of the input data 7a to (4999
- Output up to the (overlap amount Y÷2)th pixel, and then output 249 pixels from the (overlap IY÷2)th pixel of input data 7b.
Output up to the 9th pixel.

By outputting in this way, the input data 7a, 7b
The amount of overlap is corrected, and it is summarized as line data, and half of the effective data of 114,672 pixels is 7336 pixels.
Pixels can be output from the center of the document reading width.

The control timings of output data 2 are E, X, and W.

Here, the output data of the synthesis/separation up circuit 10b is in the main scanning direction, and image data is output at 3/2 times the speed of the input data, and the output data of the synthesis/separation down circuit 10a is also in the main scanning direction. Image data is output at 3/2 times the speed of input data.

Also, here, the image data of C0D7b in the center is up to 50
00 pixels are valid, and the image data of the left and right C0D7a and CCD7C has a maximum of 4836 pixels. Also CCD7b
The amount of overlap between CCD7c and CCD7c is X, and CCD7b and CCD7
The amount of overlap with a is set to Y, and the values of X and Y are set within 164 pixels as described above.

5(a) and 5(b) are block diagrams showing the synthesis/separation up circuit 10b and the synthesis/separation down circuit 10a of FIG. 3. In the figure, 20 is a dip switch or flip-flop, and 21 is a logic that uses summation to output 1/2 of the input (hereinafter referred to as 1/2 frequency divider).
, 22.23 is the inverter, 24, 27.28 is the sum, 2
5, 26, 29° 32. 35. 36, 41, 42, 59
, 60, 61 are data selectors, 30, 31.37.3
8 is an address counter, 33, 34, 39.40 are comparators, 43, 44.45, 46.50 are flip-flops, 48.49 is an AND gate, 47 is a delay element,
55, 56, 57, and 58 are toggle RAMs (random access memories), and 51, 52, 53, and 54 are 3-state buffers with data latch functions.

Regarding the operation of the circuit with the above configuration, FIG. 6(a) and
This will be explained with reference to the time chart of FIG. 6(b).

1. In the case of the synthesis/separation up circuit, the input data 7b and 70 are latched by 3-state buffers 53, 54 and 51° 52, which have data and latch functions, respectively, and are transferred to toggle RAM 57 or 58 and toggle RAM 55.
Or data is selectively output to 56. The selection signal is the Q output and 100 output (toggle mode) of the flip-flop 44.
(control signal F in FIG. 6(a),
G). 3-state buffer with latch function 51.52
．． 53 and 54 are assumed to receive selection signals and output data.

Toggle RAM 55-5 day write/read control is C3, W
E times signal controlled, C8 is AND gate 48.49 (
The write timing is determined by C according to FIG. 6 (bll, J).
8 and WE control the read timing (Fig. 6 (a) F, G, I, , J), and the control signals of C3 (I, J signals of al, CL of B
This is obtained by shifting K1 by the delay element 47 and ANDing the toggle mode signals F and G of the flip-flop 44.

The clock for the flip-flop 44 is latched by the aforementioned LSYNC, C4:CLKIB. The flip-flop 44 divides the clock frequency by 1/2 and outputs toggle mode signals F and G. The clock of the 3-state buffers 51 and 53 with latch function is CLKIB, and the input data is CLK1.
The G signal of the flip-flop 44 is used as a control signal to output data to the toggle RAM 55.57 during the L period, and the clock of the 3-state buffer 52.54 having a latch function is CLK 1. The input data is latched by CLKl, the F signal of the flip-flop 44 is used as a control signal, and the toggle RAM 56.5 is output during the L period.
Output the data to 8.

Furthermore, the address counters of toggle RAMs 55 to 58 are
They are connected to address counters 30.31° and 37.38, respectively. Toggle RAM is such that when one RAM is in the process of writing, the other RAM is in the process of reading. Here, the currently input data is written to one, and the other RAM stores the data input at the previous stage. It is being read.

It is assumed that the data selectors 59 and 60 select and output the read data of the toggle RAM. This selection signal is
It is controlled by the F signal of the flip-flop 44.

Toggle RAM 57 for reading and writing data 7b.
The address counters 37 and 38 of 58 are presettable up counters, and are controlled by a count up clock, count start and end control signals, and an initial count signal. The counter clocks are CLKIB and CL.
As described above, the clock of B is locked so that it can process 5000 pixels during the LSYNC period, and the clock of A is locked so that it can process 7500 pixels during the LSYNC period.

First, when the counter 37 controls the write address of the RAM 57, the clock of the counter 37 is controlled by the data selector 41.
The R signal of B is input, and this becomes the B clock. The initial count value of the preset at that time starts from O, and this is because the fixed value 3 in the data selectors 35 and 36 is 0, and the selection signal F causes the O output to become the preset value of the counter. The count start/end signal is the 0 signal of the data selector 41 and becomes the D signal (IN LGATE latch signal) of the flop flip 45 described above.

Therefore, 5000 pixel data of the input data 7b is written into the RAM 57 from addresses 0 to 4999.

RAM 57 is in the process of writing, RAM 58 is in the process of reading,
When the counter 38 controls the read address of the RAM 5B, the V signal of the data selector 42 is input as the clock of the counter 38, which becomes the A clock. then,
The preset initial value is 2500, which is the fixed value 9 of the data selector 32, which is 2500, and the selection signal Z4 is switched between L and H using a jumper line or date switch, and is output to the data selector 36.35. , and the selection signal G signal of the data selector 36 (
This is because the 2500 output becomes the preset value of the counter due to the inversion of the F signal. The count start/end signal is the S signal of the data selector 42, which determines the output effective area of 7500 pixels of data during the LSYNC period.

This is a signal E obtained by latching the output control signal (OUT LGATE) with the above-mentioned A. At this time, (4999-X/2
) At the count, No. 48 from the comparator 40 becomes the Q signal of the data selector 41, and the flip-flop 50 outputs the signal X and ends counting.

The operations of the RAMs 57 and 58 repeat the above operations.

Here, (4999-X/2) is the overlap iX transferred from the CPU and latched by the flip-flop 20.
The 2 frequency divider 21 makes it X/2, and the inverter 22 makes -
The sum of the four factors is 27 and the fixed value 6=4999, that is, (4999-X/2) is the comparator 40,
This means that it is input as the comparison value of No. 39.

When the counter 37 is in read operation, the signal from the comparator 39 becomes the output Q signal of the data selector 41,
Flip-flop 50 outputs signal X and ends counting.

Also, starting the address from 2500 when reading is as follows:
This is because the data of the central CCD 7b is centrally divided.

RAM55.56 for reading and writing input data 7C
The address counters 30 and 31 are presettable up counters, and are controlled by a count up clock, a count start/end control signal, and an initial count signal. The counting clock is CLK I B and C'L
It is controlled by A of K2.

First, when the counter 30 controls the write address of the RAM 55, the clock of the counter 30 is controlled by the data selector 41.
The R signal of B is input, and this becomes the B clock. At that time, the preset initial counter value starts from 0. This is because the fixed value 1 of the data selectors 25 and 26 is O, and the selection signal F causes the 0 output to become the preset value of the counter. The other input value of the data selectors 25 and 26 is the overlap amount X inputted from the flip-flop 20, which is divided into X/2 by the 1/2 frequency divider 21.

The count start/end signal is the data selector 410P signal, and the D signal (IN
LGATE latch signal). Therefore, 5000 pixel data of data 7C is stored in the RAM 55 at addresses O to 4.
Up to 999 will be written.

RAM 55 is in the process of writing, RAM 56 is in the process of reading,
When the counter 31 controls the read address of the RAM 56, the {circle around (2)} signal of the data selector 42 is input as the clock of the counter 31, and A of CLK2 serves as the clock.

At that time, the initial value of the preset is the data selector 2 mentioned above.
6 (fixed value 1 is O), and the selection signal G (=F) causes the output of X/2 to become the preset value of the counter. The count start/end signal is the T signal of the data selector 42, and the
According to the signal, when the count value reaches (X+4835), the L signal of the comparator 34 is outputted to the flip-flop 50 via the data selector 42, and the X signal of the flip-flop 50 ends the process. Here (X+4
835) is the sum of the overlap amount X input from the flip-flop 20 with a sum of 24 and the fixed value 5=4835, that is, (
X+4835) and output to the data selector 29. The data selector 29 is fixed and the value 8 is set to 2499, and the selection signal Z3 is switched (X+48
35) is selected from the data selector 29 by the comparator 33.3.
4 is output. flip flop 50
The output X signal is connected to the selection signal input of the data selector 61 by a switching means such as a jumper line or a date switch. This is why the data selector 61 controls the output data. The operations of the RAMs 2S and 56 repeat the above operations.

2. Case of synthesis/separation down circuit In the synthesis/separation down circuit, let Y be the amount of overlap input from the flip-flop 20. In addition, input data 7b,
? As shown in parentheses in FIG. 5(b), input data 7b is a 3-state buffer 51.5 with a latch function.
2, the input data 7a is output to three-state buffers 53 and 54 having a latch function.

In the case of data 7C, the RAM 57 is in the writing operation, the RAM 58 is in the reading operation, and the counter 38 is in the RAM 58
When controlling the read address of A, the clock of the counter 38 is inputted with the ■ signal of the data selector 42, which
clock. At that time, the initial value of the preset is (1
64-Y), which means that the overlap amount Y input from the flip-flop 20 is set to -Y by the inverter 23, and the sum is 2.
It is output to 8. The fixed value 7 of the sum 28 is 164 (164-Y), which is output from the sum 28 to the data selector 32. In the synthesis/separation up circuit, the selection signal Z
4 with a jumper wire etc. to make 2500 outputs, but in the synthesis/separation down circuit, the other input (1
64-Y) is output by switching the selection signal Z4 using a jumper wire, etc. (L, H switching)
. Therefore, (164-Y) becomes the preset value of the counter.

The count start/end signal is the S signal of the data selector 42, and the E signal (OUT
LGATE clock A latch signal). At this time, comparator 4 at count (4999-Y/2)
The signal from 0 becomes the Q signal of the data selector 41, and the flip-flop 50 outputs the signal X. RAM57.
The operation of 58 repeats the above operation. Here (49
99-Y/2) is the sum of 2,7(
(4999-Y/2) is obtained from the fixed value 6=4999). This is input to the comparison value of the comparator 40°39. When the counter 37 is in a read operation, the signal from the comparator 39 becomes the output Q signal of the data selector 41, and the flip-flop 50 outputs the signal X.

In the case of data 7b, similarly, when the RAM 55 is in the writing operation, the RAM 56 is in the reading operation, and the counter 31 is controlling the read address of the RAM 56, the counter 31
The clock is inputted with the V signal of the data selector 42,
This becomes A's clock. At that time, the initial value of the preset is Y/2, which is obtained by dividing Y input from the flip-flop 20 into Y/2 by the 1/2 frequency divider 21 and inputting it to the data selector 26, and the selection signal G This is because Y/2 is selectively outputted and becomes the preset value of the counter. The count start and end signal is sent to data selector 4.
When the count value reaches 2499, the signal from the comparator 34 becomes the output U signal of the data selector 42, the flip-flop 50 outputs the signal X, and the count ends. The operations of the RAMs 55 and 56 repeat the above operations.

The output data is connected by a jumper line or the like so that the W signal of the flip-flop 50 becomes the selection signal of the data selector 61. The output data is output at the timing of output data 2.

As described above, in the present invention, the read data of the synthesis/separation up circuit is from 2500 pixels to (49
For input data 7C, it is from X/2 pixels to (4835+X) pixels. The read data of the synthesis/separation down circuit is Y/2 for input data 7b.
From pixel to 2499 pixels, input data 7a is (16
4-Y) pixels to (4999-Y/2) pixels.

Therefore, by setting the reading start position for each data 7a, 7b, and 7c from half of the overlapping amounts X and Y, the lenses (for example, 6a, 6b, and 6c in FIG. 4) that form the original image on the photoelectric conversion element can be used. By not using image data with reduced resolution at the edges and image data with reduced amount of incident light as valid data, the sense of discomfort as an image at the joint between each CCD is also removed.

Further, since it is set as (164-Y) on the hardware, if the amount of overlap is greater than or equal to 164 and less than or equal to 0, an error will occur in the read data of the combining/separating circuit. Therefore, by utilizing the present invention, inputting an appropriate amount of overlap can be easily and reliably realized with a simple circuit configuration.

〔effect〕

As described above, according to the present invention, by connecting the photoelectric conversion elements at a position that is half of the amount of overlap between them, the image at the joint can be reproduced without any discomfort, and by inputting the amount of overlap using a key input section such as an operation section, Serviceability and operability can be improved, and the circuit configuration of the synthesis/separation circuit can be simplified. Furthermore, when the variable input overlap amount is below or above a predetermined value, the input is not valid, and a warning is displayed to encourage the correct value to be entered, and to prevent erroneous input, the overlap amount can be ensured. It is possible to provide an image reading device that has the effect that correction can be performed with an inexpensive configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram illustrating an embodiment of an image reading device using the present invention, FIG. 2 is a diagram showing the reading width of three CCDs, and FIG. 3 is a block diagram showing a document image processing circuit. Figure 4 shows the same reading width as Figure 2, Figure 5 (
al, (bl is a block diagram showing the synthesis/separation up and down circuits, the same figure (C) is a block diagram showing the overlap amount, and the same figure (a
) and (b) are block diagrams of circuits that overlap the synthesis/separation circuits and prompt the input of appropriate values to output tx and y commands; Figures 6 (a) and fb) are time charts of each part; (C1 is a timing chart in which the CPU transfers commands for the amount of overlap FIG. 8 is a block diagram showing a specific example of a circuit that outputs the command Y. When the command for the amount of overlap X and Y is input from the keys on the operation panel,
9 is a flowchart showing the output to the combination/separation circuit of bl, when the overlap amounts X and Y are input from the keys on the operation unit and sent to the combination/separation circuit of FIGS. 5(a) and (b). 12 is a flowchart outlining the steps from determining whether the output and input are appropriate, prompting for optimization, and actually reading the image. 7a, 7b, 7c...Photoelectric conversion element, OR...Overlapping amount, lO...Synthesis/separation up, down circuit, 10
8...Warning display section. Fig. 1 Fig. 2 Fig. 2 Fig. 5 (C)

Claims (5)

[Claims] (1) In an image reading device using a plurality of photoelectric conversion elements, controlling the overlapping amount of image information output from each photoelectric conversion element, a storage means for storing the image information, and reading and writing of the storage means. 1. An image reading device comprising a reading/writing means, wherein the reading/writing means reads out a reading position of image information read from a storage means from half of the amount of overlap. (2) In an image reading device using a plurality of photoelectric conversion elements, the image information of a document is read and the image information output from each photoelectric conversion element is read in a superimposed manner, and the image information output from the photoelectric conversion elements is output. A storage means for storing image information to be read, a read/write control means for controlling reading and writing of the storage means, and an operation panel for controlling operations of an image reading device, the image information being read from the storage means. An image reading device in which the readout position is set at half the amount of overlap, characterized in that the amount of overlap of image information output from the photoelectric conversion element can be controlled by the operation panel. . (3) In an image reading device using a plurality of photoelectric conversion elements, the image information of a document is read, and the image information output from each photoelectric conversion element is read in a superimposed manner, and the image information is output from the photoelectric conversion elements. A storage means for storing image information to be read, a read/write control means for controlling reading and writing of the storage means, and an operation panel for controlling operations of an image reading device, the image information being read from the storage means. In the image reading device in which the readout position is set to half the amount of overlap, the amount of overlap of the image information output from the photoelectric conversion element can be variably input using the operation panel, and the amount of overlap that has been variably input is set to a predetermined value. An image reading device characterized in that when the input value is less than or equal to or more than that, the input is invalidated. (4) The image reading apparatus according to claim (3), further comprising means for displaying a warning when the variably input overlap amount deviates from a predetermined value. (5) The predetermined value of the variable input overlap amount is the number of pixels obtained by subtracting the maximum readable area of each photoelectric conversion element by the effective reading area determined based on the reading density and the maximum readable document area. 4. The image reading device according to claim 3, wherein the value is divided by the number of photoelectric conversion elements used.