JP2710775B2 - Image reading device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image reading apparatus, and more particularly, to a digital copying apparatus which projects an image on a plurality of photoelectric conversion elements and obtains image information read by the photoelectric conversion elements. , Facsimile,
The present invention relates to an image reading device applicable to a CAD (Computer Aided Design) input device and the like. (Prior Art) In a conventional image reading apparatus using a plurality of photoelectric conversion elements (image sensors), in order to obtain read image information of the photoelectric conversion elements, the order of read pixels is corrected by correcting the amount of overlap between them. The number of effective pixels is not mentioned only by changing. Further, a processing method of counting down the reading time counting means has not been adopted. In such a conventional image reading apparatus, the image information at the left and right ends becomes an uncertain image, and when output by a printer or the like,
This causes a problem that white streaks or black streaks occur. (Purpose) The present invention has been made in order to solve such problems of the related art, and its purpose is to enable input of a simple overlap amount and simple read control,
An object of the present invention is to provide an image reading apparatus capable of improving image quality. (Structure) In order to achieve the above object, the present invention relates to an image reading apparatus which reads a document image as it is in a main scanning direction by a plurality of photoelectric conversion elements arranged in a line and reads each document line by line. The conversion element includes first to third three photoelectric conversion elements, and the first to third photoelectric conversion elements have a part of a reading range of the first photoelectric conversion element and the second photoelectric conversion element. The first overlapping region and the second photoelectric conversion element are arranged so as to have a second overlapping region in which a part of a reading range of the second photoelectric conversion element and the third photoelectric conversion element are partially overlapped. A first overlap amount corresponding to the overlap amount of the first overlap region and a second overlap amount corresponding to the overlap amount of the second overlap region; Or third photoelectric conversion When outputting the image signal input from the conversion element, the image signal from the first photoelectric conversion element corresponding to the first overlap amount is invalidated, and the first photoelectric change element corresponding to the non-overlapping area The image signal from the third photoelectric conversion element corresponding to the second overlap amount is invalidated, and the image signal from the third photoelectric conversion element is invalidated. And control means for validating the image signal from the third photoelectric conversion element corresponding to the area where the image is not to be obtained. Hereinafter, a specific description will be given based on an embodiment of the present invention. FIG. 1 is a schematic configuration diagram illustrating an embodiment of an image reading apparatus using the present invention. In the figure, reference numerals 1 to 4 denote conveying rollers, 5 an illumination device, 6 an optical lens, and 7 a CCD (charge coupled device) constituting an image sensor. In this configuration, a document is fed in the direction of the arrow in the figure and is transported by transport rollers 1-4. The original image illuminated by the illumination device 5 during the conveyance is formed on the CCD 7 by the optical lens 6. In this case, since the number of effective reading pixels per CCD7 is determined, the width of the original that can be read is determined if the original reading density is determined, but if the original is wider than the original that can be read by the CCD, Multiple CCDs must be used. In the above embodiment, it is assumed that the number of effective read pixels per CCD 7 is 5000 pixels, the maximum original width of the original to be read is 917 mm, and the original read density is 16 pixels / mm. Here, the number of CCD7 used is the maximum document width of 917 mm above,
Maximum reading pixel number is 1 from document reading density of 16 pixels / mm
Since 4672 pixels are required, and the number of effective read pixels per CCD7 is 5,000 as described above, three pixels are required. FIG. 2 is a schematic view for explaining the relationship when the above three CCDs 7 are used. D is the maximum original width, 6a to 6c are optical lenses, 7a to 7c are CCDs, and OR is the reading area of each CCD. Indicates overlap. In FIG. 2, in order to read the maximum original width D, three image sensors (CCD) 7a to 7c are used. Each CCD is formed by an optical lens 6a to 6c, and the reading area of each CCD is OR.
They overlap as shown by. The overlapping area amount is set to (15000−14672) 6722 = 164 pixels or less, and is adjusted so as to satisfy the maximum reading original width D. In other words, as is clear from FIG. 2, the three CCDs are 1
They are arranged side by side so that part of the image for the line is read in an overlapping manner. Original images formed on the CCDs 7a to 7c are output from these CCDs 7a to 7c as analog signals. However, since these signals are extremely small, these outputs must be amplified. FIG. 3 is a block diagram schematically showing a processing circuit for a document image output from a CCD. In the figure, 7a to 7c are CCD, 8a
To 8c are amplifiers, 9a to 9d are analog / digital conversions (A /
D) Circuits 10a and 10b are synthesis / separation circuits. In FIG. 3, the outputs of the CCDs 7a to 7c are amplified by amplifiers 8a to 8c. The outputs of the amplifiers 8a to 8c are converted from analog image signals into multi-level (for example, 64 gradations) digital image signals for each pixel in A / D conversion circuits 9a to 9c. In the digital image signal after the A / D conversion, noise appears in the regular image data due to noise of the original image, uneven light amount, stain on the contact glass, uneven sensitivity of the CCD, and the like. Therefore, as a countermeasure against this noise, shading correction has been conventionally performed in the A / D conversion circuit. As described above, the outputs from the respective CCDs are amplified, subjected to shading correction, A / D converted, and input to the combining / separating circuits 10a and 10b as multivalued data. In the above case, each CCD is simultaneously scanned and outputs pixel data at the same time. This timing corresponds to the scan synchronization signal (LS) as shown in the time chart of FIG.
YNC) synchronizes the CCDs 7a to 7c in the main scanning direction and
Valid data from c is controlled by a control signal (LGATE). In the sub-scanning direction (insertion speed) of the document, it is assumed that LSYNC outputs a control signal 16 times per 1 mm of sub-scanning. Therefore, the sub-scanning density is also 16 pixels / mm, and the main scanning density is 1 pixel.
It is equal to 6 pixels / mm. The scan synchronization signal is output at regular intervals in order to make the charge accumulation time of the CCD constant. At present, the image data from the three CCDs 7a to 7c are analog-processed in parallel between the scan synchronization signals. However, as described above, the amount of overlap between the CCD images is corrected, and the digital processing unit after the analog processing is performed. For example, scaling processing, MTF (modulation transfer function) processing, smoothing processing, etc.) also require three CCs due to the need to process data during the period of the scan synchronization signal.
The output data from D is made into one line, and the amount of overlap is corrected. However, if the output data of the three CCDs 7a to 7c is combined into one line during the period of the scan synchronization signal, the processing speed of image data per pixel is tripled. In the present invention, the CCD1
When processing 5,000 pixels per pixel, the processing time per pixel is 62.5 ns / 1 pixel, but when 3 CCD data are combined into one line during 312.5 μs, it becomes 20.8 ns / 1 pixel, processing Time is three times faster. However, in the present invention, the output data of the three CCDs are not combined on one line, but the median value of the maximum original width D (here, FIG. 2).
The center pixel is the 2449th pixel of the CCD 7b)
Data of 7,500 pixels are processed during the scan synchronization signal period by dividing the data, one is processed in the main scanning direction, and the other is processed in the reverse direction, thereby reducing the processing time. This is because the document insertion position is inserted as a center reference, so that division processing at the center can be performed. One processing direction is the main scanning direction (synthesis / separation circuit 10a in FIG. 3), and the other direction is the reverse direction (synthesis / separation circuit 10b in FIG. 3). Can be processed without discomfort. The processing that does not cause a sense of incongruity is, for example, a processing such as pixel thinning in the post-processing. (1) As shown in FIG. If the other direction is reversed, the position of a in FIG. 1 must be calculated in order to calculate where the reference surface of the document is. (2) As shown in FIG. 5b, when the image data is divided at the center and both are scanned in the same direction, the divided portions shown by b in the figure do not match. (3) In the present invention, as shown in FIG. 5c, the image data is divided into the center with the original at the center, and when one is set in the main scanning direction and the other is set in the opposite direction, the reference of the original is at the center. Image data is connected without discomfort. As can be seen from the above (1), (2), and (3), the input image data is divided into two lines, one of which is in the main scanning direction and the other is in the reverse direction, thereby reducing the processing time of pixels. In addition, image information without a sense of incongruity in post-processing can be obtained. FIG. 8 is a diagram illustrating the overlap amount X and the overlap amount Y input from the key input unit 102, which are calculated and corrected by the CPU 100, and converted into a command for the overlap amount X and a command for the overlap amount Y. FIG. 4 is a block diagram for outputting to a circuit in parallel. The output data is 4999 pixels from 2498 pixels of the output data 2 for the input data 7b in the synthesis / separation up circuit 10a, and x + 48 pixels from the output data x pixels for the input data 7c.
There are 36 pixels, and each output timing is controlled by output gates 2 and 3 (x is the overlap amount x). In the synthesis / separation down circuit 10b, the input data 7b is changed from 2500 pixels of the output data 3 to 0 pixel, and the input data 7a is changed from y + 4836 pixels of the output data 3 to the y pixel. (Y is the amount of overlap y). Also, here, the values of x and y are 50
00 pixels are valid, and the overlap amount with the left and right CCDs 7a and 7c is x, y
It is what it was. The values of x and y are within 164 pixels as described above. Further, the reason why the median divided data of the center CCD 7b is different is that the data is required in the next stage of the image processing unit. That is, the overlap amounts x and y need to be arithmetically corrected to hexadecimal numbers. The block diagram of FIG. 8 will be described with reference to the flowchart of FIG. Reference numeral 100 denotes a CPU (Central Processing Unit), 101 denotes an IO element for controlling input / output of data, 102 denotes a key input unit, and 104 denotes a synthesis / separation circuit in FIG. When there is a request for input of the overlap amount from the key input unit 102, for example, the numeric keypad of the operation unit, the CPU 100 waits for the input of the overlap amount x, and then x is input and x is determined. next
The CPU 100 waits for the input of the overlap amount y, and then y is input and y is determined. Next, the CPU 100 performs a hexadecimal correction operation in order to correct the overlap amount x to command data of the overlap amount x. Thereafter, similarly, a hexadecimal number correction operation is performed on the overlap amount y, and command data of the overlap amount y is obtained. Thereafter, commands of the overlap amounts x and y are output in parallel to a circuit corresponding to FIG. FIG. 6 is a block diagram showing the combining / separating up circuit 10a and the combining / separating down circuit 10b of FIG. In the figure, 20 is a data selector, 21 is a flip-flop, 22 is a sum, 23 is an inverter, 24 and 25 are data selectors, 26 and 27 are address counters, 18 and 29 are sums, 30, 31 are NAND gates,
32 and 33 are data selectors, 34 and 35 are address counters, 3
6, 37 is a NAND gate, 38 is a data selector, 39, 40, 41 are flip-flops, 42 to 45 are toggle RAMs (random access memory), 46, 47 are state buffers, 48 to 50 are data selectors, 51 is an inverter, 52 to 55 are flip-flops, 56 to 59 are AND gates, and 60 is a data selector. The operation of the circuit having the above configuration will be described below with reference to the time chart of FIG. First, the setting data 10 which is the command of the overlap amount x and the command of the overlap amount y is synchronized with the sub-scanning direction control signal (FGATE) and the scanning synchronization signal (LSYNC), and the flip-flop 21
And output data 10 is obtained. The fixed setting data 11 is 0 at the time of combining / separating up, and 0 at the time of combining / separating down.
4836. In addition, in FIG. 6, the setting data 10 and the fixed setting data 11 from the CPU are summed up by the sum 22, so that a plurality of overlapping amounts can be input. Here, the fixed setting data 11 is the initial fixed data, and the CP
By making the setting data 10 from U easily variable, it is possible to easily cope with a temporal change in the OR (overlapping amount) in FIG. 1. In case of combining / separating up input data 7a and 7b are latched by flip-flops 40 and 41, respectively, and toggle RAM 42 is provided by 3-state buffers 46 and 47.
Or 43, the data output of RAM44 or 45 is selected. The selection signal is controlled by the NAND gates 56 and 57 (control signals G and H in FIG. 7). The three-state buffers 46 and 47 output L. The write / read control of the toggle RAMs 42 to 45 is controlled by the CS and WE signals, and CS controls the write timing by the AND gates 58 and 59 (FIGS. 7 and 7) and the read timing by CS and WE (FIG. 7). FIG. 7 (E, F, I, J). 7th control signal of CS
The I and J signals in the figure are obtained by shifting the clock of CLK1 by the delay circuit 54 and by ANDing the toggle mode signals E and F of the flip-flop 53. For the flip-flop 43, the clock obtained by inverting the above-mentioned LGATE (FIG. 4) with the signal inverted by the CLK1 inverter 51 is referred to as C, E, and F in FIG. ). 3-state buffer 46,47
Are the NAND output signals of the E and F signals of the flip-flop 53 and the LGATE latch signal of the flip-flop 52. Further, the address counters of the toggle RAMs 42 to 45 are connected to the address counters 26, 27, 34, 35, respectively.
Toggle RAM is used when one RAM is in the write operation and the other is not.
The RAM is being read, in which the currently input data is written into one, and the other RAM is reading the data input in the previous stage. The data selectors 48 and 49 select and output the read data of the toggle RAM. This selection signal is controlled by the E signal of the flip-flop 53. The address counters 34 and 35 of the RAMs 42 and 43 for reading and writing the data 7b are preset up counters, which are controlled by a count up clock, a control signal for starting and ending counting, and an initial count signal. The clock of the counter is controlled by the inverter output B of CLK1 and the output A of CLK2. As described above, the clock of B is LSYN.
The clock capable of processing 5,000 pixels during the period C, and the clock A capable of processing 7,500 pixels during the LSYNC period. First, when the counter 34 is in the write address control of the RAM 42, the clock of the data selector 60 is inputted to the counter 34, which becomes the B clock. At this time, the initial count value of the preset becomes 0, because the setting data 4 is 0 in the data selector 32 (the setting data 5 is 2498) and the 0 output becomes the preset value of the counter by the selection signal C. . The count start / end signal is the M signal of the data selector 60, which is the C signal CLGATE latch signal of the flip-flop 52 described above. Accordingly, data of 5000 pixels of data 7b is written to the RAM 42 from addresses 0 to 4999 (FIG. 7T). RAM42 is writing, RAM43 is reading, and the counter is
When 35 is the read address control of the RAM 43, the P signal of the data selector 60 is input to the clock of the counter 35, which becomes the A clock. Then, the initial value of the preset
2500, which means that the setting data 7
This is because 2500 is set (setting data 6 is 0), and 2500 output becomes the preset value of the count by the selection signal C. This is because it becomes a preset value of the count. The count start / end signal is the N signal of the data selector 60, and the D signal (LGATE, clock A) of the flip-flop 55 described above.
Latch signal). At this time, the signal from the NAND gate 37 becomes the signal of the output R of the data selector 38 and the set signal Q of the flip-flop 39 at the 5000th count.
The operations of the RAMs 42 and 43 repeat the above operations. When the counter 34 is in the read operation, the signal from the NAND gate 36 becomes the signal of the output R of the data selector 38 and becomes the set signal Q of the flip-flop 39. Also, the address starts from 2500 at the time of reading by dividing the data of the central image sensor (CCD) 7b into the center, and since the combining / separating up is in the same direction as the main scanning direction, the up count is performed. The address counters 26 and 27 of the RAMs 44 and 45 for reading and writing the data 7a are preset counters that can be preset, and are controlled by a count up clock, a control signal for starting and ending counting, and an initial count signal. The counting clock is controlled by the inverter output B of CLK1 and the output A of CLK2. First, when the counter 26 controls the write address of the RAM 44, the O signal of the data selector 60 is input to the clock of the counter 26, which becomes the B clock. At this time, the initial counter value of the preset becomes from 0. This is because the setting data 2 of the data selector 24 is 0 (the other input value of the data selector 24 is x
Value) and the selection signal C causes the 0 output to become the preset value of the counter. The count start / end signal is the K signal of the data selector 60, and becomes the C signal (LGATE latch signal) of the flip-flop 52 described above. Therefore, RAM42
Is written with data of 5000 pixels of data 7a from address 0 to 4999 (FIG. 7U). RAM44 is writing, RAM45 is reading, counter
When 27 controls the read address of the RAM 45, the P signal of the data selector 60 is input to the clock of the counter 27, which becomes the A clock. At this time, the initial value of the preset is inputted from the key input unit 102 in FIG. Data 11
This is because the sum of (0) is the value selected by the data selector 25 (setting data 3 is 0), and the selection signal C causes the command of the overlap amount x to become the preset value of the counter. The count start / end signal is the L signal of the data selector 60. When the count value at the start of counting reaches (overlap amount x + 4836) by the set signal of the flip-flop 39, the reset signal S of the flip-flop 39 is output, and the flip-flop 39 is output. The process is terminated by the Q output of 39. The output data of the data selector 40 is selected based on the Q output, and a command of the overlap amount x is output. The operations of the RAMs 44 and 45 repeat the above operations. Further, by adjusting the amount of overlap between the data 7a and the data 7b only by the data 7a, a simple configuration is achieved, and the ease of adjustment is considered. This adjustment can be confirmed in an image by connecting to an external measuring instrument (for example, an oscilloscope) or a printer. Further, since the valid data of the data 7a is 4836 pixels (the reason is as described above), the output of the sum 22, that is, the sum of the inverter output of the command of the overlap amount x + 0 (fixed setting data 11) and the count value is obtained. As a result, (the command of the overlap amount x + 4836−x = 4836), the 4836 count is determined as the output data of the sum 18. Therefore, by taking the NAND of the signal, the read count of the data 7a is determined, and the read counter is determined. Is the reset value of the flip-flop 39. 2. In the case of combining / separating down In this case, the RAM writing operation of combining / separating down is the same as the RAM writing operation in the case of combining / separating up, so the description is omitted. Next, a description will be given of the RAM read operation of the synthesis / separation down. In the case of data 7b, the RAM 42 is
43 is being read, and when the counter 35 controls the read address of the RAM 43, the clock of the counter 35 is set to the data selector 60.
Is input, and this becomes the clock of A. At this time, the initial value of the preset is 2500, because the setting data is 2500 in the data selector 33 (setting data 6 is 0) and the 2500 output becomes the preset value of the count by the selection signal C. The count start / end signal is the N signal of the data selector 60 and the D signal (LGATE, clock A latch signal) of the flip-flop 55 described above. Since the counter 35 is an up / down counter,
At the time of reading by the up / down control signal C, down counting is performed. At this time, the NAND gate 37 at 0 count-1st
Is the output R signal of the data selector 38 and the set signal Q of the flip-flop 39. In this case RAM4
The operations of 2,43 are toggle operations. Further, the address starts from 2500 at the time of reading by dividing the data of the center CCD (FIG. 2B) into the center, and the down-counting is performed because the synthesis / separation down is in the opposite direction to the main scanning direction. In the case of the data 7c, similarly, when the RAM 44 is performing the write operation, the RAM 45 is performing the read operation, and when the counter 27 controls the read address of the RAM 45, the clock of the counter 27 receives the P signal of the data selector 60. Clock. At this time, the initial value of the preset is input from the key input unit 102 in FIG. 8 and the command of the overlap amount y subjected to the operation correction (the overlap amount y is corrected to the hexadecimal number operation) by the CPU 100 and the fixed value at the time of combining / separating down. Sum of setting data 11 (4836),
That is, the command of the overlap amount y is +4836, which is the value selected by the data selector 25 (setting data 3 is 0), and the command +4836 of the overlap amount y becomes the preset value of the counter by the selector signal C. is there.
The count start / end signal is the L signal of the data selector 60. When the count start count value becomes a command of the overlap amount y by the set signal of the flip-flop 39, the reset signal S of the flip-flop 39 is output.
The operation is terminated by the Q output of the flip-flop 39. This Q
It is assumed that the output data of the data selector 50 is selected according to the output and a command of the overlap amount x is output. Further, since the counter 27 is an up / down counter, the down count at the time of reading is performed by the up / down control signal C. In this case, the operation of the RAMs 44 and 45 is a toggle operation. In the present invention, the fixed setting data 11 is a fixed value (0 at the time of synthesis / separation up, 4836 at the time of synthesis / separation down), but it is also easy to input from the key input unit 102. Further, by adjusting the amount of overlap between the data 7b and 7c using only the data 7c, a simple configuration is achieved, and the ease of adjustment is considered. This adjustment can be confirmed in an image by connecting to an external measuring instrument (for example, an oscilloscope) or a printer. Since the valid data of the data 7c is 4836 pixels (the reason is as described above), the output of the sum 22, ie, the command +4836 (fixed setting data 11) of the overlap amount y, takes the sum of the inverter output and the count value ( Since the command of the overlap amount y is + 4836−4836 = y), the 4836 count is determined as the output data of the sum 18. By taking the NAND of the signal, the read count of the data 7c is determined, and the flip-flop 39 of the read counter is determined. Reset value. According to the present embodiment, a plurality of image sensors (CCD)
In the image reading apparatus using the above, the amount of overlap between the CCDs can be summarized as one line of image information as an offset value based on the maximum number of effective pixels, and between the CCDs based on the maximum number of effective pixels. The overlap amount is defined as an offset value, and one of the CCDs is determined by the offset value between adjacent CCDs.
And the other can be combined as one line of image information without correction. In addition, two lines are simultaneously processed in the center of the image, and when writing image information to the memory in one line, writing is performed in the main scanning direction, and reading is performed in the opposite direction when reading, and based on the maximum number of effective pixels. The amount of overlap between the CCDs can be used as the offset value, and the maximum number of effective pixels + the number of offset pixels can be used as the preset value of the down counter.
One CCD can be corrected with an offset value between CCDs, and the other can be collected as one line of image information without correction. Also, by providing a plurality of input units for the overlapping amount, even if the overlapping amount varies with time from the initial overlapping amount, it can easily cope with the change and always obtain accurate and appropriate read image information. be able to. (Effects) As is clear from the above description, according to the present invention configured as described above, the setting and changing of the overlap amount can be easily performed by the overlap amount setting means. Further, among the first to third photoelectric conversion elements, all image signals from the second photoelectric conversion element disposed at the center are validated by the control means, and the first and third photoelectric conversion elements disposed at both ends are effective. Of the image signals of the photoelectric conversion element, the image signal of the area overlapping with the second photoelectric conversion element was invalidated, so that simple readout control can be performed, and
The image quality can be improved by moving the joint portion of the image formed when the image data from the plurality of photoelectric conversion elements are connected away from the center of the one-line image.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram illustrating an image reading apparatus using the present invention, FIG. 2 is a schematic diagram illustrating a relationship between a maximum original width and a CCD, and FIG. FIG. 4 is a block diagram for explaining the circuit of the reading apparatus, FIG. 4 is a time chart for explaining the operation timing of the circuit of FIG. 3, and FIGS. 5a, 5b and 5c are diagrams for explaining the division of respective image data. FIG. 6 is a diagram showing a synthesis / separation up circuit and a down circuit. FIGS. 7 (A) and 7 (B) are time charts thereof. FIG. FIG. 9 is a block diagram showing a specific example of a circuit for outputting an overlap amount command to the combining / separating circuit. FIG. 9 is a flow chart from when the overlapping amount is input to when it is output to the combining / separating circuit in FIG. 7a, 7b, 7c ...: A plurality of photoelectric conversion elements.

Claims (1)

(57) [Claims] In an image reading apparatus in which an original image is divided in a main scanning direction by a plurality of photoelectric conversion elements arranged in a line and read line by line, the plurality of photoelectric conversion elements are first to third three photoelectric conversion elements. These first to third photoelectric conversion elements include a first overlapping region where a part of the reading range of the first photoelectric conversion element and the second photoelectric conversion element is partially overlapped, and a second photoelectric conversion element. A first overlapping area corresponding to an overlapping amount of the first overlapping area, while being arranged so as to have a second overlapping area in which a part of the reading range of the conversion element and the third photoelectric conversion element is overlapped; An overlap amount setting unit capable of arbitrarily setting and changing an amount and a second overlap amount corresponding to the overlap amount of the second overlap region; and an image signal input from the first to third photoelectric conversion elements. When outputting Invalidates an image signal from the first photoelectric conversion element corresponding to the first amount of overlap, validates an image signal from the first photoelectric change element corresponding to a non-overlapping area, All the image signals from the photoelectric conversion elements are valid, the image signals from the third photoelectric conversion elements corresponding to the second overlap amount are invalidated, and the third photoelectric conversion elements corresponding to the non-overlapping areas Control means for validating the image signal from the image reading device.