JPS6326069A - Image enlarging and reducing circuit - Google Patents

Abstract

PURPOSE:To heighten the processing speed of enlarging and reducing by providing latch registers between the image memory and the shift register of a source side and between the shift register and the image memory of a destination side respectively, thereby making the shifting and transfer of image data simultaneously. CONSTITUTION:A memory control circuit 3 reads 16 words from an image memory 1 and loads them in the latch registers 100-1015 of the source side. In this time, when the shift registers 40-415 of the source side are not shifting, and donot hold data, words are loaded in 40-415 and shifted based on the enlarging signal of an enlarging and reducing signal generating circuit 7. Then, one is added to the address of horizontal direction, and 16 pieces of words are loaded in registers 100-1015. Enlarged image data are stored in the shift registers 50-515 of the destination side, and when data are inputted to all bits, loaded in the latch registers 110-1115 of the destination side, and further transferred to an image memory 2 and stored. At the same time, next enlarged image data are stored in 50-515.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image enlarging/reducing circuit capable of simultaneously performing an enlarging/reducing shift operation and image data transfer.

[Background technology]

As an image enlargement/reduction circuit, for example, Utility Application No. 59-134
There is one proposed by No. 738 (filed on September 5, 1980). This image scaling circuit loads the image data to be scaled into the source shift register, and when loading the contents from the source shift register to the destination register, the shift clock frequency ratio of both registers is set to the scaling ratio. By directly changing the corresponding image data to the destination register, the enlarged/reduced image data is generated and the image data is transferred to the RA
It is read from 21 RA''v1 recorded in M and stored in the image memory ('6).

According to this image enlargement/reduction circuit, when using the same line of image data redundantly for the example: Woman', Enlarged Dog Samurai,
By reading image data of the same content from the RAM, it is possible to omit shift operations using shift registers for overlapping lines, thereby increasing processing speed.

[Problem that the invention seeks to solve]

However, according to the image enlargement/reduction circuit described above, the image data is transferred from the image memory to the shift register, the shift operation for enlargement/reduction in the shift register, the shift operation of the enlarged/reduced image data in the shift register, and the image Since data cannot be transferred from the shift register to the image memory at the same time, there is a limit to increasing the processing speed.

[Means for solving problems]

The present invention has been made in view of the above, and in order to further speed up the processing speed of image scaling by performing the above-mentioned shift operation and transfer at the same time, it is possible to The present invention provides an image enlarging/reducing circuit in which a latch register is provided between a shift register on the nation side and an image memory.

Hereinafter, the image scaling circuit according to the present invention will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and as shown in FIG. 3(a), image data of MXN words (for example, 1 word is 16 bits) is transferred to M lines from 0 to M-1. 0~N-
An image memory 1 that stores the image data at address N of 1, an image memory 2 that enlarges and reduces the image data of the image memory 1, and a memory control circuit 3 that controls writing and reading of the image memory 1.2. A source-side shift register 4 that is loaded with image data in the memory 1 and scales it up or down by a shift operation, and a destination-side shift register 5 that is loaded with the scaled image data and scales up or down according to the scaling ratio. In order to achieve this, an enlargement/reduction signal generation circuit 7 controls the frequency ratio of the shift clock of the shift register 4.5, a sequence control circuit 9 controls the sequence of image data transfer, loading to the shift register, etc., and an image memory 1.
A source-side launch register 10 stores the image data read from the shift register 4 and loads it into the shift register 4 when the shift register 4 is not shifting or does not hold image data; a destination side latch register 11 that launches the image data when the data is loaded;
It has a launch register control circuit 12 that controls latch registers 10 and 11.

FIG. 2 shows the shift register 4.5 and latch register 10.11 of FIG. 1, with 16 shift registers 4.5 and 4.1, respectively. -・・・-・-・413.5o, 51
"""-' 5 + s and 16 latch registers 10°, 10., ---1・10.6.11°, 11.
------・11. It shows that it is composed of S.

In the above configuration, a case will be described in which the image data in the image memory 1 is enlarged by 1.41 times 6 times and stored in the image memory 2. First, the reciprocal of the magnification rate 1.41 is 1/
1.41=0.71 is calculated and added by an adder (not shown). FIG. 3(B) shows the relationship between the number of additions and the added value, and the fact that when there is no carry in the added value, image data of the same line is repeatedly employed. The memory control circuit 3 controls the image memory 1 based on the addition result.
16 words, that is, (
0, 1, 2, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9
, 9, 10, 11) and read out the words of lines 100, 103, ------- on the source side.
-10,, Herod. At this time, if the source-side shift registers 4°, 41""-""' 4, s are not in the process of shifting and do not hold data, the source-side shift registers 4°, 4. -43, and shifted based on the enlargement signal of the enlargement/reduction signal generation circuit 7. Next, +1 is added to the horizontal address and the third
The 16 words of the above-mentioned line in the first column of FIG. ．． 101-...-10
2. Herod. At this time, if the source side shift register 4°, 4+'-'-...-41, is in the process of shifting or holds data, the source-side launch register 100.10+ --------- ---1 (The contents of Ls are the source side shift register 4°, 4I...
...4 and 5 are not loaded and are held on hold. At the same time, source side latch registers 10°, 1(
Loading to L "-"--.-10+s is also suspended.

This suspension is caused by the source side shift register 4°, 4, ---
------41. It is released when the is in the middle of a shift or leaves the state of holding data. Repeating the above operations, the source side shift register 4°, 41...
Image data is loaded into 415 and enlarged based on the enlargement signal from the enlargement/reduction signal generation circuit 7.

The enlarged image data is stored in the destination shift registers 5°, 51-. ．． 11゜---”-
'-' 11, loaded into s. Destination side latch register 11o, 11. ------11
The 16 words of enlarged image data loaded in 1s are transferred to the image memory 2 and stored therein, and at the same time the destination side shift register 50% DI--"--'
5 The next enlarged image data is stored in Is.

At this time, the destination side latch register 11
゜, 111 ・・−・−−−−−11+ If the contents of s have not all been transferred to the image memory 2, the destination side shift register 5゜, 51”'−−−
The loading of the contents of 5 Is to the destination side latch registers 11°, 111 and 111s is suspended, and the shift clock is also stopped.

The above-described operations are repeated 7 and when the enlargement operation for all target words is completed, the contents of the enlarged image are stored in the image memory 2.

Reduction operations can be performed in the same way. First, if the reduction rate is, for example, 0.4, an adder adds 0 and 4.

The relationship between the added value and the number of additions is as follows.

In the above table, if the line with carry corresponds to the line in FIG.
゜, 10+''-...-1ots.Hereinafter, based on the reduction signal output from the enlargement/reduction signal generation circuit, the source side shift register 4゜, 4, -----.
This is the same as the enlargement operation except that the reduction is performed at -41, so the explanation will be omitted. In addition, in the above embodiment, since 16 registers are used, it can also be applied to rotation of image data by 90 degrees.

〔Effect of the invention〕

As explained above, according to the image scaling circuit of the present invention, a launch register is provided between the image memory and the shift register on the source side, and between the shift register and the image memory on the destination side.
By performing the image data shift operation and transfer at the same time, the enlargement/reduction processing speed can be further increased.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention. Figure 2 is the first
Enlarged view of the main part of the figure. 30th (a) and (b) are explanatory diagrams showing the relationship between the memory, the addition value of the enlargement/reduction ratio, and the carry; FIG. Explanation of symbols■, 2---Image memory 3---Memory control circuit 4.5---Shift register 10.11-1---Latch register Patent applicant
Fuji Xerox Co., Ltd. Agent Patent Attorney Taira 1) Tadao Diagram 3 (If ζ mouth)

Claims (1)

[Scope of Claims] An image scaling circuit that scales up and down the image data stored in an image memory to scale up and down the image, comprising: scaling means that scales up and down the image data according to a scaling rate; a first register means for temporarily storing the image data outputted from the image memory and outputting it to the scaling circuit; An image enlargement/reduction circuit comprising: second register means for outputting to a memory; and control means for simultaneously performing enlargement/reduction operations of the enlargement/reduction means and input/output operations of the first and second registers. .