JPH05334179A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To provide a memory integrated circuit provided with a bit weight reversion control means for converting output data into a data format corresponding to each processor to be used in a processor using plural different processors. CONSTITUTION:The memory integrated circuit is constituted of a memory cell array 3 for storing data, the 1st address buffer 1 for inputting a row address value, a row decoder 2 for decoding a row address value inputted from the buffer 1, the 2nd address buffer 8 for inputting a column address value. Furthermore, the same is constituted of a column decoder 6 for decoding the column address value inputted from the buffer 8, a sense switch 5 for reading out data from the array 3 in accordance with the address values obtained from both the decoders 2, 6, and an output data weight reversing circuit 7 for controlling the reversion of bit weight of data obtained from the switch 5 by a weight inversion signal S and outputting the controlled data to a data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory integrated circuit, and more particularly to a memory integrated circuit suitable for a processing device using a plurality of different processors.

[0002]

2. Description of the Related Art When a plurality of different processors are used for image processing, the data format depends on the processor.
SB (Least Significant Bit)
First thing and MSB (Most Signifi
There is a cant bit) first type, and it is necessary to invert the bit weight when necessary when exchanging data. In the conventional memory integrated circuit, when inverting the bit weight, as shown in FIG. 3, a weight inverting circuit for inverting the weight of input / output data based on the weight inversion signal S is provided outside the memory integrated circuit 12. 11 were equipped. (1) When writing data: The weight inversion circuit 11 sets the data output direction to the memory integrated circuit 12 side based on the direction control signal DIR. ． The weight inversion circuit 11 selects whether or not to invert the data weight based on the weight inversion signal S. Here, when the weight inversion signal S is an inversion instruction, the weight inversion circuit 11 inverts the input data I / O1 to I / O8 and outputs it to the memory integrated circuit 12. On the other hand, when the weight inversion signal S is a non-inversion instruction, the weight inversion circuit 11 outputs the input data I / O1 to I / O8 to the memory integrated circuit 12 without inverting them. ． The memory integrated circuit 12 writes the input data from the weight inverting circuit 11. (2) When reading data :. The weight inverting circuit 11 sets the data output direction to the external data bus side based on the direction control signal DIR. ． The weight inversion circuit 11 selects whether or not to invert the data weight based on the weight inversion signal S. Here, when the weight inversion signal S is an inversion instruction, the weight inversion circuit 11 inverts the output signal from the memory integrated circuit 12 and outputs it as data I / O1 to I / O8 to the external data bus. On the other hand, when the weight inversion signal S is a non-inversion instruction,
The weight inverting circuit 11 outputs the output signal from the memory integrated circuit 12 to the external data bus as data I / O1 to I / O8 without inverting it.

[0003]

However, in the above-mentioned conventional example, since the weight inversion circuit for bit weight inversion control is externally attached, the circuit is complicated and the number of parts is large, so that power saving and There is an inconvenience that miniaturization is difficult.

[0004]

SUMMARY OF THE INVENTION The object of the present invention is to improve the disadvantages of the prior art, and in particular, in a processing device using a plurality of different processors, to convert the output data into a data format corresponding to each processor used. Another object of the present invention is to provide a memory integrated circuit having a weight inversion control means.

[0005]

Therefore, in the present invention, a memory cell array for storing data, a first address buffer for inputting a row address value, and a row address value from the first address buffer are decoded. A row decoder, a second address buffer for inputting a column address value, a column decoder for decoding a column address value from this second address buffer, and a data array from the memory cell array according to the address values from the row decoder and the column decoder. And a sense switch for reading. Then, an output data weight reversal circuit for controlling the weight reversal of the bits of the data from the sense switch by the weight reversal signal inputted from the outside and outputting it to the data bus is adopted. This is intended to achieve the above-mentioned object.

[0006]

The row address value of the read address values is input to the first address buffer, and the column address value is input to the second address buffer. CS (Chip
Select: Chip selection signal) and OE (Output)
t Enable (read signal) becomes “low level”, the row address value stored in the first address buffer is sent to the row decoder and decoded, while the column address value stored in the second address buffer becomes , Sent to the column decoder and decoded. The sense switch selects a memory cell to be read in the memory cell array according to the read address value from the row decoder and the column decoder, and reads data from the memory cell. The data read from the memory cell array is output to the output data weight inverting circuit via the sense switch. The output data weight inversion circuit inverts the weight of the data from the sense switch and outputs it to the data bus if the weight inversion signal is an inversion instruction. On the other hand, if the weight inversion signal is a non-inversion instruction, the output data weight inversion circuit outputs the data weight from the sense switch to the data bus without inverting it.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In the first embodiment, as shown in FIG. 1, a memory cell array 3 for storing data,
A first address buffer 1 for inputting a row address value AR, a row decoder 2 for decoding a row address value AR from the first address buffer 1, a second address buffer 8 for inputting a column address value AC, A column decoder 6 for decoding the column address value AC from the second address buffer 8 and an input / output data bus I / O
Input data control 4 for inputting data on 1 to I / O8 and input data from the input data control 4 according to the address values from the row decoder 2 and the column decoder 6 are stored in the memory cell array 3 and at the same time from the memory cell array 3 The sense switch 5 for reading data and the weight inversion signal S are used to control the weight inversion of the bits of the data from the sense switch 5 to control the input / output data bus I.
/ O1 to I / O8. Here, the first address buffer 1
Is CS (Chip Select: Chip selection signal)
Goes to "low level", the row address value AR on the address bus is taken in. Input data control 4 is C
S (Chip Select: Chip Select Signal) and WE
When both (Write Enable: write signal) become "low level", the input / output data bus I / O1
~ Capture data on I / O8. The output data weight inverting circuit 7 has a CS (Chip Select: chip select signal) and an OE (Output Enable: read signal) both at a “low level” and a WE (Wrig.
ht Enable: write signal) is "high level"
Will work. Next, the operation of this embodiment will be described. (1) When writing data: The row address value AR of the write address value is input to the first address buffer 1. The column address value AC of the write address value is input to the second address buffer 8. ． CS (Chip Select: Chip selection signal)
And WE (WrightEnable: write signal) are set to "low level". ． The row address value AR stored in the first address buffer 1 is sent to the row decoder 2 and decoded.
The column address value AC stored in the second address buffer 8 is sent to the column decoder 6 and decoded. ． The input data control 4 is the input / output data bus I
Data on / O1 to I / O8 [a, b, c, d, e, f,
g, h] is taken in and output to the sense switch 5. ． The sense switch 5 inputs the input data [a, b, c, d, e, f, g, h] from the input data control 4.
According to the write address values from the row decoder 2 and the column decoder 6 are written in the memory cells at the corresponding address positions in the memory cell array 3. (2) When reading data: The row address value AR of the read address value is input to the first address buffer 1. The second column address value AC among the read address values
Input to the address buffer 8. ． CS (Chip Select: Chip selection signal)
And OE (Output Enable: read signal) are set to "low level". ． The row address value AR stored in the first address buffer 1 is sent to the row decoder 2 and decoded.
The column address value AC stored in the second address buffer 8 is sent to the column decoder 6 and decoded. ． The sense switch 5 selects a memory cell in the memory cell array 3 to be read according to the read address value from the row decoder 2 and the column decoder 6, and the 8-bit data [a, b, c, d, e from the memory cell is selected. ，
f, g, h] are read. ． Data read from the memory cell array 3 [a,
b, c, d, e, f, g, h] are output to the output data weight inverting circuit 7 via the sense switch 5. ． The output data weight reversing circuit 7 receives the data [a,
b, c, d, e, f, g, h] are inverted and [h,
g, f, e, d, c, b, a] and output to the data buses I / O1 to I / O8, respectively. On the other hand, if the weight inversion signal S is a non-inversion instruction, the output data weight inversion circuit 7 does not invert the weight of the data [a, b, c, d, e, f, g, h] from the sense switch 5. , And output to the data buses I / O1 to I / O8 as they are. In the second embodiment, as shown in FIG. 2, a memory cell array 3 for storing data and a row address value A
A first address buffer 1 for inputting R, a row decoder 2 for decoding a row address value AR from the first address buffer 1, a second address buffer 8 for inputting a column address value AC, a second A column decoder 6 for decoding the column address value AC from the address buffer 8, an input data control 4 for inputting data on the input / output data buses I / O1 to I / O8, an address from the row decoder 2 and the column decoder 6 A sense switch 5 for storing the data from the input data control 4 in the memory cell array 3 according to the value and reading the data from the memory cell array 3, and a weight inversion signal S.
And the division signal W to control the bit weight inversion of the data from the sense switch 5 to control the input / output data buses I / O1 to I / I.
It is composed of an output data division / weight inversion circuit 10 for outputting to / O8. Here, the first address buffer 1
Is CS (Chip Select: Chip selection signal)
Goes to "low level", the row address value AR on the address bus is taken in. Input data control 4 is C
S (Chip Select: Chip Select Signal) and WE
When both (Write Enable: write signal) become "low level", the input / output data bus I / O1
~ Capture data on I / O8. The output data division / weight inversion circuit 10 includes a CS (Chip Select: chip select signal) and an OE (Output Enable).
Both read signals are "low level" and WE
It operates when (Write Enable: write signal) becomes “high level”. Next, the operation of this embodiment will be described. (1) When writing data: The row address value AR of the write address value is input to the first address buffer 1. The column address value AC of the write address value is input to the second address buffer 8. ． CS (Chip Select: Chip selection signal)
And WE (WrightEnable: write signal) are set to "low level". ． The row address value AR stored in the first address buffer 1 is sent to the row decoder 2 and decoded.
The column address value AC stored in the second address buffer 8 is sent to the column decoder 6 and decoded. ． The input data control 4 is the input / output data bus I
Data on / O1 to I / O8 [a, b, c, d, e, f,
g, h] is taken in and output to the sense switch 5. ． The sense switch 5 inputs the input data [a, b, c, d, e, f, g, h] from the input data control 4.
According to the write address values from the row decoder 2 and the column decoder 6 are written in the memory cells at the corresponding address positions in the memory cell array 3. (2) When reading data: The row address value AR of the read address value is input to the first address buffer 1. The column address value AC of the read address value is input to the second address buffer 8. ． CS (Chip Select: Chip selection signal)
And OE (Output Enable: read signal) are set to "low level". ． The row address value AR stored in the first address buffer 1 is sent to the row decoder 2 and decoded.
The column address value AC stored in the second address buffer 8 is sent to the column decoder 6 and decoded. ． The sense switch 5 selects a memory cell in the memory cell array 3 to be read according to the read address value from the row decoder 2 and the column decoder 6, and the 8-bit data [a, b, c, d, e from the memory cell is selected. ，
f, g, h] are read. ． Data read from the memory cell array 3 [a,
b, c, d, e, f, g, h] are output to the output data division / weight inversion circuit 10 via the sense switch 5. ． The output data division / weight inversion circuit 10 does not invert the data weight if the weight inversion signal S is selected to be non-inverted, and outputs the data [a, b, c,
d, e, f, g, h] as they are to the data bus I / O 1 ...
Output to I / O8 respectively. If the weight inversion signal S is selected for inversion and the division signal W is selected for division, output data division /
The weight inverting circuit 10 divides the data [a, b, c, d, e, f, g, h] from the sense switch 5 into 4 bits each and inverts the weights, [d, c, b, a, h, g,
data bus I / O1 to
Output to I / O8 respectively. Alternatively, the weight inversion signal S
Is selected for inversion and the division signal W is selected for non-division, the output data division / weight inversion circuit 10 causes the data [a, b, c, d, e,
f, g, h] are not divided and the weights are inverted, [h, g, h
f, e, d, c, b, a] and output to the data buses I / O1 to I / O8, respectively.

[0008]

Since the present invention is constructed and functions as described above, according to the present invention, in a processing device using a plurality of different processors, it is possible to convert output data into a data format corresponding to each processor to be used. The bit weight of output data can be controlled to be inverted without externally attaching a weight inversion circuit for controlling the weight inversion of bits, which simplifies the circuit configuration and reduces the number of parts, and the device It is possible to provide an unprecedented excellent memory integrated circuit which can achieve miniaturization, improvement in reliability and economy.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1 First Address Buffer 2 Row Decoder 3 Memory Cell Array 4 Input Data Control 5 Sense Switch 6 Column Decoder 7 Output Data Weight Inversion Circuit 8 Second Address Buffer 9 Output Data Division / Weight Inversion Circuit S Weight Inversion Signal W Division Signal

Claims (2)

[Claims] 1. A memory cell array for storing data,
A first address buffer for inputting a row address value,
A row decoder for decoding a row address value from the first address buffer, a second address buffer for inputting a column address value, a column decoder for decoding a column address value from the second address buffer, and A row decoder and a sense switch for reading data from the memory cell array in accordance with an address value from the column decoder are provided, and a weight inversion signal externally input controls the bit weight inversion of the data from the sense switch to control the data. A memory integrated circuit having an output data weight inversion circuit for outputting to a bus. 2. A memory cell array for storing data,
A first address buffer for inputting a row address value,
A row decoder for decoding a row address value from the first address buffer, a second address buffer for inputting a column address value, a column decoder for decoding a column address value from the second address buffer, and A sense switch for reading data from the memory cell array according to an address value from the row decoder and the column decoder is provided, and bit weight inversion of the data from the sense switch is performed by a weight inversion signal and a division signal input from the outside. A memory integrated circuit having an output data division / weight inversion circuit for controlling and outputting to a data bus.