JPH06275079A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To attain the read and write operation of plural data where an address continues in one cycle even when the inputted address shows any access start address. CONSTITUTION:This device is provided with an address decoding circuit 2 making a high-order address part an input and making first word line 90 where continuous low-order bit shows the memory cells of 0-1 addresses an output and a word line conversion circuit 30 making a low-order address part a control signal and converting the first word line 90 to second word line 91 showing two pieces of continuous memory cells making the address the head. Then, the device is a semiconductor storage making the second word line 91 the input to a memory cell group 10 where the value of low-order address shows zero address, and making the first word line 90 the input to a memory cell group 11 where the value of the low-order shows one address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of simultaneously reading and writing a plurality of data having consecutive address addresses.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device capable of simultaneously reading and writing a plurality of data has been used as a memory incorporated in a microprocessor or a digital signal processor. An example of a conventional semiconductor memory device will be described below with reference to the drawings.

FIG. 5 shows, as a first conventional example, a structure of a semiconductor memory device having a memory area of 8 words which enables simultaneous reading and writing of 2 words of data from consecutive address addresses.

In FIG. 5, reference numeral 60 denotes an address (add address having a width of 3 bits, which is externally input to the semiconductor memory device.
[2: 0]). Of the address 60, it is the address upper part 61 (add [2: 1]) having a width of 2 bits that is used to select the word of the memory cell group. The memory space of this semiconductor memory device includes a memory cell group 10 in which data having the least significant bit of address 60 is 0, that is, data of even addresses, and data having the least significant bit of address 60 being 1. That is, the memory cells are grouped into two memory cell groups of the memory cell group 11 in which the data of odd addresses are stored. An address decode circuit 2 receives the upper address part 61 and enables one of the four first word lines that are outputs. Reference numeral 50 is an input / output circuit that is an interface with the external circuit for the data 70 output from the memory cell group 10.
Is an input / output circuit which is an interface with the external circuit for the data 71 output from the memory cell group 11.

In the conventional semiconductor memory device configured as described above, when the value of the least significant bit of the address 60 is 0, that is, the value of the address 60 indicates an even address, the address address is continuous by one access. The read and write operations of 2-word data are completed, but address 6
When the value of the least significant bit of 0 is 1, that is, the value of the address 60 indicates an odd address, two accesses are required to complete the read operation and the write operation of the data of two consecutive address addresses. Become. Since the access is divided into two times, it is necessary to increment the address at the time of the second access. In the case of the read operation, the data read at the first time is temporarily held and read at the second time. A means for connecting with the data and outputting only the necessary data is required. Further, in the case of the write operation, it is necessary to have a means for dividing the data given from the outside and writing the divided data into the memory cell twice.

Further, as a second conventional example of a semiconductor memory device having a memory area of 8 words, which allows simultaneous reading and writing of 2 words of data from consecutive address addresses, FIG. 6 shows JP-A-63-308783. Shows the configuration shown in.

In FIG. 6, the memory space is the address 6
A memory cell group 10 in which data of which the value of the least significant bit of 0 is 0, that is, data of even addresses is stored, and a memory of which data in which the value of the least significant bit of address 60 is 1, that is, data of odd address It is grouped into two memory cell groups of the cell group 11. 2 is address 60
Is input and one of the eight first word lines that are outputs
An address decoding circuit that enables a book. 5
Reference numeral 0 is an input / output circuit that is an interface with an external circuit for the data 70 output from the memory cell group 10, and 51 is data 71 output from the memory cell group 11.
Is an input / output circuit that is an interface with an external circuit.

In the conventional semiconductor memory device configured as described above, no matter which access start address the input address indicates, a read or write operation of two words whose address addresses are continuous is performed by one access. Can be completed. However, the address decoding circuit 2 generates two word lines for accessing one memory cell in the order of (even address, odd address) and (odd address, even address). This is
This is a factor that increases the number of transistors in the memory cell.

[0009]

The configuration of the first conventional example has a problem that the access operation may not be completed in one cycle, the processing time becomes long, and the control circuit becomes complicated. .

In the configuration of the second conventional example, the access operation can be completed in one cycle, but since two word lines are supplied per word to the memory cell group, the memory cell itself. The number of transistors increases and the number of word lines increases by one, so that the area of the memory cell group also increases. This also causes a problem of increasing the power consumption of the entire semiconductor memory device.

In view of the above problems, the present invention completes the access operation in one cycle and suppresses the increase of the area, regardless of which access start address the input address indicates.
A semiconductor memory device that suppresses an increase in power consumption is provided.

[0012]

According to the semiconductor memory device of the present invention, 2 ^M effective data can be simultaneously read from consecutive address addresses without depending on the value of an N-bit address input from the outside. In order to enable writing, the address is separated into an upper address part consisting of upper (NM) bits and a lower address part consisting of lower M bits of the N-bit address, and the upper address part is input. And an address decode circuit which outputs a first word line indicating a memory cell whose consecutive lower M bits are from 0 to (2 ^M −1) and a first word line which is an output of the address decode circuit. A word line for converting the lower address portion into a second word line indicating 2 ^M memory cells continuous with the address of the N-bit address as a control signal A conversion circuit; and a memory cell group obtained by dividing the memory space represented by an N-bit address by 2 ^M for each memory cell having an address having the same value of the lower M bits of the lower address part. Of the memory cells whose lower address value is from 0 to (2 ^M −2), the second word line output from the word conversion circuit is input, and the lower address value of the memory cell group is The memory cell indicated by the address (2 ^M -1) has a configuration in which the first word line which is the output of the address decoding circuit is input.

According to the semiconductor memory device of the present invention, in addition to the above configuration, effective data output from a plurality of memory cell groups are rearranged in an order suitable for an external bus, and a plurality of data input from the external bus are rearranged. It has a configuration of having an alignment circuit for rearranging the data of 1) in an order suitable for the memory cell group.

[0014]

According to the present invention, with the above-described structure, the address decoding circuit has the first address corresponding to the value of the input upper address part.
Enable the word line of. The word line conversion circuit which receives the first word line as an input enables the second word line which is the word line to be actually accessed according to the value of the lower address part. As a result, it is possible to read and write a plurality of data whose address addresses are continuous in one cycle regardless of which access start address the input address indicates.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor memory device of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a semiconductor memory device of the present invention, which has a memory space of 2 ^N words and is capable of simultaneously reading and writing 2 ^M words of data having consecutive address addresses. Here is an example.

In FIG. 1, reference numeral 60 denotes an address (add) having an N-bit width which is externally input to the semiconductor memory device.
[(N-1): 0]). The address 60 is used to control the present semiconductor memory device together with an address upper part 61 (add [(NM): M]) having a width of (N−M) bits used to select a word of a memory cell group. It is composed of an address lower part 62 (add [(M-1): 0]) having a width of M bits to be used.
The memory space of the present semiconductor memory device includes an address lower part 62.
Memory cell group 10 in which data having a value of 0 is stored
And a memory cell group 11 in which data having a value of 1 in the lower address section 62 is stored, and a memory cell group 1 in which data having a value of (2 ^M −1) in the lower address section 62 is stored.
The memory cells are grouped into 2 ^M memory cell groups of [2 ^M -1]. An address decode circuit 2 receives the upper address part 61 as an input and enables one of the output 2 ^(NM) first word lines 90.

When the value of the address lower part 62 is 0, 30 is the first address enabled by the address decoding circuit 2.
The word line 90 of is directly output to the memory cell group 10,
When the value of the address lower part 62 is other than 0, the first word line 90 enabled by the address decoding circuit 2
Is switched to the second word line 91 at the address +2 ^M and is output to the memory cell group 10. 31 indicates the first word line 90 enabled by the address decoding circuit 2 when the value of the address lower part 62 is 0 or 1.
Is output to the memory cell group 11 as it is, and when the value of the address lower part 62 is other than 0 and 1, the first word line 90 enabled by the address decoding circuit 2 is set to +2 ^M.
Switching to the second word line 91 of the address, the memory cell group 11
Is a word line conversion circuit for outputting to. Similarly, 3 [2 ^M-
2], when the value of the address lower part 62 is 0 to (2 ^M −2), the first word line 90 enabled by the address decoding circuit 2 is used as it is for the memory cell group 1 [2 ^M −
2] and the value of the lower address section 62 changes from 0 to (2 ^M
In cases other than -2), the first word line 90 enabled by the address decoding circuit 2 is switched to the second word line 91 at the address +2 ^M and is output to the memory cell group 1 [2 ^M -2]. It is a word line conversion circuit. Reference numeral 4 designates data obtained by rearranging data 70 to 7 [2 ^M -1] read from the memory cell groups 10 to 1 [2 ^M -1] in ascending order using the address lower part 62 during the read operation. 5 [2
And outputs the ^M -1], and the data in the write operation rearranged in the order of the memory cells to which data is to be written supplied from the output circuit 50~5 [2 ^M -1] using the address lower portion 62 70-7 [2 ^M -1] is the memory cell group 1
It is an alignment circuit that outputs 0 to 1 [2 ^M -1]. Reference numerals 50 to 5 [2 ^M -1] are input / output circuits which are interfaces between the semiconductor memory device and external circuits.

This semiconductor memory device is constituted by the above functional blocks. As a more detailed embodiment, based on FIG. 1, FIG. 2 shows an example of a semiconductor memory device capable of simultaneously reading data of 2 words having a memory space of 8 words and continuous address addresses.

In FIG. 2, reference numeral 60 denotes an address (add) having a width of 3 bits which is externally input to the semiconductor memory device.
[2: 0]). The address 60 is composed of an address upper part 61 (add [2: 1]) having a width of 2 bits used for selecting a word of a memory cell group and a 1-bit address used for controlling the semiconductor memory device. Address lower part 6 with width
2 (add [0]). The memory space of the semiconductor memory device includes a memory cell group 10 in which data having a value of 0 in the lower address section 62, that is, data of an even number address, and a data group having a value of 1 in the lower address section 62, that is, an odd address. It is grouped into two memory cell groups of the memory cell group 11 for storing data. An address decode circuit 2 receives the upper address part 61 and enables one of the four first word lines 90 that are outputs. When the value of the lower address part 62 is 0, 30 outputs the first word line 90 enabled by the address decoding circuit 2 to the memory cell group 10 as it is, and when the value of the lower address part 62 is 1, Is the first word line 90 enabled by the address decoding circuit 2.
Is switched to the second word line 91 at the +2 address and is output to the memory cell group 10. Reference numeral 4 is an alignment circuit that outputs data 70, 71 read from the memory cell groups 10, 11 in ascending order using the address lower part 62 to the input / output circuits 50, 51 during a read operation. Reference numeral 50 is an input / output circuit which is an interface with the external circuit for the data having a smaller address address from the alignment circuit 4, and 51 is an interface with the external circuit for the data having a larger address address from the alignment circuit 4.

This semiconductor memory device is constituted by the above functional blocks. The operation of the semiconductor memory device of this embodiment described above will be described below with reference to FIGS. 3 and 4.

First, the case where the input address 60 is an even address will be described. FIG. 3 shows an example of the read operation when the value of the address 60 is 010. The value of the address upper part 61 is 01
Therefore, the address decoding circuit 2 enables the word line indicating add [2: 1] = 01 in the first word line 90. The first word line 90 becomes a word line for accessing the address 011 to the memory cell group 11, and reads the data stored at the address 011 of the memory cell group 11. At the same time, the first word line 90 is input to the word line conversion circuit 30. Since the value of the address lower part 62 is 0, the word line conversion circuit 30 outputs the input first word line 90 as it is to the memory cell group 10 as the second word line 91. The second word line 91 reads the data stored at the address 010 of the memory cell group 10. Data 70 read from the memory cell group 10
And the data 71 read from the memory cell group 11 are input to the alignment circuit 4, and the data 70 having the smaller address address is output to the input / output circuit 50 according to the value of the address lower part 62, and the data having the larger address address is output. Data 7
1 is output to the input / output circuit 51.

Next, the case where the input address 60 is an odd address is shown. FIG. 4 shows an example of the read operation when the value of the address 60 is 011. The value of the address upper part 61 is 01
Therefore, the address decoding circuit 2 enables the word line indicating add [2: 1] = 01 in the first word line 90. The first word line 90 becomes a word line for accessing the address 011 to the memory cell group 11, and reads the data stored at the address 011 of the memory cell group 11. At the same time, the first word line 90 is input to the word line conversion circuit 30. Since the value of the address lower part 62 is 1, the word line conversion circuit 30 outputs to the memory cell group 10 as the second word line 91 indicating the address obtained by adding +2 to the address address of the input first word line 90. To do.
The second word line 91 reads the data stored at the address 100 of the memory cell group 10. Memory cell group 1
The data 70 read from 0 and the data 71 read from the memory cell group 11 are input to the alignment circuit 4, and the data 71 having the smaller address according to the value of the address lower part 62 is input to the input / output circuit 50. The data 70 having the larger address is output to the input / output circuit 51.

The same applies to the case of the data write operation. External data 80, 81 is input / output circuit 5
0 and 51 are input, and in the alignment circuit 4, according to the value of the address lower part 62, the data of the even address is aligned to the memory cell group 10 and the data of the odd address is aligned to be output to the memory cell group 11. Therefore, the write operation can be completed in one cycle.

As described above, according to the present embodiment, no matter what access start address the input address indicates,
It is possible to read and write a plurality of data having consecutive address addresses in one cycle, and it is possible to suppress an increase in the area of the memory cell region and suppress an increase in power consumption.

[0025]

As described above, according to the present invention, an address is divided into a high-order (NM) high-order address part and a low-order M-bit low-order address part of the N-bit address. The lower M bits that continue as an input are 0
An address decode circuit that outputs a first word line indicating a memory cell from the address to (2 ^M -1), and a first word line that is the output of the address decode circuit using the lower address section as a control signal. A word line conversion circuit that converts the address of the N-bit address into a second word line indicating 2 ^M memory cells that are continuous and a memory space represented by an N-bit address that is lower than the lower M bits. A memory cell having a memory cell group divided by 2 ^M for each memory cell at an address having the same value in the address portion, and showing the value of the lower address from 0 to (2 ^M −2) in the memory cell group. Receives the second word line which is the output of the word conversion circuit as an input, and the memory cell in which the value of the lower address in the memory cell group is (2 ^M -1) is the address Using the first word line, which is the output of the code circuit, as input, the valid data output from the plurality of memory cell groups are rearranged in an order suitable for the external bus, and the plurality of data input from the external bus are sorted. By providing an alignment circuit that rearranges the data in an order suitable for the memory cell group, no matter which access start address the input address indicates, a plurality of data read and write operations in which the address addresses are continuous in one cycle It is possible to suppress the increase in the area of the memory cell region and the increase in power consumption.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a semiconductor memory device of the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram in the case of an even address input according to the embodiment.

FIG. 4 is an operation explanatory diagram in the case of odd address input in the embodiment.

FIG. 5 is a schematic view of a semiconductor memory device showing a first conventional example.

FIG. 6 is a schematic diagram of a semiconductor memory device showing a second conventional example.

[Explanation of symbols]

10-1 (2 ^M -1) memory cell group 2 address decoding circuit 30-3 (2 ^M -2) word line conversion circuit 4 alignment circuit 50-5 (2 ^M -1) input / output circuit 60-62 address 70- 7 (2 ^M −1) data 80 to 8 (2 ^M −1) input / output data 90 to 91 word line

Claims (2)

[Claims] 1. An N-bit address input from the outside is separated into a high-order (NM) high-order address part and a low-order M-bit low-order address part of the N-bit address. An address decode circuit that outputs a first word line indicating a memory cell whose addresses are consecutive lower M bits from 0 to (2 ^M -1), and a first word line that is an output of the address decode circuit. With the lower address part as a control signal, and a word line conversion circuit for converting into a second word line showing 2 ^M consecutive memory cells starting from the address of the N-bit address, and expressed by an N-bit address. A memory cell group obtained by dividing the memory space by 2 ^{M for} each memory cell at an address having the same value of the lower address part of the lower M bits. The second word line which is the output of the word conversion circuit is input to the memory cell group in which the value of the address is from 0 to ( ^2M- 2), and the value of the lower address in the memory cell group is input. Is (2 ^M −
1) A semiconductor memory device characterized in that a first word line which is an output of the address decoding circuit is inputted to a memory cell group indicating an address. 2. The method according to claim 1, wherein the valid data output from the plurality of memory cell groups are rearranged in an order suitable for the external bus, and the plurality of data input from the external bus are stored in the memory. A semiconductor memory device having an alignment circuit that rearranges cells in a suitable order.