JPH0661870A - Variable length coder decoder - Google Patents

Abstract

PURPOSE:To reduce the memory capacity by grouping a variable length code group while taking notice of a consecutive number of bits and using plural memories for each group to form a decoding table. CONSTITUTION:High-order 8-bits of an address input 9 are inputted to a chip select signal generating circuit 10. Simultaneously the input 9 is connected respectively to the address of semiconductor memories 1-8 forming a decoding table. In this case, the addresses of each memory are connected so that bits less than the code length bits required for group recognition are most significant bits for the memories. The circuit 10 discriminates 0s included in an input signal sequentially from the MSB of the input signal 9. Then one of chip select signals 11-18 is inputted to one chip select in semiconductor memories 1-8. Thus, the variable length code is inputted as the address to obtain a prescribed decoding result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoder, and more particularly to reduction of memory capacity when the variable length code decoding table is constructed using a semiconductor memory.

[0002]

2. Description of the Related Art As one of the methods for decoding a variable length code group,
There is a so-called table lookup method in which a variable-length code table is configured by a semiconductor memory and the decoding result stored in the variable-length code decoding table is read according to input data. FIG. 10 is a block diagram of a variable length code decoder having a variable length code decoding table using a conventional semiconductor memory. In the figure, 200 is a memory having an address space with a bit width equal to or larger than the bit width of the maximum code length of the variable length code group.

This table uses variable length codes at address 9
When input as, the decoding result is obtained. Now, each variable-length code serving as an input address is considered as an equal-length code having a length equal to the maximum code length of the codes included in the variable-length code group. When there is a code with a code length less than the maximum code length in the upper part of the equal-length input address, the decoding result corresponding to the upper variable-length code is obtained regardless of any pattern in the lower part. There is. For example, in a variable-length code having a maximum code length of 16 bits and a 6-bit variable length code, even if the upper 6 bits of the input address 16 bits are valid and the lower 10 bits are any value,
It is configured so that the decoding result of the variable length code of the upper 6-bit length can be obtained. That is, the same decoding result is written in advance for all addresses that can be expressed by the lower 10 bits, and the same result can be obtained no matter which address is input.

As described above, the conventional variable-length code decoding table considers the variable-length code as an input address to be an equal-length code of the maximum code length of the codes included in the variable-length code group. Equivalent to the bit width of the maximum code length of the code included in the variable-length code group as the address space of
Alternatively, a bit width of more than that is required, and when the variable length code decoding table is configured using a semiconductor memory, a memory having the address space is required.

[0005]

The variable length code decoding table of the conventional variable length code decoder is configured as described above, and the number of codes included in the variable length code group is actually the maximum code of the codes. Even if the value is much smaller than the long bit width address space, it is necessary to configure the variable length code decoding table with a memory having a minimum capacity or more necessary for storing the decoding result of each variable length code. However, there is a problem that the area of the memory forming the variable length code decoding table becomes large.

The present invention has been made in order to solve the above problems, and has a variable length code decoding table capable of reducing an extra memory capacity for a variable length code which is less than the maximum code length. The purpose is to obtain a variable length code decoder.

[0007]

Means for Solving the Problems As a result of intensive studies to achieve the above-mentioned object, the inventors of the present invention have found that variable-length codes can be grouped by the number of consecutive 0s or 1s from the beginning. Focusing attention, the present inventors have found that by configuring the variable length code decoding table for each group, it is possible to reduce the memory capacity when the variable length code decoding table is configured.

That is, the variable-length code decoder according to the present invention provides an optimum address space for each variable-length code decoding table in which the variable-length code decoding table is divided into groups according to the number of consecutive identical codes continuing from the head of the variable-length code. The memory to be possessed is allocated, and the variable length code decoding table is constituted by a plurality of memories.

[0009]

According to the present invention, the decoding table is configured by using a plurality of semiconductor memories in which the variable-length code groups are divided into groups and the bit width of the maximum code length included in each group is used as the address space of the equal-length bit width. I decided to do so,
The address space required by the decoding table can be significantly reduced, and the capacity of the semiconductor memory forming the decoding table can be reduced.

[0010]

EXAMPLES Example 1. 1 is a memory block diagram of a variable length code decoding table of a variable length code decoder according to a first embodiment of the present invention. In FIG. 1, reference numeral 100 is a variable length code decoding table, 1 to 8 are semiconductor memories divided into groups according to a rule to be described later, 10 receives an input address 9, and one of the semiconductor memories 1 to 8 is selected according to the information. Chip select signals 11 to 11 for selecting one
18 is a chip select signal generation circuit for outputting 18. The input address 9 is connected to each of the semiconductor memories 1 to 8 so that it can be supplied by a predetermined bit.

FIG. 2 is a diagram showing an example of the configuration of the chip select generation circuit 10 described above. An 11-bit address input 9 is shown.
Among them, the logic is constructed so that the upper 8 bits are received at the terminals A3 to A10 and a predetermined group identification signal corresponding thereto is output.

In FIG. 3, the 11-bit address input 9 is used as a variable length code group, and the input address 9 is divided into eight groups according to the number of consecutive zeros (0) from the beginning of the variable length code group. It is a figure which shows the correspondence of and a group classification. As can be seen from this figure, the input address of the decoding table of each group is performed by using the code of 0 and subsequent ones continuing from the head used for group division.

In this way, the variable length code group (input address 9) is classified into eight groups by paying attention to the number of consecutive zeros (0) continuing from the head thereof, and the above eight semiconductors are grouped into each group. The allocation is decided so that the memories 1 to 8 are used. For example, the semiconductor memory 1 shown in FIG.
3 is assigned to the decoding table of the variable length code of the group classification “1” and the decoding table of the variable length code of the group classification “0” of FIG. Make up.

Next, the operation will be described. The address input 9 has a bit width of 11 bits which is the maximum code length included in the target variable length code group.
The upper 8 bits of are input to the chip select signal generation circuit 10.

At the same time, the address input 9 is connected to the address inputs of the semiconductor memories 1 to 8 forming the decoding table, respectively. At this time, an address is connected to each memory so that the bits after the code length necessary for group recognition become the most significant bit (hereinafter, MSB) of each memory. For example, for the semiconductor memory 4 forming the decoding table of the group classification “000” in FIG. 3, 4 bits or more from the MSB of the input address 9 are connected to the address input of the semiconductor memory 4.

The chip select generation circuit 10 sequentially determines zero (0) contained in the input signal from the MSB of the input signal 9 and outputs the determination result. The truth table at this time is shown in FIG. As shown in FIG. 4, the chip select signals 11 to 1 are generated by the number of zeros continuing from the head of the input address 9.
One of the eight is selected and output. Then, one of the chip select signals 11 to 18 is input to one chip select of the semiconductor memories 1 to 8 forming the corresponding decoding table.

As a result, of the semiconductor memories 1 to 8 forming the decoding table, only one memory having the decoding table of the input variable length code is selected. That is, the input address 9 is supplied to all of the semiconductor memories 1 to 8 constituting the decoding table, but the address actually accessed is only the memory to which the chip select signal is input. Become. As described above, a variable length code is input as an address and a predetermined decoding result can be obtained.

When the decoding table of the variable length code group shown in FIG. 3 of the present embodiment is constructed by using a single memory as in the conventional example, the maximum code length included in the variable length code group is 11 bits. Therefore, an address space of 2 ¹¹ = 2048 words is required. On the other hand, in this embodiment, the variable-length code group is divided into eight groups, and each group has a maximum of 2
⁶ = 64 word address space, so 64 x 8 =
Since the number of words is 512 words, the decoding table can be configured with a 1/4 address space as compared with the conventional example, and the required capacity of the semiconductor memory can be reduced.

As described above, according to this embodiment, the code decoding table is constructed by using the eight semiconductor memories 1 to 8, and the chip select signal generating circuit 11 inputs the 11-bit address input 9 from the beginning to zero. The determination is made by focusing on the number of (0), and the only select signal corresponding to the determined group classification is output to the corresponding semiconductor memory,
Since the semiconductor memory is configured to be accessible, an address space having a maximum bit width of a bit pattern after the code length necessary for recognizing the group classification is obtained, and an address space required by one decoding table is obtained. Therefore, the capacity of the semiconductor memory required for constructing the decoding table can be reduced.

Example 2. In the above embodiment, the variable length decoding tables are divided into groups based on the number of consecutive zeros (0) continuing from the head of the variable length code group, and the semiconductor memories having the optimum address spaces are assigned respectively. Then, the variable length code group is continued from the beginning 1
The variable length decoding tables are grouped according to the number of. That is, in FIG. 5, the 11-bit address input 9 is used as a variable length code group, and 1
It is a figure which shows the correspondence of the variable-length code and group classification when the input address 9 is divided into eight groups according to the continuous number of. The input address of the decoding table of each group is performed by using the code of 1 and subsequent ones continuing from the head used for the group division.

When the variable length code decoding table is divided by such a method, the configuration shown in FIG. 1 is basically used, but the chip select generation circuit 10 is replaced with the chip select circuit 10a shown in FIG. Can be realized by using. By doing so, the same effect as that of the above-described embodiment can be obtained.

Example 3. Next, the memory configuration of the variable length code decoding table according to the third embodiment of the present invention will be described with reference to FIGS.
Will be explained. In this embodiment, an input address 9 which is an 11-bit variable length code group is input to eight divided semiconductor memories 1 to 8 via a selector. In the figure, 19 is a selector, and 11
The bit input address 9 and the chip select signals 11 to 18 are input. 8 is a detailed configuration diagram of the selector 19. The selector 19 is based on a shift amount determining circuit 21 that receives the chip select signals 11 to 18 and determines a shift amount, and an output of the shift amount determining circuit 21. Input address 9
, And a shifter 20 for outputting a bit pattern having a code length after the code length required for recognition of the group classification.

Next, the operation will be described. Similar to each of the above-described embodiments, the upper 8 bits of the address input 9 are input to the chip select signal generation circuit 10. At the same time, all bits of the address input 9 are also input to the selector 19. In the chip select signal generation circuit 10, the input address 9 is
The determination is made by paying attention to the number of zeros (0) or 1s continuing from the head, and the only select signal corresponding to the determined group classification is input to the semiconductor memories 1 to 8 forming the corresponding decoding table. With selector 1
It also outputs to 9.

In the selector 19, the input chip select signals 11 to 18 are received, and the shift amount determining circuit 21 discriminates how many high-order bits of the input address 9 are consecutive 0s or 1s. The shift amount for outputting the bits after 0 or 1 in succession as the MSB is calculated, and the result is output to the shifter 20.
Upon receiving this information, the shifter 20 performs a shift operation so that the lower bits of the input address 9 that are obtained by discarding the predetermined upper bits necessary for group recognition are output, and this is used as a decoding table address for each of the semiconductor memories 1 to 8. Output to. This decoding table address is supplied to each of the semiconductor memories 1 to 8 in the same manner, but the only memory actually accessed is the one memory to which only one chip select signal is input. With this configuration, the same effect as that of the above-described embodiment can be obtained.

Example 4. In the above-described embodiment, the input address 9 is divided into groups by the number of consecutive 0s or 1s, but as shown in FIG. 9, the chip select generation circuit 10b provided with the switch circuit 22 is used to continue the division from the head. Any variable length code that can be divided into groups of 0 or 1 can be used.

As described above, by using the memory configuration in which the variable length code group is divided into groups and the decoding table is provided for each group, for example, in an LSI having a relatively small internal memory such as a digital signal processor. A decoding table can be built in and built in, and access to an external device is not required.
The degree of integration can be improved.

[0027]

As described above, according to the variable-length code decoder according to the present invention, the variable-length code group is set to 0 from the beginning.
Alternatively, since the variable length code decoding table is configured by using a plurality of semiconductor memories corresponding to each group while paying attention to the number of consecutive 1's, the variable in the group after the grouping is changed. In order to identify the long code, it suffices to focus only on the pattern of 0 or 1 and subsequent ones from the beginning. When configuring the decoding table in each group, the address space is set to the variable length code of each group. Among them, the pattern of 0 or 1 following from the beginning can have the longest bit width, and the address space can be significantly reduced. As a result, it is necessary when configuring the variable length code decoding table. It is possible to reduce the memory capacity and the cost for configuring the variable length code decoder and the area occupied by the memory for the variable length code decoding table. There is an effect that can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a variable length code decoder according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a chip select signal generation circuit of the variable length code decoder.

FIG. 3 is a diagram showing a group configuration when the variable length code group of the variable length code decoder is divided into groups by the number of 0s continuing from the head.

FIG. 4 is a diagram showing a truth table of the chip select signal generation circuit.

FIG. 5 is a diagram showing a group configuration when the variable-length code decoder according to the second embodiment of the present invention is used to divide a variable-length code group of the variable-length code decoder into groups of 1 from the beginning.

FIG. 6 is a configuration diagram of a chip select signal generation circuit used in the above embodiment.

FIG. 7 is a block diagram of a variable length code decoder according to a third embodiment of the present invention.

FIG. 8 is a detailed configuration diagram of the selector of the above embodiment.

FIG. 9 is a configuration diagram of a chip select signal generation circuit of a variable length code decoder according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional variable length code decoder.

[Explanation of symbols]

 1-8 Semiconductor memory 9 Input address 10, 10a, 10b Chip select signal generation circuit 11-18 Chip select signal 19 Selector 20 Shifter 21 Shift amount determination circuit 22 Switch circuit 100, 101 Variable length code decoder

Claims (5)

[Claims] 1. A variable-length code decoder having a variable-length code decoding table configured by using a semiconductor memory, and decoding a variable-length code group by a table lookup method using the variable-length code decoding table, The variable length code decoding table is provided corresponding to each group that is divided into groups according to the number of consecutive same codes continuing from the head of the variable length code group, and from the consecutive same codes of the variable length codes of the group. Depending on the number of consecutive consecutive same-codes from the beginning of the input variable-length code above, the table space stores the decoding result information in the memory space whose bits are bits other than the upper common bits. It has a memory selection means for selecting the only table memory corresponding to the table memory from the plurality of table memories, The variable length code decoder, wherein the output from the table memory groups corresponding to the long code, it is an decoding result corresponding to the input variable length code. 2. The variable-length code decoder according to claim 1, wherein a plurality of table memories forming the variable-length code decoding table are grouped into the table memories from the input variable-length codes. A variable-length code decoder, characterized in that the upper bits corresponding to the memory space of the table memory, other than the upper common bits used, are connected. 3. The variable-length code decoder according to claim 1, which corresponds to the size of each memory space included in a plurality of table memories constituting the variable-length code decoding table, which receives the output of the memory selection means. , Variable-length code shift means for shifting the bits of the variable-length code to be input so that bits other than the upper common bits can be obtained, and the shift means output is connected to each of the table memories. A variable length code decoder characterized by the above. 4. The variable length code decoder according to claim 1, wherein the variable length code decoding table is divided into groups according to the number of consecutive 0s or 1s from the head of the code of the variable length code group. A variable-length code decoder characterized in that it is provided correspondingly. 5. The variable-length code decoder according to claim 4, wherein the memory selection means starts from the head of the code of the variable-length code group and continues from 0 or from the head of the code of the variable-length code group. A variable-length code decoder having a mode changeover switch for selecting the only table memory according to any one of the number of consecutive 1's.