JPS58146081A - Memory input-output circuit - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a memory, by providing a circuit which makes only a specific bit effective among bit selecting signals, a bit position selecting circuit which selects the bit position of the output from the circuit mentioned above on a data bus, and a code bit extending circuit. CONSTITUTION:In ordinary memory accessing, a bit select signal 21 makes all bits effective, but bit selecting signals which make only lower rank bits (b), intermediate rank bits (c), or higher rank bits (d) effective also exist. In accordance with the bit selecting signal 21, effective bits are fetched from a bit selecting circuit 22 and a bit position selecting circuit 24, and outputted onto a data bus 14. In this way, accessing in which one word of the data memory is divided into parts >=2 is performed and, therefore, the memory is effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output circuit for a data memory in an arithmetic processing device controlled by a microprogram.

In a digital processing device controlled by a microprogram, the number of bits of the data bus is determined by the required operational precision.The number of bits of one word of the normal data memory is also adjusted to the above number of bits.

However, in many cases, many types of data are handled, and in that case, the number of bits required to represent the data is not the same. Conventionally, a memory input/output circuit has an address signal 11, a data memory 12, and , data input/output gate 1
3. It consists of a data bus 14.

Data memory 12 selected by address signal 11
The data, each word of which consists of N bits, is input/output to and from the N-bit data bus 14 through the data input/output gate 13. Since one word is always taken per data, (
If we store t words of data that can be expressed sufficiently with N/2) bits, a data memory with a capacity of NXt bits is used, but the actual data has a meaning of (N/2)Xt bits. Therefore, if the number of bits per word of the data memory is fixed, unnecessary bits may be used depending on the data, resulting in poor memory usage efficiency.

The purpose of the present invention is to eliminate this drawback and provide a memory input/output circuit that can effectively utilize memory and handle more data with the same capacity. The memory input/output circuit of the present invention has the following features:
It includes a circuit that enables only a specific bit from a bit selection signal, a bit position selection circuit and a sign bit extension circuit that select the bit position of the output from the circuit on the data bus, and one word of the data memory is divided into two. Figure 2 is a block diagram showing an embodiment of the present invention, in which the bit selection circuit z2, bit position The relationship between the selection circuit 24 and the sign bit extension circuit 23 is shown.

The access to the data memory according to this embodiment will be explained in detail below.
)t:i The position of each bit on the data memory bus 25, the bit position selection circuit 24, and the sign bit extension circuit 23
This is a diagram showing four examples of correspondence with the positions on the data bus 14 via the O. The shaded area indicates the bit that has been selected by the bit selection circuit 22 and is enabled, and the area indicated by S is FIG. 5 is a concrete block diagram of the bit selection circuit 22, showing the portion outputted to the data bus by the sign bit extension circuit 23 during reading. The decoder circuit 103 inputting the two bit selection signals 10L102 selectively selects the corresponding bit group selection signals 130 to 133 to 10
The bit group selection signals 130 to 133 are passed through the circuits 104 to 106 to the bit selection signal 101゜1.
The bit group valid signals 107 to 108 corresponding to 02 are selectively set to ``0'' to enable the corresponding memory pit group. For example, in the case of FIG. 3 (II), the bit group valid signals 107 to 109 are all set to ``0'', and in the case of Φ) in the same figure, only the lower bit group valid signal 109 of the memory is set to ``0''. FIG. 6 is a concrete block diagram of the bit position selection circuit 24 and sign bit extension circuit 23 shown in FIG. For example, in the case of FIG. 3(a), Φ), data 1 of the lower bit group of the memory
20, and in the case of FIG. 3C, the data 119 of the middle bit group of the memory is output to the lower data bus 126. The data input/output gate circuits 121 and 122 send the data 118 of the upper bit group of the memory to the upper data bus 124 and send the data 119 of the middle bit group of the memory to the middle data bus 124 only in the case of FIG. 3(a). The 0 selector circuit 114 that outputs to the bit selection signal 125 selects the most significant hits 111 to 113 of the pit group of the memory according to the bit selection signals 101 and 102.
The output is input to the output gate circuit 115 via the AND circuit 43, and is output to the intermediate data bus 125 and the upper data bus 124 in cases other than (a) in FIG. be done.

FIG. 3(a) shows the case of normal memory access, where the bit selection signal 21 specifies that all bits are valid.

The bit selection circuit 22 inputting each issue makes all bits of the data memory valid. The bit position selection circuit 24 inputting the signal outputs the data on the data memory node 25 to the data node 14 without changing anything.

The sign bit extension circuit 23 does not output to the data bus. This causes the same data as the data memory bus 25 to be output to the data bus 14. In the case of Figure 3 (b), the bit selection signal 21 is the lower bit. In response to this signal, the bit selection circuit 22 makes only the lower bits valid.The bit position selection circuit 24 selects only the enabled bits of the data memory 12 on the data node (slash 14). The O sign bit extension circuit 23 extends the most significant bit of the enabled lower bits by the remaining bits on the data bus 14 (the part indicated by 8) and outputs it to the data bus 14. 14, the data has the same number of bits as in the case of Iris 3 (a), and the code is also extended, so the same figure (a)
) can be calculated as the same data format as in the case of
The difference between the case of FIG. It is to change. The sign bit extension circuit 23 outputs the most significant bit of the selected middle bits of the data memory onto the data bus 14 as the remaining bits on the data bus 14.
This is the same as in Figure (b). In the case of Fig. 3(d), the same figure (C
), the upper bits on the data memory bus 25 are outputted onto the data bus 14 with the pit position changed and the sign bit extended.

It is also possible to extend the data of uO'' instead of the sign bit and output it on the data bus 14 by using the sign bit extension circuit 23 shown in FIG. By setting ``1'' to ``1'', the extension bit 42 is the same as the sign bit 41, and the sign bit is extended.Also, by setting the code selection signal 26 to ``0'', the extension bit 42 is always set. 0″ is extended to @0#.

During writing, the bit position of the data on the data bus 14 is changed by the bit position selection circuit 24 and output onto the data memory bus 25, contrary to when reading, except that the sign extension circuit 23 does not operate. Other operations are the same as when reading.

In this way, one word at the same address is used as the bit selection signal 2.
◇ As is clear from the above explanation, according to the present invention, it is also possible to access one word of the data memory by dividing it into two or more parts. It is possible to store only the valid part of the data, allowing efficient use of memory, and allowing more data to be stored with the same capacity.

[Brief explanation of the drawing]

The first section is a block diagram of a conventional memory input/output circuit, the second section is a block diagram showing an embodiment of the memory input/output circuit according to the present invention, and the third section is a block diagram showing the position of each bit on the data memory bus and pit position selection. An explanatory diagram showing an example of correspondence with pit positions on a data bus via a circuit and a sign extension circuit,
Figure 4 is a circuit diagram showing the extension bit selection circuit in Figure 2, Figure 5 is a block diagram specifically showing the bit selection circuit in Figure 2, and Figure 6 is the pit position selection circuit in Figure 2 and its symbols. FIG. 2 is a block diagram specifically showing a bit extension circuit. 11...Address signal, 12...Data memory, 13...Data input/output gate, 14
・River...Data bus, 21...Bit selection signal, 22...Bit selection circuit, 23...
Sign bit extension circuit, 24...Pit position selection circuit, 25...Data memory bus, 26...
...Sign selection signal, 41...Sign bit, 4
2...Extension bit, 43...AND gate, 101...Bit selection signal, 102...
. . . Bit selection signal, 103 . . . Decoder circuit, 104. 105, 106...AND circuit, 107...Memory upper bit group valid signal,
108... Memory middle bit group valid signal, 1
09...Memory lower bit group valid signal, 11
1...The most significant bit y of the upper bit group of memory),
112... Most significant bit l- of middle bit group of memory, 113... Most significant bit of lower bit group of memory, 114... Selector circuit, 115
...Output gate circuit, 116...OR
Circuit, 117... Inverter circuit, 118.
...Data of upper bit group of memory, 119...
...Data of middle bit group of memory, 120...
... Data of lower bit group of memory, 121, 122
...Data input/output gate circuit, 123...
... Data selector circuit, 124 ... Upper data bus, 125 - Old ... Middle data bus, 126
......lower data bus, 130...all bit selection signal, 131...upper bit group selection signal, 132...middle bit group selection signal, 13
3 Atsushi l Figures 2 Figures Chicken, 3 Hen Atsushi 4 Figures

Claims (1)

[Claims] A data memory for writing and reading data, and dividing one word on the data memory into two or more parts according to a bit selection signal? a bit selection circuit for selectively accessing; a bit position selection circuit for selecting a bit position on a first data bus of the output of the data memory according to the bit selection signal; and a circuit for extending a sign bit. A memory input/output circuit comprising: