JPH0789439B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to semiconductor integrated circuit device technology and further to EEP-ROM.
(Electrically erasable and writable memory: Also called EA-ROM.) And a digital circuit using this EEP-ROM are applied together to a semiconductor integrated circuit device, which is particularly effective The present invention relates to a technique effectively used for a single-chip type microcomputer equipped with an EEP-ROM, for example.

[Background technology]

For example, a so-called single-chip type microcomputer is typical as a semiconductor integrated circuit device in which a memory and a digital circuit are formed together.

This single-chip type microcomputer is often used, for example, for embedding in equipment, and in the past, many had a built-in non-rewritable ROM, but recently, for example, Nikkei Electronics, published by Nikkei McGraw-Hill, March 30, 1981. As described in No. 80 (Technical Bulletin), a real-time rewritable non-volatile memory as a ROM has been provided. By incorporating such a rewritable non-volatile memory, the user can freely write the system program and fixed storage data of the microcomputer according to the type of controlled device. it can. As a result, it becomes possible to adapt the same type of microcomputer to a wide variety of applications, and while making the most of the effect of mass production of the semiconductor integrated circuit device, it becomes possible to apply it to a wide variety of small amount of equipment.

FIG. 4 shows an example of a microcomputer equipped with an EEP-ROM.

The microcomputer shown in the figure is configured as a single-chip microcomputer, and has a CPU (central processing unit) 1 as a digital circuit.
And EEP- as an electrically erasable and writable memory
Has ROM2. CPU1 and EEP-ROM2 are connected via an address bus L1, a data bus L2, and a control bus L3.

The CPU1 generates the address Ax and the read / write control signal R / W to access the EEP-ROM2, and exchanges data Dx via the data bus L2.

The EEP-ROM 2 includes a memory cell array 21, an address decoder 22,
It has latch circuits A and B, a data selection circuit 23, and the like.

In the memory cell array 21, for example, five memory rows each having 2 bytes (2 × 8 bits) as one word are arranged, and have a memory capacity of 10 bytes (2 bytes × 5 words = 10 bytes) as a whole. D1a, D1b to D5a, D5b indicate storage data of 1 byte each. Stored data D1a, D1b to D5a, D
5b is erased and written in units of 2 bytes (1 word).

Each of the latch circuits A and B holds 1-byte data, and holds 1-word data as a whole. In the latch circuits A and B, the storage data of the portion designated by the upper digit of the address Ax is temporarily held / saved in word units.

The address decoder 22 outputs word selection signals X1 to X5 for selecting any one word data in the memory cell array 21 based on the upper digit of the address Ax. At the same time, a latch selection signal Xo for selecting one of the latch circuits A and B is output based on the lower digit of the address Ax.

The data selection circuit 23 is a kind of switching circuit and is controlled by the latch selection signal Xo.

FIG. 5 shows the above-mentioned microcomputer,
An operation example when rewriting a part of the data stored in EEP-ROM2 is shown.

6 (a), (b) and (c) show changes in the state of the EEP-ROM2 in a stepwise manner when a part of the stored data in the EEP-ROM2 is rewritten.

In FIGS. 5 and 6, for example, when rewriting the 1-byte stored data Da1 in the EEP-ROM2, first, as the first step, the address Ax is given from the CPU1 to the EEP-ROM2. As a result, as shown in FIG. 6 (a), the EEP-ROM2
1 word data (Da1, Dab) including the target storage data Da1 is read from the storage cell array 21 in the latch circuit.
Held and saved in A and B.

Next, as a second stage, at this point, the read / write control signal
Set the R / W to write specification mode. As a result, as shown in FIG. 6B, the held data Da1 of the latch circuit A selected by the data selection circuit 23 of the latch circuits A and B is rewritten to the arbitrary write data Dx. To be

After this, as the third stage, as shown in FIG. 6 (c),
The data held by the latch circuits A and B, Dx and D1b, are stored in the memory cell array 2
Written to the original storage location in 1.

As described above, the arbitrary 1-byte data in the EEP-ROM2 can be designated and rewritten.

However, in the above-mentioned microcomputer,
It has been made clear by the present inventor that the following problems occur when rewriting the stored data in the EEP-ROM 2.

That is, in the above-mentioned microcomputer, EEP-
When rewriting the stored data in the ROM2, (1) read the stored data and hold / save it in the latch circuits A and B, (2) partially rewrite the data held in the latch circuits A and B, (3 ) The above three operations (1) and (2) of writing the data held by the latch circuit to the original storage location
(3) is carried out step by step in a time division manner. Therefore, in order to complete the rewriting of the stored data in the EEP-ROM2, as shown in FIG. 5, the total time t1 and t2 required to execute the operations (1) and (2) ( t1
+ T2) was necessary. And this total time (t1 + t
2) was the apparent access time tac of EEP-ROM2. As described above, rewriting the stored data in the EEP-ROM 2 requires a considerably longer time than reading the stored data. Further, since the write operation is performed after the storage data is once read to the latch circuits A and B, if the above rewriting required time tac is shortened, the time allotted to the write operation is reduced. However, it becomes difficult to secure a sufficient write margin time (write margin).

[Object of the Invention]

An object of the present invention is a semiconductor integrated circuit device having an EEP-ROM built-in, and the time required for rewriting to the EEP-ROM is
It is an object of the present invention to provide a technique capable of shortening while securing a sufficient write margin time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

A typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, when rewriting the stored data in the EEP-ROM,
(1) Read the stored data and hold / save it in the latch circuits A and B. (2) Partially rewrite the data held in the latch circuits A and B. (3) Originally store the data held in the latch circuit. Writing to the position, the above three operations (1)
(2) Among the operations in (3), the operations of (1) and (2) are performed in parallel at the same time, thereby shortening the access time to the EEP-ROM while ensuring a sufficient write margin time. It achieves the purpose of making possible.

〔Example〕

Hereinafter, representative embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a microcomputer to which the present invention is applied.

The microcomputer shown in the figure is basically the same as that described above. That is, the micro
The computer is configured as a single-chip type microcomputer, and has a CPU (central processing unit) 1 as a digital circuit and an EEP-ROM 2 as an electrically erasable and writable memory. The CPU1 and EEP-ROM2 are connected via an address bus L1, a data bus L2, and a control bus L3.

The CPU1 generates the address Ax and the read / write control signal R / W to access the EEP-ROM2, and exchanges data Dx via the data bus L2.

The EEP-ROM 2 includes a memory cell array 21, an address decoder 22,
It has latch circuits A and B, a data selection circuit 23, and the like.

In the memory cell array 21, for example, five memory rows each having 2 bytes (2 × 8 bits) as one word are arranged, and have a memory capacity of 10 bytes (2 bytes × 5 words = 10 bytes) as a whole. D1a, D1b to D5a, D5b indicate storage data of 1 byte each. Stored data D1a, D1b to D5a, D
5b is erased and written in units of 2 bytes (1 word).

Each of the latch circuits A and B holds 1-byte data, and holds 1-word data as a whole. In the latch circuits A and B, the storage data of the portion designated by the upper digit of the address Ax is temporarily held / saved in word units.

The address decoder 22 outputs word selection signals X1 to X5 for selecting any one word data in the memory cell array 21 based on the upper digit of the address Ax. At the same time, a latch selection signal Xo for selecting one of the latch circuits A and B is output based on the lower digit of the address Ax.

The data selection circuit 23 is a kind of switching circuit and is controlled by the latch selection signal Xo.

In addition to the configuration described above, in this embodiment, the EEP-ROM2
In rewriting the above, in the above two latch circuits A and B, only the latch circuit selected by the lower digit of the address Ax is written with data from the outside, and the other non-selected latch circuits are not rewritten in the memory cell 21. The storage data of the portion is configured to be written. Therefore, at the time of rewriting, the selection signal Xo given to the data selection circuit 23 is also given to the latch circuits A and B. As a result, the read / write modes of the latch circuits A and B are individually controlled, and when the stored data is rewritten, the emergency exchange data D1b which is once erased due to the rewriting is read and held in the latch circuit B. The saving operation and the operation of externally writing data to the word circuit holding the write data can be simultaneously performed in parallel with each other.

FIG. 2 shows the above-mentioned microcomputer,
An operation example when rewriting a part of the data stored in EEP-ROM2 is shown.

Further, FIGS. 3 (a) and 3 (b) show changes in the state of the EEP-ROM2 in two stages when rewriting a part of the data stored in the EEP-ROM2.

In FIGS. 2 and 3, for example, when rewriting the 1-byte storage data Da1 in the EEP-ROM2, first of all, as the first step, the address Ax and the write data Dx are sent from the CPU1.
Is given to EEP-ROM2. At the same time, the read / write control signal R / W is set to the write designation mode. Then, as shown in FIG. 3A, the non-rewriting data D1b which is once erased by the rewriting is read and held / saved in the latch circuit B, and the latch circuit A is externally written. The operation of writing the data Dx is performed at the same time.
That is, here, the operations (1) and (2) of the above-described first and second stages are simultaneously performed in parallel.

Therefore, after the first step, the operation corresponding to the operation (3) of the third step can be immediately started. That is, here, in the second stage, as shown in FIG. 3B, the respective holding data Dx and D1b of the latch circuits A and B are written in the original storage positions in the storage cell array 21.

As described above, by performing the write operation from the beginning of the rewrite operation, the arbitrary 1-byte data in the EEP-ROM2 is completed in a short access time (tac = t2). As a result, it becomes possible to shorten the time required for rewriting (tac) to the EEP-ROM 2 while ensuring a sufficient write margin time.

[Effect] (1) When rewriting the stored data in the EEP-ROM,
(1) The stored data is read and held / saved in the latch circuits A and B. (2) The data held in the latch circuits A and B is partially rewritten, (3) The data held in the latch circuit is written to the original storage position, and the above three operations (1)
(2) Among the operations in (3), the operations of (1) and (2) are performed in parallel at the same time, thereby shortening the access time to the EEP-ROM while ensuring a sufficient write margin time. The effect of being able to do is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, above EEP-ROM2
The storage data structure of may be a combination other than 2 bytes and 1 word.

[Field of application]

The case where the invention made by the present inventor is applied to the single-chip type microcomputer which is the field of use as the background has been described above, but the invention is not limited to this, and for example, an arithmetic processor, a communication interface, or the like. It can also be applied to semiconductor integrated circuit devices for peripheral functions.

[Brief description of drawings]

FIG. 1 is a block diagram showing a single-chip type microcomputer incorporating an EEP-ROM to which the present invention is applied, and FIG. 2 is a rewriting operation of an EEP-ROM in a single-chip type microcomputer to which the present invention is applied. FIG. 4 is a timing chart showing an example, and FIGS. 3 (a) and 3 (b) are diagrams showing the states when the single-chip microcomputer to which the present invention is applied perform the rewriting operation of the EEP-ROM in stages. FIG. 6 is a block diagram showing a configuration example of a conventional single-chip microcomputer with built-in EEP-ROM. FIG. 5 is a timing chart showing an example of rewriting operation of EEP-ROM in the conventional single-chip microcomputer. Figures (a), (b), and (c) show the state when the conventional single-chip microcomputer rewrites EEP-ROM. Which is a diagram showing step by step. 1 ... CPU (central processing unit), 2 ... EEP-ROM, 21 ...
... memory cell array, 22 ... address decoder, 23 ... data selection circuit, A, B ... latch circuit, L1 ... address bus, L2 ... data bus, L3 ... restricted bus, Dx ... write data, Ax …… Address.

Claims (1)

[Claims] 1. A non-volatile memory capable of electrically erasing and writing stored data in a unit of data of a plurality of bits, and a non-volatile memory connected to the non-volatile memory, having the same number of bits as the unit of data and individually by an external address. What is claimed is: 1. A semiconductor integrated circuit device, comprising: a plurality of latch circuits that can be selected and deselected; and a digital circuit that rewrites or reads stored data via the latch circuits, wherein the stored data in the nonvolatile memory is rewritten. , The operation of reading and saving stored data in a latch circuit selected by an external address and the operation of externally writing data in a latch circuit not selected by the external address are performed simultaneously in parallel with each other. A characteristic semiconductor integrated circuit device.