JPS6233396A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent an erroneous writing without requiring a timer by controlling a period of an external writing cycle by an external period control signal. CONSTITUTION:When an output of a signal output pin 11 is high level, a write enable signal the inverse of WE falls and then a program control circuit 8 starts an external writing cycle and when the write enable signal the inverse of WE is low level, the program control circuit 8 operates the signal output pin 11 as a signal input pin. Namely, while the write enable signal is low level, when a high level is externally impressed to the signal output pin 11, the program control circuit 8 continues the external writing cycle. When a low level is externally impressed to the signal output pin 11, the program control circuit 8 completes the external writing cycle and moves to an internal writing cycle. Thereby, a timer for controlling a period of the external writing cycle is not required but an erroneous writing resulting therefrom can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an electrically rewritable nonvolatile memory (EEPROM).

[Prior Art] In the above-mentioned EEPROM, it takes several milliseconds to 10 milliseconds to write data into a memory cell.

For this reason, if writing is performed one byte at a time like in static RAM, it will take several tens of seconds to 80 seconds to write all bits in a 64-pit EEPROM with an 8-word x 8-bit configuration. .

Therefore, an EEPR with a density of 64 bits or more
In OM, a so-called page mode write function, which writes several bytes at once, has become standard. For example, if 16 bytes are written at one time as one page, the time required to write on all pips will be 1/16, and the writing will be completed in less than 5 seconds.

FIG. 2 is a block diagram of a writing system of an EEPROM equipped with a page mode writing function. In the figure, a memory cell array 1 has a configuration in which a plurality of unit memory cells are arranged in a matrix along the row and column directions. The a address buffer 2 is connected to an external device (for example, CPtJ
) is used to temporarily store the row address given from ). The output of the O address buffer 2 is applied to the row decoder 3, decoded, and then applied to the memory cell array 1. Column address buffer 4 is for temporarily storing column addresses from an external source (e.g., CPU).Column address buffer 4
The output is applied to a column decoder 5, decoded, and then applied to a column latch 6. A data input buffer 7 is connected to this column latch 6. The data buffer 77 is for temporarily storing data (data to be written to the memory cell array 1) provided externally (for example, cpv).The column latch 6 is used to store data stored in the data buffer 7. Column decoder 5
To. Therefore, it is used to temporarily store the data in the specified byte. The output of column latch 6 is applied to memory cell array 1.

The program control circuit 8 is for controlling the operation of each circuit included in the EEPROM. Connected to this program control circuit 8 are signal input pins 9 and 10 and a signal output pin 11 as signal pins of interest to the present invention. Signal input pin 9 has external (
For example, a chip enable signal CE such as CPU>is input. This chip enable signal CE is EE'PRO
This is a signal for activating M. A write enable signal WE is input to the signal input pin 10 from the outside.

This write enable signal WE is a signal for controlling the write cycle of the EEPROM.

From signal output pin 11, Ready/Busy
(hereinafter abbreviated as R/8) signal is output. This R/
The B signal is a signal for indicating the internal state of the EEFROM, and is given to, for example, an external CPU (not shown).

FIG. 3 is a time chart 1 for explaining the operation of the EEPROM shown in FIG. The operation of the EEPROM shown in FIG. 2 in the page mode will be briefly explained below with reference to FIG. A page mode write operation consists of two cycles: an external write cycle and an internal write cycle. For the first external write cycle, the device (EE
PROM) can be controlled from the outside, and data can be written in it in almost the same way as static RON4.

However, the data written at this time is not actually written into the memory cells, but is merely stored in the column latch 6 provided for each column. At this time, the page address, ie, the row address, must be kept constant.

When the external write cycle ends, the device is disconnected from the external control system, i.e., it no longer accepts external control signals, and an internal write cycle occurs in which the data stored in the column latch 6 is actually written to the memory cell array 1. begins. In this way, since the internal write cycle is performed independently within the device, an external device such as a CPU needs to know the start and end of the internal write cycle in some way. Therefore, the above-mentioned R/B signal is used as a signal to notify the start and end of the internal write cycle.

To explain in more detail, when the chip enable signal CE and the write enable signal WE fall to a low level while the R/8 signal is at a high level, a timer (included in the program control circuit 8) is activated. The external write cycle for page mode writing begins. During this external write cycle, an external address is latched into row address buffer 12 and column address buffer 4 at the later fall of deep enable signal CE and write enable signal WE. Also, is data from outside a data human buffer? It is latched to 7.

Then, the data latched in the data manual buffer 7 is launched into the column latch 6 corresponding to the column address at the earliest rise of the chip enable signal GE and the write enable signal WE. When the output of the above timer goes low level, the R/B signal goes low level,
The external write cycle ends and the internal write cycle begins.

In the internal write cycle, the row address latched in the row address buffer 2 is decoded by the row decoder 3, and one word line is selected. Therefore, the data latched in the column latch 6 is written into the byte of the memory cell array 1 connected to this selected word line.

[Problems to be Solved by the Invention] Since the conventional E[:FROM is configured as described above, the end of the external write cycle cannot be controlled from the outside. Therefore, the chip enable signal G
E, R while the write enable signal WE is at low level.
If the /B signal fell, there was a risk that incorrect data would be latched into the column latch.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that does not require a timer and can prevent erroneous writing.

[Means for Solving the Problems] A semiconductor memory device according to the present invention is such that the period of an external write cycle is controlled by a period control signal from the outside.

[Operation] In the present invention, since the period of the external write cycle is controlled by a period control signal from the outside, the timer of the conventional device is unnecessary, and errors caused by it are prevented.

[Implementation Ili! ] FIG. 1 is a time chart for explaining the operation of an embodiment of the present invention. The general configuration of this embodiment is almost the same as the conventional example shown in FIG. 2, and detailed explanation thereof will be omitted. However, this embodiment does not require a timer for controlling the external write cycle, which was necessary in the conventional example.

Further, the program control circuit 8 has a circuit configuration that performs operations as described below. below,
An embodiment of the present invention will be described with reference also to FIG.

The feature of this embodiment is that the signal output pin 11 shown in FIG. 2 is used as a signal input pin during an external write cycle;
The continuation and termination of an external write cycle is controlled by a signal from an external device (for example, a CPU).

That is, in this embodiment, the period of the external write cycle is controlled by an external signal.

In FIG. 1, when the write enable signal WE falls while the output of the signal output pin 11 is at a high level, the program control circuit 8 starts an external write cycle. In this external write cycle, the program control circuit 8 causes the signal output pin 11 to function as a signal input pin while the write enable signal WE is at a low level.

That is, if a high level is externally applied to the signal output pin 11 while the write enable signal is at a low level, the program control circuit 8 continues the external write cycle. On the other hand, when a low level is applied to the signal output pin 11 from the outside, the program control circuit 8 ends the external write cycle and shifts to an internal write cycle.

Except for the period of the external write cycle, the signal output pin 11 functions as a signal output pin for the R/B signal as in the conventional example.
While the R/B signal is at a low level, it indicates that an internal write cycle is in progress.

In the above embodiment, in the external write cycle, if a high level is applied to the signal output pin 11 during the period when the write enable signal W is at a low level, the external write cycle is continued, and if a low level is applied, the external write cycle is continued. Although the configuration has been described such that the cycle ends in the first cycle, the same effect as in the above embodiment can be obtained even if the cycle is reversed.

[Effects of the Invention] As described above, according to the present invention, the end of the external write cycle of the page mode write operation is controlled by an external signal. There is no need to provide a timer for controlling the period of the write cycle, and the 1!11 write caused by C can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a time chart 1 for explaining the operation of an embodiment of the present invention. FIG. 2 is a block diagram of a writing system of a conventional EEPROM equipped with a page mode writing function. FIG. 3 is a time chart for explaining the operation of the conventional example shown in FIG. In the figure, 1 is a memory cell array, 2 is a row address buffer, 3 is a row decoder, 4 is a column address buffer, 5 is a column decoder, 6 is a column latch, 7 is a data manual buffer, 8 is a program control circuit,
9t3 and 10 are signal input pins, and 11 is a signal output pin. Agent Masuo Oiwa Diagram 2 Procedural Amendment Band (self-motivated) Showa Year Month Day 1, Case Indication Patent Application No. 174604 No. 1988 2,
Name of the invention: Semiconductor storage device 3, Person making the amendment 5, Detailed description of the invention column 6 of the specification subject to amendment, Contents of the amendment (1) “Static ROMJ” on page 5, lines 10-11 of the specification "Static RAM J1.: \J Correct. (2) In the 6th shell of the specification, lines 18-19, "Data from the outside is also latched into the data manual buffer 7."
Delete. (3) From page 6, line 20 to page 7, line 1 of the specification, “
Then, "The data is latched in the manual data buffer 7" is corrected to "It is also input from the outside."that's all

Claims (2)

[Claims] (1) An external write cycle that has an electrically rewritable nonvolatile memory cell array and temporarily stores a predetermined unit of data input from the outside in a latch means, and the data stored in the latch means. and an internal write cycle for collectively writing data into the memory cell array, wherein a period of the external write cycle is controlled by an external period control signal. Device. (2) In a semiconductor memory device equipped with a signal output pin for outputting a signal representing an internal state of the semiconductor memory device, the signal output pin is also used as a signal input pin for inputting the period control signal. A semiconductor memory device according to claim 1, characterized in that: