JPS6140628A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS6140628A JPS6140628A JP16305784A JP16305784A JPS6140628A JP S6140628 A JPS6140628 A JP S6140628A JP 16305784 A JP16305784 A JP 16305784A JP 16305784 A JP16305784 A JP 16305784A JP S6140628 A JPS6140628 A JP S6140628A
- Authority
- JP
- Japan
- Prior art keywords
- ram
- gates
- orxn
- orx0
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の属する技術分野）
本発明はメモリに関し、とくにマイクロコンピュータに
内蔵されている書込み読み出し可能なメモリの初期値設
定回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field to Which the Invention Pertains) The present invention relates to a memory, and particularly to an initial value setting circuit for a writable and readable memory built into a microcomputer.
（従来技術）
書込み読み出し可能なメモリは電源投入時に内容が不定
であり初期設定する必要がある。従来の書き込み読み出
し可能な、メモリ（以下、ＲＡＭという）の初期値設定
動作を第１図を用いて説明する。(Prior Art) The contents of a writable and readable memory are undefined when the power is turned on, and it is necessary to initialize the memory. A conventional initial value setting operation of a readable/writable memory (hereinafter referred to as RAM) will be explained with reference to FIG.
第１図においてＲｘｏｙｏ〜Ｒｘｎｙｎは各々ＲＡＭを
構成する１ビツト記憶素子（１メモリセル）、ＡＤ（１
〜人ＤｆｉはＲＡＭのアドレスを示すアドレス信号、
Ｒ，％Ｒ，は読み出しバッファ、 Ｗｏ％ ｗｎ は青
き込みバッファ、Ｄｏ ”−Ｄ ｎは書き込み及び読み
出しデータである。In FIG. 1, Rxoyo to Rxnyn are 1-bit storage elements (1 memory cell) and AD (1 memory cell) constituting the RAM, respectively.
Dfi is an address signal indicating a RAM address, R, %R, is a read buffer, Wo% wn is a blue write buffer, and Do''-D n is write and read data.
初期設定ではまずアドレス信号ＡＤ、で選択されるＲＡ
ＭのＲｘｏｙｅからＲｘｎｙｅ Ｋ書き込みデータであ
るり、％Ｄ、よ６ハイレベル＠１″ｍあるいはロウレベ
ル１０″が書き込まれる。In the initial settings, RA is selected by the address signal AD.
From Rxoye of M to Rxnye K write data, %D, 6 high level @1''m or low level 10'' is written.
次にアドレス信号人ＤＩで選択されるＲＸｔｊＹｌから
ＲＸｎｙｌが同様に初期設定される。このように順次ア
ドレス信号でＲＡＭを選択しながらＲＡＭに初期値を書
き込みすべてのＲＡＭに＠１”あるいは′″０″′を初
期設定していた。Next, RXtjYl to RXnyl selected by the address signal DI are similarly initialized. In this way, initial values are written to the RAMs while sequentially selecting the RAMs using address signals, and all RAMs are initialized to @1'' or ``0''.
以上のような初期値設定の場合ワードアドレス毎にデー
タを書き込マまければならないので初期設定完了までに
時間がかかるという欠点があった。In the case of initial value setting as described above, data must be written for each word address, so there is a drawback that it takes time to complete the initial setting.
（本発明の目的） ′
本発明の目的は極めて短い時間でＲＡＭの初期値設定を
行うことのできる初期値設定回路を提供。(Object of the present invention) 'An object of the present invention is to provide an initial value setting circuit that can set the initial value of a RAM in an extremely short period of time.
するものである。 。It is something to do. .
（発明の構成） ′
本発明の初期値設定回路はＲＡＭのすべてのワード線を
同時に選択する手段とＲＡＭのすべてのビット線に同時
にデータを与える手段とを含んで構成される。
゛
（実施例の説明）
次に本発明の一実施例について図面を用いて説明する。(Structure of the Invention) The initial value setting circuit of the present invention includes means for simultaneously selecting all word lines of the RAM and means for simultaneously applying data to all bit lines of the RAM.
(Description of Embodiment) Next, an embodiment of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例のブロック図である。FIG. 2 is a block diagram of one embodiment of the present invention.
通ｔマイタ日コンピスータは電源投入後ＲＥＳＥＴ信号
によりＣＰＵ及びその他の回路の初期値設定を行ってい
るので本実施例ではＲＥＳＥＴ信号をＲＡＭの初期設定
のための制御信号として用いる。Since the computer uses the RESET signal to set the initial values of the CPU and other circuits after the power is turned on, this embodiment uses the RESET signal as a control signal for initializing the RAM.
第２図でＯＲｙ ｏ〜０Ｒｙｎｅ ＯＲｘｍ〜０Ｒｘ
ｎ はＯＲゲートであり、その他第１図と同じ記号で示
されたものは同一機能である。まずＲｇ８ＥＴ信号をハ
イレベル′″１″にするとｏｕｙ、〜０Ｒｙｎ 。In Figure 2, ORy o~0Ryne ORxm~0Rx
n is an OR gate, and other elements shown with the same symbols as in FIG. 1 have the same functions. First, when the Rg8ET signal is set to high level ``1'', ouy, ~0Ryn.
ＯＲゲート出力が同時に′１″になりすべてのＲＡＭセ
ルのワード線を同時に選択する。またＲＥ８ＥＴ信号を
＠ １１１にすると、ビットｌｉＫ接続され九０ Ｒｘ
ｏ〜０Ｒｘｎの出力がすべて同時に′″１″になるた
めすべてのＲＡＭセルに同時に″１″が書き込まれ、初
期値＠１＠ですべてのＲＡＭは初期設定される。The OR gate output becomes '1' at the same time and selects the word lines of all RAM cells at the same time. Also, when the RE8ET signal is set to @111, the bit liK is connected and 90 Rx
Since the outputs of o to 0Rxn all become ``1'' at the same time, ``1'' is written into all RAM cells at the same time, and all RAMs are initialized with the initial value @1@.
またロウレベル＠θ″′にて初期設定をする場合は０Ｒ
ｘ０〜０ＲｘｎをＮＯＲゲートにしＤ０〜Ｄｎの信号を
反転し０Ｒｘｏ〜ＯＲｘ、 の入力信号とすれば実現
できる。Also, when initializing at low level @θ″′, 0R
This can be realized by using x0 to 0Rxn as NOR gates, inverting the signals D0 to Dn, and using them as input signals 0Rxo to ORx.
（発明の効果）
以上のように本発明によればマイクロコンビニ−′ｏｎ
ｎｓｎ′ｒ等ｏ制ｍｍ号１極Ｊ６１短Ｉｎ時間Ｋ
ｌＲＡＭの初期設定を行うことができる。
１々お、本発明はマイクロコンビ為−タ
内のＲＡＭたけに限られることはなく、ディスクリート
のＲＡＭチップにも同様に適用できることは明らかであ
る。(Effects of the Invention) As described above, according to the present invention, the micro convenience store
nsn'r etc. o control mm number 1 pole J61 short In time K
Initial settings of lRAM can be made.
First, it is clear that the present invention is not limited to RAMs in microcomputers, but is equally applicable to discrete RAM chips.
第１図は従来のＲＡＭブロック図、第２図は本発明の一
実施例のＲＡＭブロック図でめる。
Ｒｘｏｙｏ 〜Ｒｘｎｙｔｒ−＝ＲＡＭ１ビット記憶素
子、＾Ｄｏ〜ムＤｎ ・・・・・・アドレス信号ｓ Ｒ
Ｏ〜Ｒｎ・・・−ＲＡＭ読み出しバッファ、’Ｗｅ 〜
Ｗ ｎ ”” ・” ＲＡ Ｍ書き込みバッファ、ＯＲ
ｙｏ〜０ＲｙｎｓＯＲｘｅ〜０Ｒｘｎ・・・・・・ＯＲ
ゲート。FIG. 1 is a conventional RAM block diagram, and FIG. 2 is a RAM block diagram of an embodiment of the present invention. Rxoyo ~Rxnytr-=RAM 1-bit storage element, ^Do~muDn...Address signal s R
O~Rn...-RAM read buffer, 'We~
W n ”” ・” RAM write buffer, OR
yo~0RynsORxe~0Rxn...OR
Gate.
Claims (1)
てのワード線を同時に選択する手段と、前記メモリのす
べてのビット線に同時に同一のデータを与える手段とを
含むことを特徴とするメモリ回路。1. A memory circuit in which data can be written, comprising means for simultaneously selecting all word lines of said memory and means for simultaneously applying the same data to all bit lines of said memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16305784A JPS6140628A (en) | 1984-08-02 | 1984-08-02 | Memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16305784A JPS6140628A (en) | 1984-08-02 | 1984-08-02 | Memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6140628A true JPS6140628A (en) | 1986-02-26 |
Family
ID=15766352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16305784A Pending JPS6140628A (en) | 1984-08-02 | 1984-08-02 | Memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6140628A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63311551A (en) * | 1987-06-15 | 1988-12-20 | Fujitsu Ltd | Memory initializing system |
| JPH0289291A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Static random access memory |
| JPH0413293A (en) * | 1990-04-30 | 1992-01-17 | Nec Ic Microcomput Syst Ltd | Memory circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5067044A (en) * | 1973-10-15 | 1975-06-05 | ||
| JPS5291620A (en) * | 1976-01-29 | 1977-08-02 | Toshiba Corp | Memory element preset circuit |
| JPS5785255A (en) * | 1980-11-17 | 1982-05-27 | Nec Corp | Memory storage for integrated circuit |
-
1984
- 1984-08-02 JP JP16305784A patent/JPS6140628A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5067044A (en) * | 1973-10-15 | 1975-06-05 | ||
| JPS5291620A (en) * | 1976-01-29 | 1977-08-02 | Toshiba Corp | Memory element preset circuit |
| JPS5785255A (en) * | 1980-11-17 | 1982-05-27 | Nec Corp | Memory storage for integrated circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63311551A (en) * | 1987-06-15 | 1988-12-20 | Fujitsu Ltd | Memory initializing system |
| JPH0289291A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Static random access memory |
| JPH0413293A (en) * | 1990-04-30 | 1992-01-17 | Nec Ic Microcomput Syst Ltd | Memory circuit |
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