JPH0514359B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to semiconductor memories, particularly dynamic
This invention relates to a RAM (random access memory) read/write control circuit.

(Prior art) Generally, large-capacity dynamic RAM is used to process large amounts of data at high speed, such as in image processing, using pipelines. In this case, the processing format is memory reading → processing → memory writing, and if this is executed sequentially in a normal mode, one cycle will take a long time. Therefore, we decided to use the high-speed mode normally provided in dynamic RAM, such as static mode.
I often use column mode. The operation in conventional static column mode is analogous to
This is done at the timing shown in the figure. That is,
The memory output data D _put becomes valid after a maximum of time t _AA shown in the figure after inputting the column address to the memory, and then Process 1 is performed on this output data. This processing 1 takes time t _p , and this processed data 1 is written to the same memory address as in the above read operation. Thereafter, reading the data at the next address requires at most the time t _ALW shown in the figure, and thereafter, the operation of processing the read data and writing the processed data to the same address is repeated. Therefore, the cycle time is t _p +
t _ALW is required, and this t _ALW is about twice the cycle time t _sc in static column mode. If this t _sc and the above t _p are equal, the cycle time is about three times t _sc . become. Another example of operation in the conventional static column mode is performed at the timing shown in FIG. That is, the address is changed at cycle time t _sc , and in the first cycle, the memory output data D _put
Data 1 at a certain address 1 is read out, and in the next cycle, data 2 at a different address 2 from the above is read out, and at the same time, processing 1 of the read data 1 is performed. In the next cycle, writing of the processed data (processed data 1) to the address 1 and processing 2 of the read data 2 are performed. In the last cycle, the processed data (processed data 2) is written to the address 2.
Therefore, in the above operation, four cycles are required for two data, and in the end, two cycles (twice _tsc ) are required for one data.

As mentioned above, in the conventional static column mode, the cycle time t _sc is 2 to 2 to perform a series of operations of reading → processing → writing.
It takes about three times as long, which is not preferable in terms of high-speed processing. Furthermore, in the operation example shown in FIG. 4, the memory control becomes complicated because the addresses must be changed at one cycle interval so that they are the same.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problem that the series of operations of reading memory → processing → memory writing in the static column mode takes a long time. , it is an object of the present invention to provide a dynamic memory that can efficiently execute the above series of operations at high speed.

[Structure of the Invention] (Means for Solving the Problems) The dynamic memory of the present invention has a structure in which an input/output bus is commonly connected to each column of a memory cell array via an input/output gate. , the write bus is connected in common through the write gate, and the input/output gate is selected for each cycle in the static column mode to latch the column decoder output when controlling the input/output gate to enable reading. In the second and subsequent cycles, a latch circuit is provided which selects the write gate based on the column decoder output latched in the previous cycle and controls the write gate to be writeable.

(Function) During each cycle of the static column mode in which the column address changes while a predetermined row address is given during the active period of the row address strobe signal, the data of a certain column address is read simultaneously, and at the same time In the second and subsequent cycles, it becomes possible to write the data read out one cycle before and then processed to the column address one cycle before. In other words, during a series of operations from memory read → processing → memory write, memory write is delayed by one cycle of static column operation compared to memory read, making it possible to read and write to different addresses simultaneously in one cycle. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a part of a dynamic RAM integrated circuit, where 1 is a memory cell array (including sense amplifiers in addition to memory cells), and each column's bit line pair is connected to an input/output gate 2... (simplified). For convenience, only one transistor gate is shown) to the input/output bus 3. In the memory cell array 1, a row address is designated by a row decoder (not shown), a column address is designated by a column decoder 4, and memory cells are selected. The output of the column decoder 4 switches and controls the transfer gates of the input/output gates 2.

Furthermore, in the memory of this embodiment, a write data bus 6 is commonly connected to the bit line pairs of each column via write gates 5 (only one transfer gate is shown for simplicity). , the write gates 5... are each controlled by the output of a latch circuit 7..., which selectively controls the corresponding column (column numbers 1 and 2 are shown for only two for simplicity). The column decoder output for this purpose is latched by a latch control signal from a latch control line 8.

Further, an input pin (terminal) for inputting write data to the write data bus 6 is provided.

Next, a series of operations of memory reading → processing → memory writing in the static column mode in the dynamic RAM will be explained with reference to FIG. First, the row decoder selects a row of the memory cell array 1 by making the row address strobe signal ( ) active (low level) and inputting a row address. Next, by inputting column addresses one after another at the cycle time _tsc in the static column mode, the column decoder 4 outputs decoded signals one after another. In this case, in the first cycle, column 1 is selected by column address 1, and after inputting column address 1, the maximum t _AA shown in the figure is
After a time, valid data 1 is output from column 1 as memory output data D _put to the corresponding input/output gate 2,
It is output via the input/output bus 3, output buffer, and output terminal. Here, the read data 1 is immediately processed by a microprocessor outside the memory, and a calculation result (processed data 1) is obtained after a processing time _tp . This processed data 1 is input from the write data input terminal through the write data bus 6,
It is written in the next second cycle. In this case, the write column address is one cycle before (first
Latch circuit 7...
Since the one latched in is used, it is thereby written to (the selection memory of) column 1. Also, in this second cycle, the column address 1 of the previous cycle (first cycle) changes to the next column address 2. Column 2 is selected by this column address 2, and the corresponding input/output gate is selected from column 2. 2. Valid data 2 is output via the input/output bus 3, output buffer, and output terminal. Thereafter, as described above, at the same time as reading data i for address i in each cycle,
The data i-1 read from address i-1 one cycle ago is processed and the processed data i-
The operation of writing 1 to address i-1 is repeated. In this case, the processing time t _p
Regarding the relationship between t sc and cycle time t _sc , it is sufficient to set t _sc according to t _p so that t _sc > t _p always holds, and for processing where t _p is small, operation is performed at the minimum t _sc can be done.

According to the dynamic RAM of the above embodiment, only one data is processed in the first cycle and the last cycle in the static column operation (in the first cycle 1, only data 1 is read from column 1, and in the last cycle In cycle n, data n is read from column n, but the processing for it is not included), but each of the remaining cycles, which make up the majority of cycles, can process read and write in one cycle, so in the end, the cycle The cycle time in static column mode is _tsc . Therefore, the series of operations of data reading → processing → data writing can be performed two to three times faster than in the conventional example. Moreover, the increase in hardware associated with this is limited to providing one write gate and one latch circuit for each column, as well as providing a write data bus and latch control line for these in common, which reduces the chip area. The increase in the amount is extremely small.

When the dynamic RAM is operated in a normal random access mode, the write gate and latch circuit are rendered inactive and the input/output gates 2 are used to perform writing/reading.

Note that the present invention is not limited to the memory integrated circuit as in the above embodiment, but is also applicable to an on-chip memory in which a memory and a logic circuit other than the memory are formed on the same chip.

[Effects of the Invention] As described above, the dynamic memory of the present invention can efficiently and quickly perform the series of operations of reading memory → processing read data → writing processed data to memory in the static column mode, and moreover, the dynamic memory of the present invention The increase in chip area is small, and the increase in chip area is negligible. Therefore, large-capacity dynamic processors used when processing image data at high speed using pipelines, etc.
It is extremely effective to apply the present invention to RAM.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a part of an embodiment of the dynamic memory of the present invention, FIG. 2 is a timing diagram showing read and write operations in static column mode in the memory of FIG. 1, and FIG.
4 and 4 are timing diagrams showing operation in different static column modes in a conventional dynamic memory, respectively. 1... Memory cell array, 2... Input/output gate, 3... Input/output bus, 4... Column decoder, 5... Write gate, 6... Write data bus, 7... Latch circuit, 8... Latch control line.

Claims (1)

[Claims] 1. In a dynamic memory having a static column mode in which the row address remains constant and the column address is changed multiple times at a constant cycle time _tsc , input/output gates for each column of the memory cell array are provided. A write gate is provided separately, a write data bus is connected to each column through the write gate, and the input/output gate is selected and controlled to be readable in each cycle of the static column mode. A latch circuit is provided which latches the column decoder output at the time of the write operation and selects the write gate according to the column decoder output latched one cycle before in the second and subsequent cycles of each cycle to control the write gate. Dynamic memory characterized by