JP2512994B2 - Vector register - Google Patents

Description

The present invention relates to a vector register used in a vector operation device represented by a supercomputer.

[Conventional technology]

The vector arithmetic unit is operated at a high speed by continuously operating the array data stored in the vector register based on the pipeline control method. recently,
The vector operation can be executed without disturbing the pipeline control even for the array data for which the condition of whether or not to perform the operation is determined. That is, the vector operation device includes a vector operation instruction with a mask for controlling whether or not an operation is performed on each array element by mask data in the mask register. The effective processing speed of the vector operation device is greatly influenced by the ratio of vector operation processing, that is, the vectorization rate. Therefore, the vector register must be constructed so that it can process vector operations with masks.

FIG. 4 is a block diagram showing a configuration example of a conventional vector register. For convenience of description, the figure also includes the arithmetic unit 5.

First vector register 1 and second vector register 2
Each array element of array data is stored in one dimension.
The array elements are respectively supplied from the two vector registers 1 and 2 to the arithmetic unit 5, and the processing result is written to the first vector register 1 or the second vector register 2 continuously for other array elements. Thus, vector operation is performed.

The number of bits of the first mask register 3 and the second mask register 4 is equal to the number of words of the first and second vector registers 1 and 2, and the respective bits of the first and second mask registers 3 and 4 are the first and the second.
Stores mask data for each word of vector registers 1 and 2. Each bit of the mask data controls the operation for each array element in the first and second vector registers 1 and 2.

In the vector operation with mask, the mask data is serially read from the first mask register 3 (or the second mask register 4) in synchronization with the reading of the array elements from the first and second vector registers 1 and 2, and the 1-bit logic Arithmetic unit 6 (AL
The mask data is supplied to the write control circuit 7 via U). The write control circuit 7 controls whether or not the calculation result is written in the first vector register 1 (or the second vector register 2) based on the mask data. By controlling in this way, it is possible to execute the vector operation with mask without disturbing the pipeline control.

[Problems to be Solved by the Invention]

Vector operations with masks process repetitive operations including conditional operations at high speed. The mask data in this case is generated by the truth of the condition. When this condition is determined by a plurality of array elements, it is necessary to generate new mask data by a logical operation between the plurality of mask data.

In the conventional vector register, the mask data is read bit by bit from the first and second mask registers 3 and 4, and a logical operation is performed by the logical operation unit (ALU) 6, and the new mask data is transferred to the first mask register 3 ( Alternatively, it is stored in the second mask register 4). Therefore, the logical operation time for the number of array elements is required to generate new mask data. That is, the conventional vector register has a drawback that it requires a great deal of processing time to generate mask data and further requires the ALU 6 for mask data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector register in which the mask data is read in synchronization with the reading of array elements and the above drawbacks are improved.

[Means for solving the problem]

The vector register of the present invention comprises N first word lines and N word M words having M sets of first bit lines intersecting the first word lines.
Each memory cell is connected to a first memory cell array of bits, each of the first bit lines and each of the M second word lines, and is commonly connected to the second bit lines and the parallel mask data selection lines. A second memory cell array, a column decoder for selectively driving the first word line according to a word address, a row decoder for selectively driving the second word line according to a bit address, and the first bit line Each of M first R / W amplifiers and a second R / W amplifier connected to the second bit line, or N first word lines and M sets of first R lines intersecting the first word lines. A first memory cell array of M words N bits having bit lines, each memory cell connected to each of said N first word lines and N sets of second bit lines and a set of third bit lines. For each parallel mask data selection line A second memory cell array of N bits connected in series, a column decoder for selectively driving the first word line according to a word address, and a column decoder connected to each of the first bit line and the third bit line. It comprises a 1R / W amplifier and a second R / W amplifier connected to each of the second bit lines.

[Action]

By taking the above means, it becomes possible to read the mask data in the second memory cell array in series in synchronization with the reading of the array elements in the first memory cell array. Further, since the mask data in the second memory cell array can be read and written in parallel, the mask data can be generated at high speed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention.
In the figure, the vector register is the first memory cell 111.
A first memory cell array 110 having M rows and N columns and a second memory cell array 1 including M second memory cells 121.
20, a column decoder 130 that selectively drives the columns of the first memory cell array 110, and a row decoder 140 that selectively drives one second memory cell 121 in the second memory cell array 120, The first of the specific columns selectively driven by the column decoder 130
For the M first R / W amplifiers 160 for reading and writing to the memory cells 111 or the second memory cell array 120 connected to the parallel mask data selection line, and for the second memory cells 121 selectively driven by the row decoder 140. And a second R / W amplifier 170 for reading and writing.

The column decoder 130 selectively drives the first word line 132 designated by the word address 131. Selectively driven first
The M first memory cells 111 in the column connected to the word line 132 output the contents to the first bit line 161 when reading, and take in the contents on the first bit line 161 when writing. This read / write selection is performed by the first R / W signal 162, whether the first R / W amplifier 160 makes the first bit line 161 high impedance (during reading) or whether the write data is supplied to the first bit line 161 ( It depends on writing).

The row decoder 140 is the second designated by the bit address 141.
The word line 142 is selectively driven. The second memory cell 121 connected to the selectively driven second word line 142 outputs the content to the second bit line 171 at the time of reading, and takes in the content on the second bit line 171 at the time of writing. The selection between reading and writing is determined by the second R / W signal 172.

Each word of the first memory cell array 110 stores an M-bit array element and is used as a vector register. Each second memory cell 121 of the second memory cell array 120
Stores master data for each array element in the first memory cell array 110 and is used as a mask register.

First memory cell array 110 serving as a vector register
The writing of the array element to is performed by supplying the M-bit array element from the R / W data line 163 to the first bit line 161 via the first R / W amplifier 160. The write word is specified by the word address 131. The M-bit array element stored in the first memory cell array 110 is output to the R / W data line 163 via the first bit line 161 and the first R / W amplifier 160. When the parallel mask data selection line 150 is driven, parallel reading or writing of the second memory cell array 120 is performed. In this case, the parallel mask data selection line 150 inhibits the driving of the first word line 132 of the column decoder 130, and thus the read / write operation of the first memory cell array 110 is inhibited.

The second memory cell array 120 can perform a read / write operation to the second memory cell 121 designated by the bit address 141 in parallel with the parallel read / write operation. Therefore, while the array element is being read from the first memory cell array 110, the mask data relating to that array element can be read serially from the second memory cell array 120, so that the vector operation with mask can be processed. The logical operation of the mask data can be processed in M bits in parallel by the arithmetic unit used for the array elements.

That is, the vector register of the present invention can store both array elements and mask data, accelerates the logical operation of mask data, and eliminates the need for a logical arithmetic unit for mask data.

2 (a) and 2 (b) are circuit diagrams showing configuration examples of the first memory cell 111 and the second memory cell 121 in FIG.

The first memory cell 111 of FIG. 2A is composed of two inverters 201 and 202, and two MOS transistors 206 and 207 whose drain terminals are connected to a pair of bit lines 203 and 204 and whose gates are connected to the first word line 132. Composed. In FIG. 1, for convenience of description, the pair of bit lines 203 and 204 is represented by one first bit line 161. The first memory cell is a normal static memory cell.

The second memory cell 121 in FIG. 2B is a two-port memory cell, which is composed of two inverters 210, 211 and four MOS transistors 212, 213, 214, 215. The gates of the MOS transistors 212 and 213 are connected to the parallel mask data selection line 150 in FIG. 1, and their drain terminals are connected to a pair of bit lines 216 and 217 (the first bit line 161 in FIG. 1). The gates of the MOS transistors 214 and 215 are connected to the second word line 142 in FIG. 1, and their drain terminals are connected to the bit lines 218 and 219 of the other pair (the second bit line in FIG. 1). This memory cell sets the parallel mask data selection line 150 and the second word line 142 to the high level, so that the read / write operation via the pair of bit lines 216 and 217 and the read / write operation via the other pair of bit lines 218 and 219 are performed. The writing operation can be performed in parallel.

FIG. 3 is a block diagram showing a second embodiment of the present invention.
In the figure, the vector register is the first memory cell 311.
A first memory cell array 310 having M rows and N columns and a second memory cell array 3 including N second memory cells 321
20, the first memory cell array 310 and the second memory cell array
A column decoder 330 that selectively drives a column of the array 320, (M + 1) R / W amplifiers 360 connected to each row by the first memory cell 311 and the second memory cell 321 and the first bit line 361,
The second memory cell 321 is composed of N second R / W amplifiers 370 connected by a second bit line 372.

The first memory cell array 310 stores array elements in each column or word, and the second memory cells 321 corresponding to each column of the first memory cell array 310 store mask data.

The column decoder 330 selectively drives the word line 332 designated by the word address 331. The M first memory cells 311 and the second memory cells 321 in the column connected to the selectively driven word line 332 output the contents to the first bit line 361 at the time of reading, or on the first bit line 361 at the time of writing. Capture the content.

The first R / W signal 362 specifies reading and writing of the first memory cell array 310, and the second R / W signal 363 is the second memory cell array 310.
Specifies read and write for array 320. R / W amplifier 360
Outputs the contents on the first bit line 361 to the outside during a read operation, and transfers the data from the outside to the first bit line during a write operation.
Output on 361. Therefore, by scanning the word address 331, (M + 1) R / W amplifiers 3 can be read.
60 continuously outputs the array elements stored in the first memory cell array 310 and the mask data relating to them,
Enables vector operations with masks.

Parallel reading of N-bit mask data stored in the second memory cell array 320 is performed by driving the parallel mask data select line 350. When the parallel mask data selection line 350 is driven and the third R / W signal 371 is set to the read mode, the N-bit mask data is transferred to the second R / W amplifier.
It is output to the outside via 370. On the other hand, when the third R / W signal 371 is set to the write mode, the second R / W amplifier 370 is externally connected.
N-bit mask data is written in parallel to the second memory cell array 320 via. That is, since the mask data can be read / written in parallel, the logical operation between a plurality of mask data can be processed in parallel, resulting in high speed operation.

The first memory cell 311 is configured as shown in FIG. 2 (a), and the second memory cell 321 is configured as shown in FIG. 2 (b).

[Effects of the Invention] As described above, according to the present invention, mask data can be accessed in parallel in the same manner as array data, so that logical operations between a plurality of mask data can be performed at high speed by using a parallel operation unit for array data. Can be processed. That is, the logic operation unit for mask data is unnecessary. Moreover, since both the array data and the mask data can be stored in the vector register, the chip size can be reduced when integrated into an integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, and FIG. 2 (a).
And (b) is a circuit diagram showing a configuration example of a memory cell.
FIG. 4 is a block diagram of the second embodiment, and FIG. 4 is a block diagram of a conventional vector register. 110,310 …… First memory cell array, 111,311 …… First
Memory cells, 120, 320 ... Second memory cell array, 12
1,321 …… Second memory cell, 130,330 …… Column decoder, 14
0 …… Row decoder, 160,360 …… First R / W amplifier, 170,370
...... Second R / W amplifier.

Claims (2)

(57) [Claims] 1. An N-word M-bit first memory cell array having N first word lines and M sets of first bit lines intersecting the first word lines, and each of the first bit lines and M first bits. Two
A second memory cell array having memory cells connected to each of the word lines and commonly connected to a second bit line and a parallel mask data selection line, and the first word line is selectively driven according to a word address. A column decoder, a row decoder for selectively driving the second word line according to a bit address, M first R / W amplifiers connected to each of the first bit lines, and a second bit line Second R / W
A vector register comprising an amplifier. 2. A first memory cell array of M words and N bits having N first word lines and M sets of first bit lines intersecting the first word lines, each memory cell being the N first word lines. And an N-bit second memory cell array connected to each of the N bit second bit lines and commonly connected to one set of the third bit line and the parallel mask data selection line, respectively, and the first word according to the word address. A column decoder for selectively driving lines, a first R / W amplifier connected to each of the first bit line and the third bit line, and a second R / W amplifier connected to each of the second bit line A vector register comprising: