JP3111051B2 - Byte write method and apparatus for memory array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to computer systems, and more particularly to selectively writing one or more bytes of information to memory words in a memory array. And a method and apparatus.

[0002]

2. Description of the Related Art A typical computer has input / output devices (such as a keyboard and a display) for a user interface, a permanent storage device (such as a magnetic disk or an optical disk), and a temporary memory device (random access memory). A plurality of interconnected hardware, including a central processing unit (CPU or processor) that accesses the persistent storage and the temporary memory device when executing program instructions (such as RAM).
The present invention relates to a method and apparatus for accessing a temporary memory array such as a RAM.

[0003] These arrays are often organized in rows and columns, sometimes further organized by other groupings, such as sectors (one sector includes many columns). All cells in a given row are called a memory word. For a store or load operation, a given memory cell (bit) in the array is
Accessed by selecting that particular cell based on its address. Such a selection is typically made by a row decode circuit that provides an active logic level on a conductor known as a word line across a given cell row. When a word line for a given row is activated, all memory cells in that row are connected to respective "bit lines". Bit lines, on the other hand, are connected to other circuits, such as sense amplifiers, which allow access to the memory cells. For example, a word line can access an array having 32 cells in a row to provide a 32-bit value (program instruction or data). In a memory array having 2 @ N word lines, selecting one of these word lines typically requires an N-bit address input. Each word line has one decoder circuit, and all decoder circuits receive and decode an N-bit address input. In response, 1
Only one word line is selected and all other word lines in the array are deselected.

FIG. 1 shows an example of a conventional memory array. In this memory array, memory cells 2 are arranged in small groups 4 of 8 bits each. Several such groups 4 exist in a given column 6. Any encoding method can be used to provide a unique memory address to access a particular row of memory cells.
A given word line 8 (only one word line is shown in FIG. 1) is selected by any type of decoding circuit, including gate 10. Only one word line is selected and all other word lines are deselected. When one word line is selected, all cells in the corresponding row are connected to respective local bit lines 12. In the array of FIG. 1, all local bit lines for a given group 4 of memory cells are further connected to global bit lines 14. These global bit lines are further connected to circuits (eg, sense amplifiers) used to read from and write to cells.

[0005] Certain designs (US patent application Ser.
No. 8 / 717,575), the charge on the gate of a transistor whose source is connected to one side of its flip-prop, in which two inverters are connected in a flip-flop fashion, is controlled by a word line, and the same transistor Is connected to the bit line. The "clear" line controls the charge at the gate of the second transistor. The source of the second transistor is connected to the other side of the flip-flop, and its drain is connected to ground. In this way, the clear line is used to clear the memory cells. Although this memory cell design has several advantages over the prior art, one disadvantage is that the cell must be cleared before writing to that cell, and that the cell in the array must be cleared. It is further necessary for layout that all cells in one row share the same clear line. Therefore, all cells in one row must be cleared before writing to any cell in that row. However, arrays are often required to support writing to individual bytes in a row. That is, a row consists of a number of bytes, each having one or more bits, but often only a portion of these bytes should be changed.

Typically, an array has thousands of bytes, but providing thousands of corresponding rows is not practical, and it is therefore more convenient to group the bytes in a single row. It is also advantageous to have more than one byte in a single row, because the read operation can read all the bits in a single row at the same time, and thus read multiple bytes of information all at once. For example, some modern microprocessors have registers with a size of 8 bytes,
A memory array is efficient if it has 8 bytes in one row. (It is often desirable to read more than 8 bytes in a single read operation to load multiple registers simultaneously). These processors use an instruction set that requires the processor to manipulate (write) individual bytes. Thus, selective writing to individual bytes in one memory row may combine this feature with the previous design, as clearing the entire row may result in loss of the remaining information in that row. It was difficult to do. It is therefore desirable and beneficial to create a method for selectively writing individual bytes in a memory row without losing the remaining information.

[0007]

Accordingly, it is an object of the present invention to provide an improved memory array for a computer system.

It is another object of the present invention to provide a memory array having a plurality of memory rows, wherein individual bytes can be selectively written to any of the memory rows.

It is yet another object of the present invention to provide a memory array that allows an entire memory row to be cleared prior to a write operation.

[0010]

The above objects are achieved by the following method of storing information in a memory device having a memory word containing a plurality of bytes. The method generally includes storing information from all bytes in a memory word in temporary space, clearing the memory word, and storing a portion of the stored information in at least one of the bytes in the memory word.
And writing the new information to at least one other byte in the memory word. The memory word includes a plurality of memory cells grouped to form a byte, the temporary space is a cache having a plurality of storage locations, and the storing step stores information from each byte in the cache. Writing to each one of the storage locations. The step of writing is performed using at least one multiplexer that selectively writes stored information or new information in response to a control signal.

The temporary space (cache) includes a latch for each memory cell, the multiplexer includes an enable line having on and off states, and the enable line is stored in the latch when the enable line is in the off state. Write information to the memory word, but write new information to the memory word if the enable line is on. Each memory word contains multiple bytes and is accessed using addressable word lines. In a particular embodiment, each memory cell is connected to a respective transistor, and each transistor has its gate connected to a word line. The clearing step includes turning on a word line to connect each memory cell to ground.

The above and further objects, features, and advantages of the present invention will become apparent from the following detailed written description.

[0013]

DETAILED DESCRIPTION OF THE INVENTION Referring to the drawings, and in particular to FIG.
A block diagram of one embodiment of the memory write circuit of the present invention is shown. The memory write circuit 20 generally comprises a memory word 22, a temporary memory device such as a cache 24 for reading data from the memory word, a memory word 2
2 comprises an information device, such as a computer processor, which supplies the new data to be stored in the new data device 26, and a multiplexer 28 having two inputs respectively connected to the cache 24 and the new data device 26. The output of multiplexer 28 is memory word 2
2 is connected as an input to. The multiplexer 28
Enable line 30 connected to the multiplexer 28
Is designed to write the contents of cache 24 to memory word 22 except when is turned on. When the enable line 30 is activated by a processor or other controller, the multiplexer 28 writes new information from the device 26 to the memory word 22. The original contents in memory word 22 are stored in temporary space (cache 2
4), after which the memory word 22 is cleared, but any part of the original content is rewritten to the memory word 22 via the multiplexer 28. The portion of the original content that is not rewritten is selectively replaced by new data. In this way, even if the memory
Even if word 22 is designed to require the entire word to be cleared prior to any write operation, it is possible to selectively write individual bytes within this memory word.

The memory word 22 can be implemented by a conventional memory device such as an SRAM (Static Random Access Memory) array having a plurality of such memory words. In this case, a single multiplexer can be used to write information to the memory words, but multiple multiplexers can be provided. Alternatively, a memory device that supports memory word 22 may only transfer information after it has been cleared, ie, after the state of each cell in that word has been set to the same (lower) voltage. A newly designed device may be used as long as it does not receive it. Similarly, cache 24 may be of various designs according to the particular application (hardware platform), and multiplexer 28 may be implemented in many ways as will be apparent to those skilled in the art.

One particular embodiment is shown in FIG. Memory circuit 40 includes a memory cell 42 connected to a read circuit 44 and a write circuit 46. Memory circuit 40 is a portion of a larger circuit that includes other memory cells (not shown) that are the same as memory cells 42 and are in a matrix of a memory array. Additional read and write circuits 44 and 46 are provided for each cell in a given row. However, as described below, although some components of the read circuit 44 and the write circuit 46 may be duplicated for additional cells in a given column, for each cell in a given column It is not necessary to provide separate read and write circuits. The memory circuit 40, which arranges the 128 cells in one column into four large groups of 32 cells, is specifically designed for the array. Each of these groups is further subdivided into eight small groups of four cells each.

A memory word is formed by a row of bits (cells) so that the bits in a given row are read or written collectively. Multiple word lines are used to address each memory word. One word line is available for each row,
In the illustrated embodiment, each word has two word lines, namely:
It has a read word line and a write word line. This configuration,
Allows memory cells to have dual ports (bit lines) so that two rows are accessed simultaneously. Two (similar) connection lines 48 and 50 from the read word line are provided in the memory cell 42 and two connection lines 52 and 54 from the write word line are provided, but the signal from the connection line 54 is Delayed as described below. The read port of memory cell 42 comprises a first read output 56 and a second read output 58, while the write port comprises a first write input 60 and a second write input 62 (as described below). Connected to

The first read word line 48 is connected to the gate of an n-type field effect transistor (NFET) 64,
The source of the ET 64 is connected to the first read output 56. The second read word line 50 is connected to the gate of another NFET 66 and the NFET 66 source is connected to the second read output 58. The first write word line 52 is connected to another NFET 68
And the source of NFET 68 is connected to the first write input 60. The second write word line 54 has another N
Connected to the gate of FET 70, the source of NFET 70 is connected to second write input 62. The drain of NFET 64 is connected to the source of another NFET 72,
The drain of 72 is connected to ground. Similarly, N
The drain of FET 66 is connected to the source of another NFET 74, and the drain of NFET 74 is connected to ground. The gates of both NFETs 72 and 74 are connected to a flip-flop formed by two inverters 76 and 78. The gates of those two NFETs,
The drain of NFET 70 and the output of inverter 78 are all connected to the input of inverter 76. The output of inverter 76 is connected to the input of inverter 78 and the drain of NFET 68. It will be apparent to those skilled in the art that this configuration of transistors and inverters provides a bistable and reproducible memory cell, such as a typical SRAM cell.

The operation of the read circuit 44 is not relevant to the present invention as it relates to a method of selectively writing to cells of a memory word, but a read operation is also described for completeness of the description. I will.
The reading circuit 44 includes three evaluation circuits 8 connected in series.
0, 82, and 84. The first read output 56 is connected to an input of a first read evaluation circuit 80, the input of which is connected to the input of an inverter 86 and the drains of two p-type field effect transistors (PFETs) 88 and 90. P
The sources of FETs 88 and 90 are connected to a source voltage (Vdd). The gate of PFET 88 is connected to system clock 89 (signal c1). The gate of PFET 90 is connected to the output of inverter 86. Inverter 86
Control the charge at the gate of the other NFET 92. The drain of NFET 92 is connected to ground and its source is the output of first read evaluation circuit 80. The first read evaluation circuit 80 is actually connected to four different memory cells. Inputs from the other three cells (not shown) of them are represented at 94. These four cells make up one of the aforementioned small groups. (Eight of these small groups together form one of four large groups in a given 128-cell column). By performing such grouping,
The number of components (evaluation circuits) required to support all cells is small. 128 in a given column
In order to receive input from all the cells, 32 such first read evaluation circuits 80 are required.

The output of the first read evaluation circuit 80 is connected to the input of a second read evaluation circuit 82 which is exactly the same as the first read evaluation circuit 80. The input of the second read evaluation circuit 82 is the input of another inverter 96 and two further PFETs.
98 and 100 are connected to the drains. PFET98
And 100 are connected to Vdd. PFET98
Is connected to the delayed clock 99 (signal cl +). The gate of PFET 100 is connected to the output of inverter 96. The output of inverter 96 is another N
The charge at the gate of the FET 102 is controlled. NFE
The drain of T102 is connected to ground and its source is the output of the second read evaluation circuit 82. The second read evaluation circuit 82 is actually connected to eight different first read evaluation circuits. Inputs from the other seven of them, not shown, are represented at 104. The cells corresponding to these eight connection lines together form one of four large groups in a given 128 cell column. To receive input from all 128 cells in a given column, four such second read evaluation circuits 82 are required.

The output of the second read evaluation circuit 82 is connected to the input of a third read evaluation circuit 84, which is the same as the first read evaluation circuit 80 and the second read evaluation circuit 82. The input of the third read evaluation circuit 84 is connected to the input of another inverter 106 and the drains of two further PFETs 108 and 110. The sources of PFETs 108 and 110 are Vdd
Connected to. The gate of PFET 108 is connected to a further delayed clock 109 (signal cl ++). PFE
The gate of T110 is connected to the output of inverter 106. The output of the inverter 106 is the output of the third reading evaluation circuit 84 and the output of the reading circuit 44. This circuit (including circuits 80, 82, and 84) replaces conventional sense amplifiers. The third reading evaluation circuit 84 is actually 4
Connected to a plurality of different second read evaluation circuits. The inputs from the other three of them, not shown, are 112
Is represented by Only one third read evaluation circuit 84 needs to receive input from all 128 cells in a given column. The second read output 58 is used to similarly generate a second (independent) output for the read operation.

When the memory array is idle and the circuit is precharged, the nodes between the read evaluation circuits are high and the output of the third read evaluation circuit 84 is low. When the read word line is turned on,
When the memory cells 42 are in the low state (0), their read evaluation circuits remain the same and the output of the third read evaluation circuit 84 remains low. If the memory cells 42 are in the high state (1) when the read word line is turned on, their read evaluation circuits flip and the output of the third read evaluation circuit 84 changes to high.

Next, a write operation of a memory word, and in particular, how this method can be used to select selected bytes of a memory word, even if the memory word is completely cleared before new data is written. Explain whether it is possible to write to
Refers to any number of groups of bits, including one). The write circuit 46 includes three evaluation circuits 114, 116, which are connected in series similarly to the read evaluation circuits 80, 82, and 84.
And 118. The first write input 60 is connected to the first write evaluation circuit 114, the input of the inverter 120 and the drains of the two PFETs 122 and 124.
The first write input 60 is also connected to a write NFET 126 described below. The sources of PFETs 122 and 124 are Vdd
Connected to. The gate of PFET 122 is connected to recovery signal 12
5 (bit line recovery). The gate of PFET 124 is connected to the output of inverter 120. The output of inverter 120 controls the charge at the gate of another NFET 128. The drain of NFET 128 is connected to ground and its source is the output of first write evaluation circuit 114. The first write evaluation circuit 114 is actually connected to four different memory cells. The input from the other three of them, not shown, is 130
(They correspond to the same three cells represented by 94). To receive input from all 128 cells in a given column, 32 such first write evaluation circuits 114 are required.

An output of the first write evaluation circuit 114 is connected to an input of a second write evaluation circuit 116 similar to the first write evaluation circuit 114. The input of the second write evaluation circuit 116 is NF
Connected to the drains of ET 132 and PFET 134. The source of PFET 134 is connected to Vdd and its gate is connected to another recovery signal 135 (signal "Group 4").
Recovery)). The gate of NFET 132 is connected to select line 137 (signal “read path enable”),
The source of NFET 132 is another inverter 136
And the drains of two additional PFETs 138 and 140. The sources of PFETs 138 and 140 are connected to Vdd. The gate of PFET 138 is connected to another recovery signal (signal "group 32 recovery"). The gate of PFET 140 is connected to the output of inverter 136. The output of inverter 136 is connected to the gate of another NFET 142, the drain of NFET 142 is connected to ground, and its source is connected to the second
This is the output of the write evaluation circuit 116. The output of the inverter 136 is also connected to a latch 144 described later. The second write evaluation circuit 116 is actually connected to eight different first write evaluation circuits. Inputs from the other seven not shown circuits are represented at 146. To receive inputs from all 128 cells in a given column, four such second write evaluation circuits 116 are required.

The output of the second write evaluation circuit 116 is connected to the input of the third write evaluation circuit 118. The input of the third write evaluation circuit 118 is connected to the input of another inverter 148 and the drains of two further PFETs 150 and 152. The sources of PFETs 150 and 152 are V
Connected to dd. The gate of PFET 150 is connected to another recovery signal (signal "group 128 recovery"). The gate of PFET 152 is connected to the output of inverter 148. The output of inverter 148 is output 149 ("cast out") of third write evaluation circuit 118. This output, the bit line, is connected to a conventional circuit (such as a sense amplifier) to complete the write evaluation / recovery operation. Third write evaluation circuit 118 is actually connected to four different second write evaluation circuits.
Inputs from three other circuits not shown are represented at 154. 128 in a given column
In order to receive input from all cells, one third
Only the write evaluation circuit 118 is required.

The data value in memory cell 42 is actually written by NFET 126. When the write word line is turned on, the first write word line 52
126 drives the memory cell via transistor 68. However, as can be seen with reference to FIG. 4, before this occurs, several other steps occur due to the timing of the various clock signals. Two key signals 89 and 155 to generate a four-phase clock system
(C1 and ci) are used. The signal ci has the same length as the signal c1, but is 90 ° out of phase. Signal 1
57 (c2) is a complement of the signal c1, and a signal 159 (ci_) is a complement of the signal ci.
Each of these four signals is a quarter (４)
Enables the generation of other signals having a length that is a multiple of the cycle.

During the first quarter cycle, all cell values in the memory word are read and stored in respective cache elements, eg, latches 144. Latch 144 is essentially an SRAM element (memory cell), but its output 156 is NFE
It is multiplexed with other data via T158. NFET
Drain 158 is a device 1 for supplying a new data signal
65, eg, connected to a cell in a register or other memory array, the gate of NFET 158 is connected to an enable device, eg, a computer processor (signal “write byte” 161). During the first quarter cycle, NFETs 68 and 132 are turned on (by word line 52 ("first word line" in FIG. 4) and read path enable signal 137) and PFETs 122 and 13 are turned on.
4, 138 and 150 are turned off (bit line recovery signal 125, group 4 recovery signal 135, group 32
Recovery signal 139 and group 128 recovery signal 151). The write NFET 126 outputs the “bit line drive” signal 1
Off during read / store cycle due to 63.

During the second quarter cycle, NFET 7
A 0 causes the signal on the second write word line 54 to pull the cell to ground level, thereby clearing all memory cells in the row. The delayed signal is generated using two AND gates 160 and 162. Gate 160 has clock signals 155 and 157 (ci and c2) as its inputs. Gate 162 has as its inputs the (first) write word line and the output of gate 160. The output of gate 162 is NF
The ET 70 is driven.

During the third quarter cycle, in response to bit line drive signal 163 becoming active,
Data is rewritten to the memory cells. The group 32 recovery signal 139 is off during this quarter cycle to avoid a tune condition. If the byte write signal 161 is turned on (by the processor) during this quarter cycle, instead of rewriting previously stored data, new data is written to cell 42, thereby To achieve the object of the present invention, i.
Will overwrite part of the word. During the fourth quarter cycle, reset signal 167 clears latch 144 so that it can accept new data during the next write operation.

Although the present invention has been described with reference to particular embodiments, this description is not meant to be construed in a limiting sense. Various modifications of this disclosed embodiment, as well as alternative embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description of the invention. Accordingly, it is understood that such modifications can be made without departing from the spirit or scope of the invention.

[0030]

[0031]

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a prior art memory array showing selection of memory words (rows) using addressable word lines.

FIG. 2 is a block diagram illustrating a method of the present invention for selectively writing new data to a portion (one or more bytes) of a given memory word.

FIG. 3 is a schematic diagram illustrating an exemplary circuit that can be used to implement the present invention.

FIG. 4 is a timing diagram illustrating signals associated with selectively writing a portion of a memory word.

Continued on the front page (72) Inventor Michael Kay Salura Tomcat Cove, Round Rock, Texas, U.S.A. References JP-A-5-233478 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/41 G06F 12/04 520

Claims (9)

(57) [Claims] 1. A method for storing information in a memory device having a memory word comprising a plurality of bytes, the method comprising: storing information from all bytes in the memory word in temporary space; Clearing; writing a portion of stored information to at least one of the bytes in the memory word; and writing new information to at least one of the bytes in the memory word.
Writing to two other bytes, wherein the memory word is one of a plurality of memory words each including a plurality of bytes in a memory device, and wherein the memory word is a plurality of bistable memories. A cell, wherein each of the memory cells is connected to a respective transistor, each transistor having a gate connected to a word line, and further comprising accessing a memory word using an addressable word line. The method of claim 1, wherein said clearing comprises turning on a word line to connect each memory cell to ground. 2. A method for storing information in a memory device having a memory word that includes a plurality of bytes, the method comprising: storing information from all bytes in the memory word in temporary space; Clearing; writing a portion of stored information to at least one of the bytes in the memory word; and writing new information to at least one of the bytes in the memory word.
Writing to two other bytes, wherein the two writing steps selectively write stored information or new information in response to a control signal.
Performed using one multiplexer, the temporary space includes at least one latch, the multiplexer includes an enable line having on and off states, and is stored in the latch when the enable line is in the off state. Writing the updated information to a memory word, but writing the new information to the memory word when the enable line is on. 3. An apparatus for storing and retrieving data, comprising: a RAM array having a memory word formed from a plurality of memory cells; and temporarily storing data contained in the memory word. Cache means for selectively storing stored data or new data in the cache in different cells in the memory word; and processor means for controlling the multiplexer means. The memory word is one of a plurality of memory words in the RAM array, the memory word being accessed by an addressable word line connected to the processor. 4. The apparatus of claim 3 including means for clearing said memory word after data from said memory word has been stored in said cache. 5. The cache according to claim 3, wherein said cache includes a plurality of latches, one for each memory cell.
An apparatus according to claim 1. 6. The processor means is connected to the multiplexer means by an enable line having on and off states, wherein the multiplexer means stores data stored in the cache in the memory when the enable line is in an off state. Write to a word, but if the enable line is on, write new information to the memory
Apparatus according to claim 3, characterized in writing in a word. 7. Each of said memory cells is connected to a first transistor providing a write port, and further connected to a second transistor providing a ground connection, wherein said word line is a first word line and a second word line. Connected to a word line, wherein the first word line is connected to a gate of each of the first transistors, and the second word line is connected to a gate of each of the second transistors; 4. The device of claim 3, wherein when memory is turned on, the memory cell is cleared. 8. Each of said plurality of memory words is connected to a respective word line such that each memory word is addressed by said processor means, and further comprising a plurality of memory words respectively connected to said plurality of memory words. And a plurality of multiplexers respectively connected to the plurality of caches such that stored or new data is selectively written to each portion of the memory word. Item 3. The apparatus according to Item 3. 9. The second word line is connected to the second word line via a delay circuit such that data contained in a given memory cell is stored in the cache before a given memory cell is cleared. The device of claim 7, wherein the device is connected to a transistor.