JP2517126B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device used in a microprocessor or the like.

2. Description of the Related Art A normal register-relative store instruction requires three ports for reading a register, a first source address, a second source address, and write data. Realizing the three ports by hardware increases the area.
As a method for preventing such an increase in area, it is conceivable to set the number of ports to two and assign two addresses to the same port. If you realize this with hardware,
Conventionally, the structure shown in FIG. 2 has been used. FIG. 2 shows a register file in which two addresses are assigned to the same port.

The operation will be described below. In the read operation, the first read address 38 and the second read address 39 are input from the outside to the selection means 31, and the selection signal 41 outputs the selection address 41 from the selection means 31. The selected address 41 is decoded by the read decoding means 32 and drives the read word line 42 corresponding to the selected address 41. The read word line 42 controls the output means 33 in the memory array, and the output means 33 outputs the data of the memory cell 34 to the read bit line 43. The data of the read bit line 43 is input to the input / output buffer 37, and the data of the memory cell 34 is output to the outside by the input / output buffer 37.

In the write operation, the write address 45 input from the outside is decoded by the write decoding means 36, and the write word line 46 corresponding to the write address 45 is driven. The write data input from the outside is input to the input / output buffer 37, and the write bit line
Output to 44. The write word line 46 controls the input means 35 in the memory array, and the input means 35 is a memory cell.
The data is output to 34, and the write data is the memory cell.
Written in 34.

However, in the semiconductor memory device as described above, in the case of a store instruction or the like, since the operand field that should be the address of the register file is included in the instruction, the address of the register file is the input of the instruction. At the same time confirmed. On the other hand, since the selection signal is generated by decoding the instruction, the selection signal is fixed relative to the address of the register file, so the selection signal is the rate-determining signal, making it difficult to speed up the read operation. Was there.

The present invention has been made in view of the above problems, and provides a semiconductor memory device in which a read operation is performed without selecting an address of a register file using a selection signal that is a rate-determining signal, and as a result, the read operation is speeded up. The purpose is to do.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention provides n read-out decoding means for inputting n read-out addresses inputted from the outside, and said n read-out decoding means. N read word lines connected to the means, and n output means connected to the n read word lines and receiving data from the memory cells.
The n read bit lines respectively connected to the n output means, and the n data and select signals output from the memory cells to the n read bit lines are input, and input / output is performed. Selecting means for outputting the selected data to the buffer.

According to the present invention, with the above structure, n read addresses input from the outside are input to the semiconductor memory device to which n addresses are assigned to the same port.
Read-out decoding means, n read-out word lines connected to the n read-out decoding means, and n read-out word lines, respectively.
N output means for inputting data from memory cells, n read bit lines connected to the n output means, and n read bit lines from the memory cells An address of the register file is selected by using the selection signal which is the rate-determining signal, by having one selection means which inputs the output n data and the selection signal and outputs the selection data to the input / output buffer. The read operation can be performed without doing so, and as a result, the read operation can be speeded up.

First Embodiment FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a first read decoding means, which receives a first read address 11
Drive the read word line 13 of. 2 is a second read-out decoding means, which is a second read-out address 12
Is input to drive the second read word line 16.
Reference numeral 3 is a first output means which inputs read data by driving the first read word line 13 and outputs the read data to the connected first read bit line 15. Numeral 4 is a second output means for inputting read data by driving the second read word line 14 and outputting read data to the connected second read bit line 16. A memory cell 5 receives write data and outputs read data. Reference numeral 6 is a write decoding means which receives a write address 17 and inputs a write word line 18
Drive. 7 is an input means for writing word line
The write data of the write bit line 19 connected by being driven is input and output. Reference numeral 8 is a selection means, which is the first and second read bit lines.
The read data of 15 and 16 and the selection signal 20 are input, and the selection data 21 is output. An input / output buffer 9 inputs the selection data 21, outputs write data, and inputs / outputs external data 22.

In the read operation, the first and second read addresses 11 and 12 are externally input to the first and second read decoding means 1 and 2, respectively, and the first read word line 13 and the second read word are read. Word line 14 is driven. When the read word lines 13 and 14 are driven, the first output means 3 and the second output means 4 transfer the read data of the memory cell 5 to the first read bit line 15 and the second read data, respectively. Output to bit line 16. The data on the first and second read bit lines 15 and 16 are input to the selection means 8, selected by the selection signal 20, and output as selection data 21. The selected data 21 is input to the input / output buffer 9, and the read data of the memory cell 5 is output as the external data 22 by the input / output buffer 9. As shown in FIG. 2, compared with the conventional configuration in which the read addresses 38 and 39 are selected at the input stage by using the rate-determining signal selection signal,
In the present invention, since the data of the read bit lines 15 and 16 is selected by using the selection signal 20 of the rate limiting signal, the read decoding means 32 is provided from the path from the selection signal 20 to the external data 22. The path of the output means 33 can be deleted, and high-speed read operation becomes possible.

In the write operation, the write address 17 inputted from the outside is decoded by the write decoding means 6, and the write word line 18 corresponding to the write address 17 is driven. External data input from the outside 22
Is input to the input / output buffer 9 and output to the write bit line 19. The write word line 18 controls the input means 7, the input means 7 outputs write data to the memory cell 5, and the write data is written to the memory cell 5.

Although two addresses are assigned to the same port in this embodiment, it is clear that the same effect can be obtained by assigning two or more addresses.

EFFECTS OF THE INVENTION As described above, according to the present invention, n read-out decoding means each receiving n read-out addresses inputted from the outside, and n read-out decoding means are connected. Connected to the n read word lines and the n read word lines, respectively, and connected to the n output means for inputting data from the memory cell and the n output means, respectively. To the input / output buffer that inputs / outputs input / output data by inputting n read bit lines and n data output from the memory cell to the n read bit lines and a selection signal. By having one selection unit outputting the selection data, the semiconductor memory device in which n addresses are assigned to the same port can change the external data from the selection signal that is the rate-controlling signal. Decoding means for reading from the path to
The path of the output means can be deleted, and high-speed read operation becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a block diagram showing a conventional example. DESCRIPTION OF SYMBOLS 1 ... 1st read-out decoding means, 2 ... 2nd read-out decoding means, 3 ... 1st output means, 4 ...
Second output means, 5 ... Memory cell, 6 ... Writing decoding means, 7 ... Input means, 8 ... Selection means, 9 ...
… I / O buffer.

Claims (1)

(57) [Claims] 1. Decoding means for n reading, which respectively receives n reading addresses inputted from the outside,
Write decoding means for inputting a write address inputted from the outside, n read word lines connected to the n read decoding means, and write connected to the write decoding means Read word lines and the n read word lines, respectively, for inputting read data from the memory cells.
Output means and connected to the write word line,
Input means outputting write data to the memory cell; n read bit lines respectively connected to the n output means; write bit lines connected to the input means; Selection means for inputting n pieces of data and selection signals of n reading bit lines and outputting the selection data, and inputting the selection data, writing data is output to the writing bit line, and data is output to the outside. And a semiconductor memory device having an input / output buffer for inputting and outputting.