JPS61150184A - Memory device - Google Patents

Abstract

PURPOSE:To perform many port operations by distributing an input data to a memory cell, selecting an output data and further maintaining it. CONSTITUTION:By inputting a control signal, a four port writing operation is informed to a data input circuit 4 and an address decode circuit 5 from a control circuit 6. After this control, the data is inputted, and through the circuit 4, the same input data is all written in, for instance, a column address (i), line addresses n, n+1, n+2, n+3. When seeing this data as a memory of many ports, the respective addresses can be considered as the first, the second, the third, and the fourth ports, respectively. In the case of a reading operation, a data output circuit 3 is treated as a mass together with 4 bits data and the read data is latched indue according to the column address. In this manner, An RAM capable of operating many ports can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to any-time write/read memory devices below R5M.
The present invention provides a circuit configuration for operating a multi-vote memory. - Prior Art In conventional RAMs, an input address signal is separated into a column address signal and a row address signal, and a unique address is given to each signal, thereby selecting a unique bit and outputting its contents. Therefore, in order to perform multi-vote memory operation, the memory cells should have a multi-vote structure (for example, IEKIC JOUNALO
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Multiple boards were used to perform multi-vote operations using an external control circuit.

Problem to be Solved by the Invention In the former case, when there are three or more points, the structure of the memory cell becomes complicated and the cell area increases, making it difficult to achieve high integration. Furthermore, as the number of output ports increases, the number of word lines also increases, making the word line selection circuit more complex. On the other hand, in the latter case, the same number of memories as the number of ports are required (however, the R
(When AM is used), there is a further drawback that the external circuit becomes complicated.

The present invention has been made in view of these points, and an object of the present invention is to provide a circuit configuration for operating a multi-port memory without using complicated memory cells or complicated external circuits.

Means for Solving the Problems In order to solve the above problems, the present invention provides a data input circuit capable of distributing input data to one or more memory cells by control signals and address signals,
The data output circuit is capable of selecting and holding one or more pieces of data using a control signal and an address signal.

By controlling these with a control circuit, multi-port operation can be performed.

Function: With the above-described configuration, the present invention can operate as a multi-port memory without using complicated memory cells or complicated external circuits.

Embodiment FIG. 1 shows a schematic configuration of a memory device in an embodiment of the present invention. In FIG. 1, 1 is a memory cell array, 2 is a memory cell array, and 2 is a memory cell array.
is a sense amplifier circuit, 3 is a data output circuit, 4 is a data input circuit, 5 is an address decode circuit, 6 is a control circuit,
7 is a data input/output terminal.

8 is an address input terminal, and 9 is a control signal input terminal.

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The operation of the apparatus shown in FIG. 1 will be explained using FIG. 2.

Here, a four-vote operation will be explained.

(1) Write operation First, by inputting a control signal, the control circuit 6 notifies the data input circuit 4 and address decode circuit 5 that it is a 4-port write operation. Therefore, the data input circuit 4 receives an instruction to write one data into four bits at the same time, and the address decode circuit receives an instruction to switch the row address for four ports. That is, the row address is given in units of 4 bits. When the above control is completed, data is input and written into the memory cell via the data input circuit 4. For example, column Abilev 1 1
The same input data is written to all row addresses n, n+1, n+2, and n+3.

In Figure 2, data ``11'' is placed in column address 1, row 1, addresses n to n+a, and data ``0'' is placed in column address j, 1 row address n - n + 3%, and data ``0'' is placed in column address 1, row 1, address n - n + 3%. Set data ``0'' to address nNn+3 as 1
An example is shown in which data ``''1'' is written to column address 1 and row address n' - n + s. If this situation is viewed as a multi-port memory, one row address n -
Addresses n + 3 can be collectively considered to be addresses N.

Address n, address n+1, address n+2, and address n+3 are the first . Second. Third. You can think of it as a fourth boat.

? ) Read Operation First, by inputting a control signal, the control circuit 6 notifies the data output circuit 3 and the address decoding circuit 6 that it is a 4-port read operation. Therefore, the data output circuit 3 receives an instruction to treat the 4-bit data as one block and to latch the read data in order according to the row address. Furthermore, since four addresses are consecutively given to the address decoding circuit 5, it generates four column addresses, as well as an address containing a row address in units of 4 bits and information on which port to select from among the row addresses. generate. Subsequently, the word line is accessed, data is read out to the bit line, and is latched to the specified output port in the data output circuit 3 via the sense amplifier circuit 2, as well as to the data input/output terminal 7.
is output to. The above operation will be explained according to the example shown in FIG. Here, four different column addresses (i, j, l) are given to one row address (address N), and the first . Second. Third. Assume that an instruction to output from the fourth port is given. Data in the column at address li is read out to the bit line by column address i and sent to data output circuit 3 via sense amplifier circuit 2 . On the other hand, the data output circuit 3 outputs the first
Since an instruction to output from the port is given, the signal is latched and output only to the first port of the first row address N. Subsequently, data in the column at address j is read out using column address j and output from the second port at address N. Thereafter, the signals are output from the third port and the fourth port in the same manner. The reason why the data output circuit 3 has a latch function is to hold previously read data until all necessary port data is available. Furthermore, although four different column addresses are used here as an example, they do not need to be different and may be the same.

Furthermore, as another embodiment, a configuration may be considered in which data to be read is always handled in units of words. An example of this is shown in FIG. The operation is similar to the example shown in FIG. 2, but since the row address is no longer required, the scale is reduced by simply selecting the required port.

Effects of the Invention As described above, according to the present invention, instead of using a memory cell with a complicated multi-board structure as in the past,
By using a plurality of M, it is possible to realize a RAM capable of multi-port operation without using an external control circuit to perform multi-port operation, which is extremely useful in practice. In addition, in the memory device of the present invention, each part can be formed as an integrated circuit on the same semiconductor substrate, and each part and each wiring are integrated on the semiconductor substrate and made on-chip, and each terminal is a terminal of the integrated circuit. It is possible to do so.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a memory device according to an embodiment of the present invention;
Fig. 2 is a diagram for explaining the operation of the device shown in Fig. 1;
The figure is a schematic configuration diagram of another embodiment of the present invention. 1...Memory cell array, 2...Sense amplifier circuit, 3...Data output circuit, 4...
...Data input circuit, 5...Address decoder circuit, 6...Control circuit, 7...Data input/output terminal, 8...Address input terminal, 9
......Control signal input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4 ζ-~ Figure 3

Claims (1)

[Claims] A memory cell array that can write, read, and hold data, a sense amplifier circuit that detects data read from the memory cell array, and a data output circuit that has the function of selecting and holding at least one piece of data using a control signal and an address signal. , a data input circuit capable of distributing input data to at least one memory cell in accordance with a control signal and an address signal, and an address decoding circuit having a function of sequentially accessing one or more words in accordance with a control signal. and a data input/output terminal for inputting and outputting data to and from the outside of the device.
A control signal is sent to each of the address input terminal, the control signal input terminal, the data output circuit, the data input circuit, the address decode circuit, the data input/output terminal, and the address input terminal to control the functions of each part. The data input/output terminal is connected to at least one of a bit line of the memory cell array or an output section of the data output circuit via the data input circuit, and the data input/output terminal is connected to the bit line of the memory cell array or the output section of the data output circuit. The line is connected to the input section of the data output circuit via the sense amplifier circuit, and the address input terminal is connected in parallel to the data input circuit, the data output circuit, and the memory cell array via the address decode circuit. A memory device, wherein the control signal input terminal is connected to the control circuit.