JPS61180991A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the effective use of data lines and at the same time to keep the electrical balance by providing signal input/output ports to a pair of data lines respectively. CONSTITUTION:A shift register SR is provided to data lines. Thus the random read/write operations are possible for a single selected bit, and the parallel read/write operations are possible via the SR for all bits connected to a work line Wi or Wj. It is possible to extract selectively data on a single bit passed through a Y decoder YD or the data on many bits passed through the SR by actuating selectively both the SR and the YD. The write operation is also possible simultaneously for all bits connected to said work lines Wi and Wj with use of the SR. and also for a single bit at random via the YD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a peripheral circuit of a memory.

[Conventional technology]

For memory using conventional IMO8T cells,
73031, a preamplifier (usually using a flip-flop) is used to detect the differential signal applied to the two data lines. From the perspective of this preamplifier, opposite voltages such as high and low voltages are always applied to the two data lines. In addition, a circuit for providing an input/output data signal is added to only one of these two data lines.6 [Problems to be Solved by the Invention] In the case of the configuration shown in the above-mentioned prior art, the input was only performed from one place.

For this reason, the other data line was not used effectively (Figure 1). Furthermore, there is a drawback that the pair of data lines that should be balanced cannot be electrically balanced.

An object of the present invention is to provide a semiconductor memory in which all data lines can be used effectively, and also to provide a semiconductor memory that does not disturb the electrical balance of a pair of data lines.

[Means for solving problems]

In the present invention, by providing a signal input/output port for each of a pair of data lines, the data lines are used effectively and electrical balance is maintained.

Electrical balance is achieved by connecting an input/output port to each pair of data lines.

〔Example〕

In the present invention, a shift register SR is provided on the data line, as shown in FIG. 2, in order to effectively use the data line, which has not been used in the past. Therefore, in addition to being able to randomly read and write to one selected bit as before, it is also possible to write and read all bits connected to one word line in parallel, such as writing and reading through this SR. It can also be processed. In other words, when one word line is selected, read signals from all bits connected to it are taken into the SR and serially taken out to the outside, and at the same time only Y to 1 bit 1 of the read signals of all bits is input to the SR. It can also be extracted as data externally through a decoder. Furthermore, by selectively operating the SR and Y decoders, it is possible to selectively take out either one bit of data passed through the Y decoder or multiple bits of data passed through the SR. Also, if you use SR for writing,
This can be done simultaneously for all bits connected to the same word line, or it can be done for random 1 bits through a Y decoder as in the past.

It is also obvious that this SR can be used as a means for simultaneously testing all bits connected to one word line.

Although it is theoretically possible to place SR and YD on the same data line when viewed from the preamplifier, generally YD and S
Since the area occupied by R is large, this is not a good idea in terms of layout. Also, two data lines (for example, do,
In order not to disturb the balance of do), YD and SR are
It is preferable to place them on different data lines.

〔Effect of the invention〕

As described above, by placing a Y decoder on one data line and a shift register on the other data line of the two data lines of a conventional IMO8T cell type memory, a memory that does not disrupt electrical balance can be obtained. It will be done.

Although the above explanation is an example using an IMO5T cell,
It is clear that this method can also be applied to general memories.

[Brief explanation of the drawing]

Figure 1: Memory using conventional IMO5T cells Figure 2:
Memory memory with shift register of the present invention YD: Decoder, Wi, Wj: Word line %M:
Cell, PA, -PA3: preamplifier, do, do: data line, Di, Do: data input, data output, respectively.
SR: Shift register

Claims (1)

[Claims] 1. A semiconductor having a plurality of word lines, a plurality of data lines, a plurality of memory cells provided at the intersections of the word lines and the data lines, and a preamplifier connected to the data lines. In the memory, a first means for reading or writing signals in the memory cells; at least reading signals in the memory cells in parallel and sequentially outputting them; reading signals in the memory cells in sequence and writing them in parallel; A semiconductor memory characterized by having second means for doing any of the following.