JPS61134989A - Serial access system of dynamic type memory - Google Patents

Abstract

PURPOSE:To remarkably improve an average data transferring speed in which -RAS cycle is considered by repeating -CAS cycle with a desired number of times within one time of -RAS cycle as for all data stored in memory cells corresponding to one line address. CONSTITUTION:A signal -RAS descends and a lime address signal AiR is fetched into a line decoder 2. Then one line of memory cells is selected and the data of the memory cells are latched by a sense amplifier 4. Thereafter, a signal -CAS descends and a row address signal AiC is fetched into a row decoder 5 through a multiplexer 12. Then 4-bit data from the sense amplifier 4 are transferred to a 4-bit shift register 7 through a transfer gate circuit 13 and the one bit of the address designated by the row address signal AiC is trans ferred to an output buffer 8 and becomes output data Dout. When the signal -CAS ascends thereafter, the output of a 2-bit down counter 15 becomes ''H'' level and the row address signal A>=C is advanced step by step, and thus, a new internal row address signal (AiC+4) is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory, and more particularly to a serial access system of a serial access memory that is a dynamic memory used in an image memory and the like and is capable of serial access.

[Technical background of the invention]

For large-capacity memories, it is important to shorten access time, but there is a strong demand for high-speed data transfer, and access order must be random for image memory and main memory of computer systems. It is often better to use cereal rather than cereal. In order to meet this demand, it has been put into practical use that dynamic memory is used in nibble mode. Figure 3 shows a conventional dynamic random access memory with nibble mode (
(RAM) is shown. That is, "in" is an address signal input, AiR is a row address signal, A>c is a column address signal, 1 is a memory cell array, 2 is a row decoder, 3 is a row address buffer, 4 is a sense amplifier, 5 is a column decoder, and 6 is a column address signal. The column address t4 y is 77. 1 is a 4-bit shift register, and the sense amplifier 4
This is for storing the read data read out from the 4-pin and tonnage parallels once and serially transmitting it to the output pin 8. It has a function that allows the data transfer order of 4-bit data to be preset by the preset control input. are doing.

Reference numerals 9 and 10 each receive a column address strobe signal chs and a row address strobe signal RAS, which are external inputs, and serve as a CAS system of the memory circuit.

[CAB-based timing generation circuit that generates Ω-based timing signals, RT″s; A timing generation circuit.

FIG. 4 shows the timing of the nibble mode operation of the memory, and the nibble mode operation will be briefly explained below.

When the signal A1B falls, the row address signal A1B is taken into the row decoder 2 and access is started, and one row of data is read from the memory cell array 1 and loaded into the sense amplifier 4. Next, as the signal CAS falls, the column address signal A1c is taken into the column decoder 5, and from the four sense amplifiers 4 including the sense amplifier of the column specified by the column address signal, the 4V, The data of 4 pins are transferred to the shift register 7, and among these 4 bits of data, the column address signals A, .

The 1st and 1st pin of the address specified by is the output buffer 8.
The output data Dout is transferred to the output data Dout.

The above 4-bit data is the column address signal person.

A predetermined combination of pins including the bit data ROM 1e at the address specified by.

data DA (j=0 to 3), and ic+
j For example, 512 pins in the row direction) X 512 pins in the column direction, 256 pins
In the case of a KX1-bit memory, the row address signal A t
9th bit ASR of n and 9th bit of column address signal Aie
This is 4-bit data with different bits A and e. Next, when the signal CAS rises and falls again, one bit of data of the untransferred data stored in the shift register 7 is transferred to the output buffer 8 and becomes output data Dout. Similarly, each time the signal CAf9 falls, the untransferred data stored in the shift register 7 is changed to 1.
Bit by bit is transferred and output. The transfer order of the 4-bit data DAic+j transferred in this way is, for example, DA, DA as shown in FIG.
,DA, ,DA,. +3ic ic+1
It is set like lc+2 or DAIce
DA lc+1 #DA, DA may be set as ic+21cm1, and is determined according to the preset input.

Therefore, according to the above nibble mode operation, the signal RAS
The access time for the first fall of the signal CAS after the fall of CAS is the same as the access time in normal memory operation, but the access time for the second and subsequent drops of the signal CAS is significantly different from the access time in normal memory operation. be shortened. This is because serial access is performed in which the order of access is fixed every time the signal CAS falls after the second@, and it is possible to prepare output data in advance.

[Problems with background technology]

By the way, in the above-mentioned conventional dynamic memory with nibble mode, only 4 bits of data can be read out serially for one access by the signal RAS, so the average data transfer rate is low considering the cycle of the signal RAS. It's not very expensive. Therefore, for one [r access, there are roughly a large number of accesses.

The number of bits in the shift register is set to 8.16. Although it is conceivable to increase the number of data by increasing the number of data, it is not possible to obtain a sufficient data transfer speed by simply doing so. In order to speed up data transfer, all data specified by one row address (for example, 64KX
1 B.

256 bits in case of 256×1
In the case of a bit RAM, there are 512 pits.

It would be impractical to provide a 256-bit or 512-bit shift resist to read out the data, but this would significantly increase the chip area.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a dynamic memory that can serially output or input all data corresponding to one row address at high speed, and can suppress an increase in chip area. It provides a serial access system.

[Summary of the invention]

That is, in the serial access system of the dynamic memory of the present invention, in the first serial access operation defined by the CAS signal after row address access, the external input column address is taken in and the 2n
(n=1゜2,...) Outputting or inputting kit data is performed via a 2n-bit shift register, and the external input column address is preset in a counter with a preset function, and the CA8 signal is 2n
The counter is incremented every li period, and in the second and subsequent serial access operations, the internal column address obtained by the counter is taken in, the contents of the shift register are updated, and the data of 211 pits is output or input. Accordingly, all data corresponding to one row address are serially output or input.

Therefore, the data transfer speed is determined by the shift register and remains high speed, and there is little increase in chip area due to the addition of counters, etc., and all data corresponding to one row address can be serially output or input. can.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The dynamic memory shown in FIG. 1 is different from the dynamic memory described above with reference to FIG. , and others are the same, so the same reference numerals as in FIG. 3 are given and the explanation thereof will be omitted.

The counter circuit 11 includes a binary counter 14 which receives the column address signal A1c from the column address buffer 6 and presets it, and a binary counter 14 which receives the column address signal A1c from the column address buffer 6 and receives four clock signals generated at the fall timing of the signal CAS from the CAS timing generation circuit 9. (2) performing an up operation every four cycles of the signal CAS to increment the nary counter 14;
It consists of a bit down counter 15. The column address multi-sensor 12 receives the column address signal A1° from the column address buffer ACK and supplies it to the column decoder 5, and then outputs the up output CT of the 2-bit down counter 15.
In response, a column address signal (expressed as A, .+4n) from the binary counter 14 is sent to the column defooder 5.
It is intended to supply Said transfer dart circuit 1
3 transfers the 4-bit parallel data read from the sense amplifier 4 to the 4-bit shift register 7 based on a timing signal supplied from the CAS timing generation circuit 9 at a predetermined timing (for example, ζ in FIG. 2). It is.

Next, we will discuss the serial access operation of the above memory in the second section.
This will be explained with reference to the figures. The signal RAS falls and the row address signal Ai8 is taken into the row decoder 2, one row of memory cells is selected, and its data is latched into the sense amplifier 4.

Next, the signal CAS falls, the column address signal A1c is taken into the column decoder 5 via the multiplexer 12, and four sense amplifiers including the sense amplifier of the column designated by the column address signal among the sense amplifiers 4 are activated. The selected 4-bit data from the sense amplifier is transferred to the 4-bit shift register 7 via the transfer ff-) circuit 13, and 1 bit of the address designated by the column address signal among the 4-bit data is transferred to the output buffer. 8 and becomes output data Dout. in this case,
Column address signal Aic from column address buffer 6 is taken into column decoder 5 and binary counter 1
4, and the grisée and to are performed. Next, when the signal CAS rises, the output of the 2-bit down counter 15 becomes % a I (high) level, and this up output CT causes the binary counter 14 to operate up and output the column address signal A. is incremented to obtain a new internal column address signal (denoted as A, c+4). Next, when the signal CAS falls, one bit of the untransferred data stored in the shift register 7 is transferred to the output buffer 8.
The output data Dout is transferred to the output data Dout. In parallel with this operation, the column address signal (A, , +4) from the binary counter 14 is taken into the column decoder 5 via the multi-brancher 12, and the sense amplifier of the column designated by this new column address signal is The four sense amplifiers included are selected, and the read operation of 4-pin data from these sense amplifiers is started.

Thereafter, similarly, each time the signal CAS falls, the untransferred data stored in the shift register 7 is output one bit at a time. In this case, the transfer order of the 4-pit data of the shift register 7 follows the preset order, and the serial transfer rate is high. Then, every time the transfer of the 4-bit data of the shift register 7 is completed, the contents of the shift register 7 are changed from the old data (based on the column address signal A1°) to the new data (based on the column address signal A1°+4). It is necessary to update the transformer 77, for example at the timing t shown in FIG. -) Circuit 13
is opened and the 4-bit read data from the sense amplifier 4 is stored in the shift resolution buffer. In this way, one bit of data is output from the shift register 7 every cycle of the signal CAS, and the column address in the memory is incremented by the binary counter 14 every four cycles of the signal 61, and
tc+4n (n=1.2...), and the contents of the shift register 7 are updated every time this column address is updated, so all the data corresponding to one row address is Output data Dou in the order shown in
It is obtained as t. Here, output data D A1c*
D A1e+11 D A1c+21 D A1c+3
is a set of 4 read out at column address signal A1c.
It is pit data and continues to be column address signal Alc+.
D A set of 4-bit gaters read when <
i. +41 > c+s l D A1 c+6
1 D A by A
It is expressed as ic+7.

Note that although the above embodiment has been described with respect to the data read operation, column address access control similar to that in the read operation is performed also in the data write operation. That is, data is output (read operation) or input (write operation) via the shift register every cycle of the external input signal (CAS in the above example).

In addition, it is not limited to 4-pin shift registers, but also 8-pin, ), 16-pin shift registers.
Bit, like... (2n biy) (n=1.2.・
) shift register may be used. In this case, the contents of the shift register are updated by operating a counter circuit every 2n periods of the external input signal (CAS in the above example) according to the number of bits in the shift register. do it.

〔Effect of the invention〕

As described above, according to the column address access system of the dynamic memory of the present invention, all data in the memory corresponding to one row address is accessed by the required number of CAS cycles within one RAS 111 period. By repeating it, you can input or output serially. Therefore, it is possible to realize a serial access memory in which the average data transfer rate considering the RAS cycle is significantly improved. Moreover, compared to conventional memories, it is only necessary to add a counter circuit, a two-column address multiplexer circuit, etc., and the chip area only increases slightly.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a serial access system of a dynamic, linear memory according to the present invention. This figure is a schematic diagram showing part of a conventional dynamic memory with nibble mode, and FIG. 4 is a timing diagram shown to explain the nibble mode operation of the memory of FIG. 3. 1...Memory cell array, 4...Sense amplifier, i
... Column address buffer, 7... Shift register,
11...Counter circuit, 12...Multiple pulser,
13...1 transfer gate circuit, 14...binary counter, 15...2 bit down counter.

Claims (1)

[Claims] In the first serial access operation defined by the external input signal after row address access, the external input column address is taken in and 2^n(
n = 1, 2, ...) bit data is output or input via a 2^n bit shift register, and the external input column address is preset in a counter with a preset function. The counter is incremented every 2^n cycles of an external input signal that defines an output operation or an input operation, and in the second and subsequent serial access operations, the internal column address obtained by the counter is taken in and the contents of the shift register are Update 2^
A serial access system for a dynamic memory, characterized in that by outputting or inputting n-bit data, all data corresponding to one row address can be serially output or input.