JPS63887A - Memory cartridge - Google Patents

Abstract

PURPOSE:To reduce the number of address buses, and connector pins, by setting an address signal for a semiconductor memory by a latched high-order address, and a low-order address through a counter. CONSTITUTION:Data from connector pins connected to the address buses (a0-a7) of a memory cartridge 20 are latched at latch circuits 22 and 23. Meanwhile, a chip select signal SEL, etc., is counted by a counter 24. And the respective outputs of the circuit 22, and the counter 24 are set as the high-order bit or the low-order bit of the address signal, and a built-in semiconductor memory cell 21 is accessed by the address signal. By such constitution, the address buses are reduced, and the number of the connector pins in the memory cartridge can be reduced, and the reliability of connection can be improved.

Description

[Detailed Description of the Invention] [NF;' Xj. [Field of application of memory cartridge] This invention is applicable to a memory cartridge. More specifically, the present invention relates to an improvement in an address generation circuit for an IC file memory cartridge (hereinafter referred to as a "dome memory cartridge").

[Conventional technology] In general, a memory cartridge houses a memory element and a connector in a case, and is attached to a memory cartridge controller (hereinafter referred to as a cartridge controller) via the connector, and is used in a host computer (so-called information processing equipment)
or connected to that processor, etc., and used. It also plays a role as an expansion or auxiliary storage medium for external, internal, and auxiliary storage devices of computer systems.

In a conventional memory cartridge, for example, if the memory capacity iIt is 500K bytes, the number of addresses is 19 from 21θ to atS, and the data bus dθ is
If you add 8 trees of ~d7, power supply, ground, and control signals, the number becomes more than 30 trees, and the number of connector pins must be equal to or more than 4.

The memory cartridge is connected to the cartridge control device through the connector having a large number of pins.

[Problems to be Solved] For this reason, the insertion/extraction force increases, and the reliability of the connection of the phase 7f also decreases. Recently, there has been a tendency for memory cartridges to become larger in capacity.
This is becoming a big problem.

This invention solves the disadvantages of an increase in the number of connector pins due to the increasing size of memory cartridges, an increase in insertion/extraction force, and low reliability of the connection, thereby improving reliability. It is an eleventh objective of the present invention to provide a memory cartridge which is excellent and suitable for the human body.

[Steps to Solve the Problems] The L stage in the memory cartridge of the present invention to achieve the above 11 objectives consists of a conductor memory, this semiconductor, and a latch that holds the upper address of the memory. circuit and the access signal sent from the information processing device or the cartridge control device, or the chip select signal-3.
The 14-conductor memory is accessed according to the value of the counter, with the count result of the counter being used as the lower address of the 14-conductor memory.

By the way, if the memory cartridge used as the storage medium of the external auxiliary storage device has a memory arrangement similar to that of a floppy disk, etc., the conventional DOS (disk operating system) can be used, and the increase in software costs can be reduced. There are advantages. However, with a floppy disk, is it possible to read/tell data in the middle of the sector?
1 degree, resulting in a so-called block transfer and sequential access within the sector.For this reason, in the cartridge control device that controls the memory cartridge, it is necessary to transfer data from the host 1 computer (host CPU). It is possible to calculate the start address of a memory block from the sector name information and send one block of data sequentially from that address. You can also handle memory cartridges in the same way as floppy disks.

In such a case, as described above, a latch circuit for holding an upper address representing the start address of a block and a counter for generating a lower address are provided inside the memory cartridge, and the data in the latch circuit and By using the counter data as an address signal to the semiconductor memory, the number of address paths to the cartridge control device can be reduced, and thus the number of connector pins can be reduced.

As a result, it is possible to provide a memory cartridge that does not require a large insertion/extraction force and has high connection reliability.

[Example Code] An example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory cartridge controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of a cartridge control device.

20 is a memory cartridge, which is installed in the cartridge controller 10 shown in FIG.゛It will be 1.

The cartridge control device 10 is a control device for driving the memory cartridge 20 shown in FIG.
Data from U (not shown) is transferred to its data bus Do.
7+ connector 11 (indicated by a dotted line), is received via the internal data bus, and is selectively sent to the data bus buffer 2, track register 3, sector register 4, command register 5, and status register 6 according to the respective data. Store in.

■These trunk register 3, sector register 4,
An interface/system: tlllRCPU (microprocessor) that calculates the address of the memory cartridge by referring to the data of the command register 5 and the status recorder 6, and 7 is a data bus bar. 7fa 2, trunk register 3l sector register 4. This is an address decoder that selects the command register 5 and status register 6 from manually input address signals. That is, the address input from the host CPU. + sign Aθ~A2. The chip select σ100 is input to the address decoder 7 as a selection signal for selecting the data bus buffer 2 and various registers 3 to 6, and is decoded thereby.

Further, [)RQ and IRQ are data request and interrupt request signals to the host CPU. And connector 12
The memory cartridge 20 is attached to the cartridge control device 10 via the dotted line. In addition, 8 and 9 are
NANI) gate with output enable O
Selectively output either E or write enable WE.

On the other hand, as shown in FIG. 1, the memory cartridge 20 has a built-in semiconductor memory device 21 (for example, a memory array) and a memory backup power supply (not shown), and a connector 12 of the cartridge control device 10. and connector 25 (shown by a dotted line).
At 12, the memory cartridge 20 is configured to be removable. Here, communication between the cartridge control device 10 and the memory cartridge 20 is performed through the connector 12.25 111.

Therefore, the data line 1]θ~1]7 of the memory element 2l of the memory cartridge 20 is connected to the data bus d o
-d71 It will be connected to the cartridge lithography control device 10 through the connector 25.

On the other hand, the address line's 1t bytes A8 to A, s. A
ts~A2a are connected to launch circuits 22.23, and latch circuits 22.23 are connected to address buses aθ~a7 connected to connector 25. Therefore, data on address buses aθ to a7 is raffled to latch circuits 22 and 23, and becomes address data. At this time, the latch circuits 22 and 23 each receive the strobe signal S7.
, STROBEI. Controlled by STROBE2.

In addition, the selection signal 5 to the data bus bar 7.2 in FIG. 2 is connected to the connector 25 as SEL.
This signal is input to the memory cartridge 20.
L is counted by the counter 24, and the count result is inputted to the lower address line of the memory element 21, and becomes the address signal of the lower byte AD-A7.

Next, to explain the operation, the data bus bar,
The data stored in is sent to the data buses dθ to d7 of the memory cartridge 20 via the data bus, the connector 12, and the connector 25, and is sent to each register of the track register 3, sector register 4, command register 5, and status register 6. is controlled by the interface control CPUI.

The address decoder 7 decodes the address signal AD-A2 from the host CPU and the chip select CS created by decoding the address signals from A3, which are higher addresses than this, to the data bus buffer γ2 and the track register. 3. Each register of sector register 4, command register 5 and status register 6 is selected,
The interface control CPUI performs read/write operations under the control of the host CPU through DRQ and IRQ signals, and changes direction with R/W from the host CPU.

Furthermore, the interface control C is used to activate either the output enable OE or the write enable WE depending on the read/write command from the host CPU and the status of No. 1 R/W, that is, the transfer direction.
The PUI outputs gate signals Gl and G2 to the NAN I) gates 8 and 9. When the CPU performs data transfer with the data bus buffer 2, the selection signal for the data bus buffer 2 becomes active, the address decoder 7 decodes this, and the selection signal becomes SE.
It is also output to the memory cartridge 20 as L.

When transferring data, the host CPU writes the track MS into the track register 3 and the sector number J into the sector register 4. Interface control river CPU1
writes the contents of track register 3 and sector register 4 to t
! t(it) calculates the address of the memory cartridge 20, and sends the 41st address a8 to a23 to the address bus aθ to a7 and STROB.
E.I. At the sending timing of STROBE2, it is sent to the launch circuits 22 and 23 of the memory cartridge 20 and set therein.

Thereafter, the host CPU sends a transfer command to the command register 5 and waits for the data request signal [)RQ to become active.

The interface control CPUI is command register 5.
The data transfer from the host CPU to the memory cartridge 20 (WR I TE) or the data transfer from the memory cartridge 20 to the host CPU (
REA I)).

Lower address of IC file memory a Q' = 1
7 is generated by counting the selection signal to the data bus buffer 2 by the counter 24 of the memory cartridge 20, and the addresses aθ to a7 are updated one by one each time one byte of data is read or written.

Reading/writing to memory is performed by R from the host CPU.
The timing is determined by the /W signal, but the command register 5, ! Depending on the content of the F command, if the I'F is written into the memory, the error enable signal Wτ is sent, and if it is read, the out enable signal Sino, σ is activated.The R/W signal is These enable signals are gated in NAN I) gates 8 and 9, respectively, and WE. It is output to the memory cartridge 20 side as OE.

As shown below, virtually divide the memory space of IC file memory-12 into multiple tracks and sectors, similar to a floppy disk, and extract one sector from the memory with the specified track number and sector number. data can be transferred in blocks.

Now, the number of connection pins in the connector 25 of this embodiment is 21 including the number of wires shown, or 24 including power lines, write protection, etc. not shown. With this number of signal lines, it is possible to access the memory space of Aθ~A2J, that is, 16 MBYTE.
f ability.

As described above, it goes without saying that the host CPU in the embodiments may be a general information processing device. In addition, in the embodiment, the SEL signal is set as the count signal of the counter, but this is a so-called access signal ``f'', and the chip select signal t is replaced with the access GC ``f''. Of course, it is also possible to rely on ノ.

Note that the term "memory cartridge" in the present invention has a conceptual meaning that includes not only so-called IC cards but also storage devices such as RAM packs that have a built-in memory and are connected to an information processing device. It is.

[Effects of the Invention] As can be understood from the explanation in 1-1 below, the present invention has the following advantages: ``11 conductor memory and 1... of this semiconductor memory. The latch circuit that holds the position address and the access (.-'i
The archbone'+shi< is equipped with a counter that counts the chip select signal by 1, and the count result of the counter is set as the lower address of the conductor memory, and the count value of the counter is set to 11 according to the value of the counter.
Since the conductor memory is accessed, the number of connector bins can be reduced.

As a result, the insertion/extraction force is not large and there is no problem with the connection. ．． We can provide highly reliable memory cart Rinon.

4. FIG. 1 is a block diagram of a memory cartridge according to an embodiment of the present invention, and FIG. 2 is a block diagram of a cartridge and storage control device.

l...Interface system 11cPU12...Data bus buffer, 3...Track register, 4...Seter register, 5...Status register, 6...Command register, 7...Address decoder, 8, 9・
...N A N I) Gate, 10...Memory cartridge ffil control device, 11, 12.25...Connector, 20...Memory cartridge, 21...゛1' conductor memory element r1 22.23 ...Latch circuit, 24...Counter, Figure 1 Figure 2/+0

Claims (3)

[Claims] (1) A semiconductor memory, a latch circuit that holds an upper address of the semiconductor memory, and a counter that counts access signals or chip select signals sent from an information processing device or a memory cartridge control device, A memory cartridge characterized in that the result is set as a lower address of the semiconductor memory, and the semiconductor memory is accessed according to the value of the counter. (2) The semiconductor memory is housed in a case and attached to a memory cartridge control device via a connector, and an upper address and an access signal or a chip select signal are sent from the memory cartridge control device. A memory cartridge according to scope 1. (3) The semiconductor memory is a static RAM backed up by a battery, and the data bus and address bus of this static RAM are connected to a connector, according to claim 1 or 2. memory cartridge.