JPS5532288A - Lsi memory - Google Patents

Lsi memory

Info

Publication number
JPS5532288A
JPS5532288A JP10583778A JP10583778A JPS5532288A JP S5532288 A JPS5532288 A JP S5532288A JP 10583778 A JP10583778 A JP 10583778A JP 10583778 A JP10583778 A JP 10583778A JP S5532288 A JPS5532288 A JP S5532288A
Authority
JP
Japan
Prior art keywords
memory
address
data
stored
bus lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10583778A
Other languages
Japanese (ja)
Inventor
Akihiko Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10583778A priority Critical patent/JPS5532288A/en
Publication of JPS5532288A publication Critical patent/JPS5532288A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Abstract

PURPOSE:To decrease the number of bus lines between LSI memory and the peripheral devices, by time sharing control of memory through the provision of address, write-in data and read-out data storage means. CONSTITUTION:The address via the NAND gate 21 gated with the clock of the clock oscillator 23 of the peripheral device 20 is stored in the address storage means 13 of the LSI memory 10. Next, the write-in data through the NAND gate 22 of the device 20 is stored in the data storage means 13 of the memory 10. Then, at the address location of the memory cell 11 stored in the means 13 by the output of the control circuit 13, the data stored in the means 13 is written in. The read-out is similarly made at sequential time sharing, to make common use of the bus lines for the address and data information to decrease the number of bus lines. Accordingly, the number of connection pins between the LSI memory and the peripheral devices can be decreased to constitute LSI memory high in mounting density.
JP10583778A 1978-08-29 1978-08-29 Lsi memory Pending JPS5532288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10583778A JPS5532288A (en) 1978-08-29 1978-08-29 Lsi memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10583778A JPS5532288A (en) 1978-08-29 1978-08-29 Lsi memory

Publications (1)

Publication Number Publication Date
JPS5532288A true JPS5532288A (en) 1980-03-06

Family

ID=14418136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10583778A Pending JPS5532288A (en) 1978-08-29 1978-08-29 Lsi memory

Country Status (1)

Country Link
JP (1) JPS5532288A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63887A (en) * 1986-06-19 1988-01-05 Hitachi Maxell Ltd Memory cartridge
JPH02123589A (en) * 1988-10-25 1990-05-11 Internatl Business Mach Corp <Ibm> Memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63887A (en) * 1986-06-19 1988-01-05 Hitachi Maxell Ltd Memory cartridge
JPH02123589A (en) * 1988-10-25 1990-05-11 Internatl Business Mach Corp <Ibm> Memory

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