JPS57135490A - Storage device - Google Patents

Storage device

Info

Publication number
JPS57135490A
JPS57135490A JP56021976A JP2197681A JPS57135490A JP S57135490 A JPS57135490 A JP S57135490A JP 56021976 A JP56021976 A JP 56021976A JP 2197681 A JP2197681 A JP 2197681A JP S57135490 A JPS57135490 A JP S57135490A
Authority
JP
Japan
Prior art keywords
written
information
pieces
memory cell
ras
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56021976A
Other languages
Japanese (ja)
Inventor
Sumio Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56021976A priority Critical patent/JPS57135490A/en
Publication of JPS57135490A publication Critical patent/JPS57135490A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

PURPOSE:To obtain a mode with short cycle time, by shortening cycle time required for a write cycle in successive modes. CONSTITUTION:When a row address latch means (-RAS) is activated, a buffer 11 and a row decoder 1 operate and information from a memory cell 22 connected to a word line is transmitted to a bit line 21. For writing infromation in the memory cell 22 in successive modes, the -RAS latches pieces of information to be written in the memory cell. Those latched pieces of information are written in the cell 22 simultaneously or successively through individual I/O lines 5. Therefore, it is confirmed that pieces informations are being written in >=2 different addresses simultaneously.
JP56021976A 1981-02-17 1981-02-17 Storage device Pending JPS57135490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56021976A JPS57135490A (en) 1981-02-17 1981-02-17 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56021976A JPS57135490A (en) 1981-02-17 1981-02-17 Storage device

Publications (1)

Publication Number Publication Date
JPS57135490A true JPS57135490A (en) 1982-08-21

Family

ID=12070053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56021976A Pending JPS57135490A (en) 1981-02-17 1981-02-17 Storage device

Country Status (1)

Country Link
JP (1) JPS57135490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122081A2 (en) * 1983-03-31 1984-10-17 Fujitsu Limited Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122081A2 (en) * 1983-03-31 1984-10-17 Fujitsu Limited Semiconductor memory device

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