JPS57174751A - Data storage device - Google Patents

Data storage device

Info

Publication number
JPS57174751A
JPS57174751A JP5960281A JP5960281A JPS57174751A JP S57174751 A JPS57174751 A JP S57174751A JP 5960281 A JP5960281 A JP 5960281A JP 5960281 A JP5960281 A JP 5960281A JP S57174751 A JPS57174751 A JP S57174751A
Authority
JP
Japan
Prior art keywords
data
writing
timing signal
memory
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5960281A
Other languages
Japanese (ja)
Inventor
Yoshio Maniwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5960281A priority Critical patent/JPS57174751A/en
Publication of JPS57174751A publication Critical patent/JPS57174751A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize the reversible recording of data with high efficiency, by using a buffer memory which is allotted as an area to hold the data control information. CONSTITUTION:When a data is written, the address strobe and the writing strobe are applied from a CPU7. Thus a flip-flop FF1 for request of memory acess is set. The data writing timing signal is applied to a buffer gate BG2, and the writing data is fed to a buffer memory 1 to start the writing of the data. Then the time-shared timing signal has a fall in the lapse of the access time of the memory 1, and a resetting FF3 is set at the rear edge of the timing signal. At the same time, FF1, FF2 and FF3 are reset to complete a cycle for the writing of data.
JP5960281A 1981-04-20 1981-04-20 Data storage device Pending JPS57174751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5960281A JPS57174751A (en) 1981-04-20 1981-04-20 Data storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5960281A JPS57174751A (en) 1981-04-20 1981-04-20 Data storage device

Publications (1)

Publication Number Publication Date
JPS57174751A true JPS57174751A (en) 1982-10-27

Family

ID=13117960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5960281A Pending JPS57174751A (en) 1981-04-20 1981-04-20 Data storage device

Country Status (1)

Country Link
JP (1) JPS57174751A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100316821B1 (en) * 1997-07-21 2002-01-15 칼 하인쯔 호르닝어 Buffer memory arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100316821B1 (en) * 1997-07-21 2002-01-15 칼 하인쯔 호르닝어 Buffer memory arrangement

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