JPS6425257A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS6425257A
JPS6425257A JP18160087A JP18160087A JPS6425257A JP S6425257 A JPS6425257 A JP S6425257A JP 18160087 A JP18160087 A JP 18160087A JP 18160087 A JP18160087 A JP 18160087A JP S6425257 A JPS6425257 A JP S6425257A
Authority
JP
Japan
Prior art keywords
write
pulse
ram
read
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18160087A
Other languages
Japanese (ja)
Inventor
Yoshiaki Tamai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18160087A priority Critical patent/JPS6425257A/en
Publication of JPS6425257A publication Critical patent/JPS6425257A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the number of RAMs by controlling a read pulse and a write pulse to the RAM, and simultaneously read-write from/to one RAM. CONSTITUTION:A write data register 6 holds write data 109 with the timing of a write pulse 105, outputs memory data 118 when it is a write to a RAM 7 with a read signal 114 from a chip select forming circuit 2, and goes to a high impedance when it is a read to RAM 7. The RAM 7 inputs (writes) the memory data by a write enable pulse 112 and a chip selecting pulse 115 when it is a write to a place (storaging place) to be instructed by a memory address 117, outputs (reads) the memory data 118 by the write enable pulse 112 and the chip select pulse 115 at the time of reading.
JP18160087A 1987-07-20 1987-07-20 Memory controller Pending JPS6425257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18160087A JPS6425257A (en) 1987-07-20 1987-07-20 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18160087A JPS6425257A (en) 1987-07-20 1987-07-20 Memory controller

Publications (1)

Publication Number Publication Date
JPS6425257A true JPS6425257A (en) 1989-01-27

Family

ID=16103642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18160087A Pending JPS6425257A (en) 1987-07-20 1987-07-20 Memory controller

Country Status (1)

Country Link
JP (1) JPS6425257A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02266446A (en) * 1989-04-05 1990-10-31 Nec Corp Memory control circuit
JPH04286796A (en) * 1991-03-18 1992-10-12 Nec Commun Syst Ltd Semiconductor integration circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02266446A (en) * 1989-04-05 1990-10-31 Nec Corp Memory control circuit
JPH04286796A (en) * 1991-03-18 1992-10-12 Nec Commun Syst Ltd Semiconductor integration circuit

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