JPS5481035A - Ic memory unit - Google Patents

Ic memory unit

Info

Publication number
JPS5481035A
JPS5481035A JP14897877A JP14897877A JPS5481035A JP S5481035 A JPS5481035 A JP S5481035A JP 14897877 A JP14897877 A JP 14897877A JP 14897877 A JP14897877 A JP 14897877A JP S5481035 A JPS5481035 A JP S5481035A
Authority
JP
Japan
Prior art keywords
memory
chips
write
access
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14897877A
Other languages
Japanese (ja)
Inventor
Kazuya Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14897877A priority Critical patent/JPS5481035A/en
Publication of JPS5481035A publication Critical patent/JPS5481035A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To enable to perform write access to other chips, while performing read access to one group of chips, in the same timing. CONSTITUTION:The IC memory unit providing a plurality of IC memory chips having a plurality of address locations and having the chip select terminal CS, write enable terminal W and read data terminal DO, are prepared and when the IC memory chip is in write mode, DO is constituted with enabling the wired logic to the DO of other IC memory chips. By grouping a plurality of IC memory chips, the control mode performing the write access to the IC memory chip of other one group in the time band performing read access to one group of IC memory chip, and the control mode selecting either one IC memory chip to a plurality of IC memory chips and performing the read or write access, are selected.
JP14897877A 1977-12-12 1977-12-12 Ic memory unit Pending JPS5481035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14897877A JPS5481035A (en) 1977-12-12 1977-12-12 Ic memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14897877A JPS5481035A (en) 1977-12-12 1977-12-12 Ic memory unit

Publications (1)

Publication Number Publication Date
JPS5481035A true JPS5481035A (en) 1979-06-28

Family

ID=15464931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14897877A Pending JPS5481035A (en) 1977-12-12 1977-12-12 Ic memory unit

Country Status (1)

Country Link
JP (1) JPS5481035A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5611676A (en) * 1979-07-06 1981-02-05 Nec Corp Semiconductor memory chip
JPS63177236A (en) * 1987-01-19 1988-07-21 Jeol Ltd Dual memory access circuit
JPS63249239A (en) * 1987-04-03 1988-10-17 Nec Corp Image storage circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5611676A (en) * 1979-07-06 1981-02-05 Nec Corp Semiconductor memory chip
JPS6214914B2 (en) * 1979-07-06 1987-04-04 Nippon Electric Co
JPS63177236A (en) * 1987-01-19 1988-07-21 Jeol Ltd Dual memory access circuit
JPS63249239A (en) * 1987-04-03 1988-10-17 Nec Corp Image storage circuit

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