JPS5461840A - Write-read control system of memory - Google Patents

Write-read control system of memory

Info

Publication number
JPS5461840A
JPS5461840A JP12835677A JP12835677A JPS5461840A JP S5461840 A JPS5461840 A JP S5461840A JP 12835677 A JP12835677 A JP 12835677A JP 12835677 A JP12835677 A JP 12835677A JP S5461840 A JPS5461840 A JP S5461840A
Authority
JP
Japan
Prior art keywords
data
memory
chip
line
memory chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12835677A
Other languages
Japanese (ja)
Inventor
Koichi Takahashi
Eishi Matsuura
Fusao Hata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12835677A priority Critical patent/JPS5461840A/en
Publication of JPS5461840A publication Critical patent/JPS5461840A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To realize the relatively simple rearrangement of data, by making it possible to write and read adroitly data to and from a plural number of memory chips by selecting addresses. CONSTITUTION:In the memory consisting of several n-bit memory chips 71 to 74, memory address line 3, memory data line 4, readwrite change-over line 5, memory-chip-number assignment address line 8, and status line 9 are connected to respective memory chips 71 to 74. During write operation, data are written to the same addresses of all memory chips 71 to 74, and during read operation, data are read out by ignoring some of address bits of each chip and by remaining address bits and chip numbers. Further, data are written during write operation, by ignoring some of address bits of each chip and by remaining address bits and chip numbers, and during read operation, data are read out from the same addresses of all memory chips.
JP12835677A 1977-10-26 1977-10-26 Write-read control system of memory Pending JPS5461840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12835677A JPS5461840A (en) 1977-10-26 1977-10-26 Write-read control system of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12835677A JPS5461840A (en) 1977-10-26 1977-10-26 Write-read control system of memory

Publications (1)

Publication Number Publication Date
JPS5461840A true JPS5461840A (en) 1979-05-18

Family

ID=14982786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12835677A Pending JPS5461840A (en) 1977-10-26 1977-10-26 Write-read control system of memory

Country Status (1)

Country Link
JP (1) JPS5461840A (en)

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