JPS5622292A - Memory element - Google Patents

Memory element

Info

Publication number
JPS5622292A
JPS5622292A JP9706379A JP9706379A JPS5622292A JP S5622292 A JPS5622292 A JP S5622292A JP 9706379 A JP9706379 A JP 9706379A JP 9706379 A JP9706379 A JP 9706379A JP S5622292 A JPS5622292 A JP S5622292A
Authority
JP
Japan
Prior art keywords
signal
signal line
bit
output
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9706379A
Other languages
Japanese (ja)
Inventor
Tominobu Yamamoto
Yoshitaka Kitano
Kenji Taniguchi
Takashi Oba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP9706379A priority Critical patent/JPS5622292A/en
Publication of JPS5622292A publication Critical patent/JPS5622292A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable to constitute the error correction circuit less number of transistors, by sectioning the memory array on chip into plural groups and commonly using one error correction circuit to plural groups in time sharing.
CONSTITUTION: The check bit generating circuit 17 produces the check bit from the data fed to the signal line 16 and outputs it to the signal line 18. At write-in, this signal is output to the signal line 21 corresponding to bit, and in other cases, the signal on the signal line 20 is output to the signal line 21 as it is. The error check circuit 22 performs the error cleck for the read-in signal output from the memory loops 1,3 or 2,4 of the group designated at the address signal A6. Further, if one bit error is present, the error bit location information is output to the signal line 23 and the signal line 24 is activated for rewrite-in of error bit. When the error correction circuit 25 receives the signal from the circuit 22, the read-in signal in one bit error correction is output to the output signal lines 15 and 20.
COPYRIGHT: (C)1981,JPO&Japio
JP9706379A 1979-07-30 1979-07-30 Memory element Pending JPS5622292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9706379A JPS5622292A (en) 1979-07-30 1979-07-30 Memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9706379A JPS5622292A (en) 1979-07-30 1979-07-30 Memory element

Publications (1)

Publication Number Publication Date
JPS5622292A true JPS5622292A (en) 1981-03-02

Family

ID=14182181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9706379A Pending JPS5622292A (en) 1979-07-30 1979-07-30 Memory element

Country Status (1)

Country Link
JP (1) JPS5622292A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621198A (en) * 1985-06-26 1987-01-07 Hitachi Ltd Semiconductor memory
JPS6376194A (en) * 1986-09-19 1988-04-06 Hitachi Ltd Semiconductor memory device
US8848465B2 (en) 2011-07-06 2014-09-30 Samsung Electronics Co., Ltd. Memory devices including selective RWW and RMW decoding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621198A (en) * 1985-06-26 1987-01-07 Hitachi Ltd Semiconductor memory
JPS6376194A (en) * 1986-09-19 1988-04-06 Hitachi Ltd Semiconductor memory device
US8848465B2 (en) 2011-07-06 2014-09-30 Samsung Electronics Co., Ltd. Memory devices including selective RWW and RMW decoding

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