JPS6376194A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the reliability of a system having an error detecting function or an error correcting function by providing a code adding circuit to add the code for detecting an error or correcting the error further to writing data after a logic operation processing or a mask processing is executed. CONSTITUTION:At a dual port memory, a parity adding circuit PC to add newly a parity bit to writing data for which the logic operation processing is executed by a logic operation unit ALU and the mask processing is executed by a data merging circuit DM is provided. For such a reason, regardless of the fact that a parity bit inputted from an external part through a data bus by the logic processing and the mask processing is not made conscious and the writing data are updated, the normal updated parity bit is added to the writing data written to the memory cell actually. Thus, the dual port memory can be connected to the system having an erroneous detecting function with the parity bit and the reliability as the system is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective for use in dual port memories and the like that have an arithmetic write function.

[Conventional technology]

Regarding dual port memory, which is used in frame panzer memory for images to display characters or figures on the screen of a CRT (cathode ray tube), and has a Nf input function for performing mask calculations, etc. For example, it is described on pages 243 to 264 of Nikkei Electronics J, March 24, 1986, published by Nikkei McGraw-Hill.

[Problem that the invention seeks to solve]

The dual port memory described above has a random access port that randomly inputs and outputs stored data in units of predetermined multiple bits, and a serial input and outputs that inputs and outputs stored data in units of word lines, that is, rows of the memory array. A serial access boat is provided. In addition, as shown in FIG. 3, this random access boat is provided with an arithmetic logic unit ALU that reads write data input from the outside via a data manual buffer DIB and from a memory cell at a specified address. Various calculations are performed on the stored data read out in advance and held in the data latch DL. The stored data held in the data latch DL and the output signal of the arithmetic logic unit 1-ALU are selected by the data merge circuit DM, and the mask data latch MD
It is selectively transmitted to the write amplifier WA according to the mask data held at L. Thereby, arithmetic processing of write data and masking processing for each focus can be performed.

However, when using dual port memory like the one above,
As shown in FIG. 3, for example, when connected to a system having an error detection function via a 9-bit data bus 101-IO2 including a parity bit and IOP, the error detection function will not function properly. That is, as described above, since this dual port memory has an arithmetic write function and a mask function, the data actually written to the memory cell is updated without being aware of the input parity bit. Therefore, the dual
Since the stored data read from the port memory does not have a normal parity bit added to it, a parity error is detected on the processing device side. This also applies when this dual port memory is connected to a system that has an error correction function using, for example, a cyclic code, and the error detection function or error correction function is meaningless. As a result, the reliability of the system is impaired.

An object of the present invention is to provide a semiconductor memory device such as a dual port memory having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
Adding a code for error detection or error correction to write data that has been subjected to logical operation processing or mask processing in a semiconductor storage device such as a dual port memory that has an operation write function and/or a mask function. A code adding circuit is provided.

[For production]

According to the above means, a normal error detection or error correction code is also added to the write data after the logical operation processing or the masking process, so that the semiconductor memory device having the operation heating function and/or the masking function The reliability of a system having an error detection function or an error correction function can be improved.

〔Example〕

Figure 2 shows a dual port system to which this invention is applied.
A block diagram of one embodiment of a memory is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dual port memory of this embodiment has a basic configuration of dynamic RAM, and includes a random access port that randomly inputs and outputs storage data in 9-bit units including parity bits, and a serial access port that inputs and outputs storage data in units of 9 bits including parity bits. A serial access port is provided for input and output. This allows the dual port memory to perform a series of serial input/output operations while simultaneously performing random access using random access ports.

The random input/output circuit RIO included in the random access boat is provided with an arithmetic logic unit ALU for performing mask operations, etc., and this arithmetic logic unit ALU
A function control circuit FC is provided for controlling. Further, this random input/output circuit RIO is provided with a data merge circuit DM and a mask data latch MDL. This makes the dual port memory in this example
It has a so-called mask function of selectively writing the output signal of the arithmetic logic unit ALLI into a designated memory cell according to the mask data held in the mask data latch MDL. Furthermore, the random input/output circuit RIO of this embodiment
includes a parity addition circuit P for adding a new parity bit to the output signal of the data merge circuit DM, that is, the write data after the arithmetic processing and mask processing.
C is provided.

The dual port memory of this embodiment receives a row address strobe signal RAS, which is used in a normal dynamic RAM, from an external device.

In addition to control signals such as column address strobe signal σAs and write enable signal W1, random access
a data transfer control signal DT10E used to control data transfer between the boat and the serial access boat;
A serial clock signal SC, which is used as a synchronizing signal during serial input/output and when a serial output control signal is used to control input/output switching of the serial access boat, is input.

The random access boat of the dual port memory in this embodiment includes, but is not limited to, nine memory arrays M-ARY 1 to M-ARY 8 and M-ARY
A sense amplifier 5AI-3A8 and SAP, a column switch C are provided corresponding to each memory array.
3WI to C5W8 and cswp are provided. In addition, memory arrays M-ARY1 to M-ARY8 and M-ARY
A random access boat column address decoder RCD and a row address decoder RD are provided in common to P. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 2 exemplarily shows the memory array M-ARY1 and its peripheral circuits. Note that the memory array M-ARYP and its peripheral circuits are used to store parity bits for error detection.

In FIG. 2, the memory array M-ARY1 has m+1 word lines WO% W arranged in the vertical direction of the figure.
m, n+1 sets of complementary data lines DO and DO=Dn-Dn arranged in the horizontal direction of the figure, and (m+ 1) x (n
+1) (Constructed by captive memory cells.

Each word line is coupled to a row address decoder RD;
One word line designated by X address signals AXO-AXi is selected.

Row address decoder RD is row address buffer R.
Complementary internal address signals xO to xi supplied from ADB (here, for example, the internal address signal axQ that is in phase with the X address signal AXO supplied from the outside and the internal address signal axQ that is in opposite phase are combined to form a complementary internal address signal a
xQ (the same applies hereinafter) is decoded, one word line designated by the X address signal AXO=AXi is selected, and set to a high level selected state. The word line selection operation by the row address decoder RD is performed by the word line selection timing signal φ supplied from the timing control circuit TC.
It is done according to X.

The row address buffer RADB receives the row address signal supplied from the address multiplexer AMX, forms complementary internal address signals axQ to axi, and supplies (A) to the row address decoder RD. , X address signals AXO to AXi for specifying row addresses and Y address signals AYO to AYi for specifying column addresses are so-called address multi-channel signals that are time-divided and supplied via the same external terminals AO to Ai. The plex method is adopted.

Therefore, the X address signals AXO to AXi are supplied to the external terminals AO to Aj in synchronization with the fall of the row address strobe signal RAS, and the Y address signals AYO to AY are supplied to the external terminals AO to Aj.
i is supplied to external terminals AO to Ai in synchronization with the fall of column address strobe signal CAS. moreover,
The dynamic RAM of this embodiment is provided with an automatic refresh mode for reading and rewriting data stored in memory cells within a predetermined cycle, and is provided with an automatic refresh mode for specifying a word line to be refreshed in this automatic refresh mode. Refresh address counter REF
C is provided.

Address multiplexer AMX receives X address signals AXO to AXi supplied from external devices via external terminals AO to At in a normal memory access mode in which timing signal φref supplied from timing control circuit TC is at low level. Select, timing signal φ
In automatic refresh mode in which ref is set to high level, refresh address signals cxQ to cxi output from refresh address counter REFC are selected.

As mentioned above, since the X address signals AXO to AXi are supplied to the external terminals Ao to Ai in synchronization with the falling edge of the row address strobe signal RAS, the row address signals are taken in by the row address buffer RADB in the evening. This is performed in accordance with a timing signal φar generated by detecting the fall of row address strobe signal RAS in timing control circuit TC.

On the other hand, complementary data line DO of memory array MARYI
-Do~Dn-σ1 is coupled on the one hand to the corresponding switch MO3FET of the column switch C3WI, and further selectively via these switch MOSFETs to the complementary common data line -g-DI (where complementary common data Non-inverted signal line CDI and inverted signal line C that constitute the line
Together with DI, the complementary common data line is expressed as D1,
The same applies hereafter).

Column switch C3WI is constituted by fi+l pairs of switch MOSFETs each coupled to a corresponding complementary data line. The other terminals of these switch MO3FET pairs are commonly coupled to a non-inverted signal line CDI or an inverted signal line CDI forming a complementary common data line. This causes the column switch C3WI to connect to the complementary data line DO
- Selectively connect 51 to Dn-true and the common complementary data line -CDI. The gates of each pair of two switches MO3FET constituting the column switch C3WI are connected in common, and are supplied with a data line selection signal formed by a column address decoder RCD for a random access boat.

The random access boat column address decoder RCD decodes the complementary internal address signals ayQ to ayi supplied from the column address buffer CADB, and selects the data line according to the data line selection timing signal φyr supplied from the timing control circuit TC. A selection signal is formed and supplied to column switches C3WI-C3W4. .

The column address buffer CADB receives a timing signal φac generated by detecting the fall of the column address strobe signal CAS in the timing control circuit TC.
Accordingly, the Y address signal AYO-AYi supplied via the external terminals AO to Ai is inputted and held, and a complementary internal address signal ayQ-ayi is formed to generate the column address decoder R for the random access boat.
Supply to CD.

Complementary data line DO of memory array M-ARY 1
On the other hand, Dn τ to Dn-L)n is coupled to a corresponding unit circuit of the sense amplifier SAI, and further coupled to a corresponding unit circuit of the data register DRI of the serial access boat.

Each unit circuit of the sense amplifier SAO has a basic configuration of a latch consisting of two cross-connected CMOS input circuits. These sense amplifier unit circuits receive a timing signal φp supplied from a timing control circuit TC.
a, the micro-read signals outputted from the memory cells to the corresponding complementary data lines are amplified and converted into binary signals of high level/low level.

A complementary common data line CDI to which complementary data lines designated by Y address signals AYO to AYi are selectively connected is coupled to a random input/output circuit RIO. This random input/output circuit RIO includes memory arrays M-ARY2 to
Complementary common data lines -CD2 to D8 and DDP provided corresponding to M-ARY8 and M-ARYP are similarly coupled.

As described later, the random input/output circuit RIO includes a data buffer DIB, a data output buffer DOB, a write amplifier circuit WA, a read amplifier circuit RA, a data latch DL, a mask data crunch MDL, an arithmetic logic unit ALU, and a data merge circuit DM. and parity addition circuit P
It is composed of C. Of these, data output buffer D
OB is in the random read mode of the dual port memory, is activated by the timing signal φrr supplied from the timing control circuit TC, and stores stored data read out via the read amplifier circuit RA.
It outputs to an external device from the input/output terminals 101 to 108 and IoP. In the random write mode of the dual port memory, the write amplifier circuit WA is activated by a timing signal φr- supplied from the timing control circuit TC, and is supplied from the data merge circuit DM via the parity addition circuit PC. The write data is converted into a binary write signal, and the complementary common data line D1~-Ω-
Transfer to D8 and CDP. In addition, the mask data raft MDL is set at the input/output terminal 101 in accordance with the timing signal φ-S supplied from the timing control circuit TC in the operation mode setting cycle of the dual port memory.
The mask data supplied from an external device is taken in through 108 and 10P.

Furthermore, in the arithmetic write cycle of the dual port memory, the arithmetic logic unit (ALU) reads data from the memory cell at a specified address and stores the data in the data latch DL.
This arithmetic logic unit ALU, which performs various arithmetic processing between the stored data held in the memory and the write data supplied from the outside, has various arithmetic modes for performing rask arithmetic, etc. Ru.

The operation mode of the arithmetic logic unit ALU is selected and specified by the function control circuit FC.
In the arithmetic mode setting cycle of the dual port memory, the arithmetic code register FOR holds the arithmetic code supplied via the address signal input external terminals AO to A3, and the arithmetic logic unit 7 decodes the arithmetic code.
It includes an operation code decoder FCD for selecting and specifying the operation mode of the ALU. Among these, the operation code register FCR receives the operation code supplied via the address input external terminals AO to A3 in accordance with the timing signal φras supplied from the timing control circuit TC in the operation mode setting cycle of the dual port memory. is input into the operational code decoder FC of the function control circuit FC.
Send to D. The operation code decoder FCD decodes these operation codes and generates operation mode selection signals amO to am.
15 and designates the operation mode of the arithmetic logic unit ALU of the random input/output circuit RIO.

These random input/output circuit RIO and function control circuit F
The configuration and operation of C will be explained in detail later.

On the other hand, the serial access port of the dual port memory in this embodiment is connected to the memory array M-ARYI-
n+l bit data register DRI- provided corresponding to each complementary data line of M-ARY8 and M-ARYP
DR8 and DRP and data selector DSL l~DS
L8 and DSLP, a pointer PNT provided in common to these nine data registers and data selectors,
It is composed of a column address decoder SCD for a serial access port and a serial input/output circuit 510. Note that a plurality of pointers PNT and serial access boat column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate. In FIG. 2, the memory array M-ARY
A data register L)R1 and a data selector DSLI corresponding to I are exemplarily shown.

The data register DRI includes n+1-bit flip-flops provided corresponding to each complementary data line of the memory array M-ARYI, and includes non-inverted signal lines and inverted signal lines of the complementary data lines corresponding to the input/output nodes of these flip-flops. Between the signal lines is a switch MO3F for data transfer.
ET is provided respectively. These switches MO3F
ET is turned on all at once by the high level of the timing signal φdt supplied from the timing control circuit TC, and the n+1 ii memory cells coupled to each flip-flop 7 block of the data register DRI and the selected word line Input and output of storage data is performed simultaneously in parallel between the two.

The input/output terminal of each bit of the data register DRI is further connected to the corresponding switch MO3 of the data selector DSL1.
Coupled to FET. The data selector DSL1 has the same configuration as the column switch C3WI described above, and selectively connects each bit of the data register DRI to the complementary common data line CD51 for serial input/output. The gates of the switch MOS FETs of each pair of data selector DSLI are connected in common, and a corresponding data register selection signal is supplied from pointer PNT.

The pointer PNT is constituted by an n+1 bit shift register, and the output terminal ps of the last bit is coupled to the input terminal of the first bit.

In the serial input/output mode of the dual port memory, the pointer PNT performs a loop-like shift operation according to the shift clock timing signal φC supplied from the timing control circuit TC. It is coupled to the corresponding output terminal of the access boat column address decoder SCD.

The serial access boat column address decoder SCD decodes the complementary internal address signals ayQ to yi supplied from the column address buffer CADB, and decodes the first bit of serial input/output specified by the Y address signals AY-0 to AYi. Only the bit of pointer PNT corresponding to is set to logic "1". That is, in the serial input/output mode, a word line is specified by the X address signals AXO to AXt, and the word line is specified by the Y address signals AYO to AY.
i specifies the first column address at which serial input/output is to be started. A logic "1" signal written to a designated bit of pointer PNT by serial access boat column address decoder SCD is shifted in a loop within pointer PNT according to timing signal φC. By shifting one logic "L" signal in this way, a high-level data register selection signal is sequentially supplied to the data selector DSLI, and each pin of the data register DRI is sequentially connected to the complementary common terminal for serial input/output. Connected to data line CDS1. Thereby, the dual port memory of this embodiment can start serial input/output of stored data from any column address.

The complementary common data line for serial input/output -CDSL is coupled to the serial input/output circuit SIO. This serial input/output circuit SIO includes data registers DR2 to DR8 and DRP and data selectors DSL2 to DSL8 and DS.
Complementary common data lines CD52 to DS8 and -CD5P for serial input/output provided corresponding to LP are similarly coupled. The serial input/output circuit SIO connects complementary common data lines DS1 to -CDS8 and DSP for serial input/output.
and serial input/output terminals 5IOI to 5108 and 5IOP
It includes nine main amplifiers, a data input cover sofa, and a data output cover sofa, which are provided correspondingly to the main amplifiers.

The data output bumper of the serial input/output circuit 510 is activated by the timing signal ψsr supplied from the timing control circuit TC in the read data transfer cycle of the dual port memory, and the data output buffer of the serial input/output circuit 510 is activated by the timing signal ψsr supplied from the timing control circuit TC. -g from S1~-CD
Read data outputted via S8 and DSP and amplified by the corresponding main amplifier is outputted to external devices from corresponding serial input/output terminals 5Io1 to 5I08 and 5IOP. In addition, the serial input/output circuit Sl0
In the serial data writing cycle of the dual port memory, the data person cover sofa is put into an operating state by the timing signal φsw supplied from the timing control circuit TC, and the corresponding serial input/output terminal 5I
Write data supplied from an external device via OI-510B and OI-510P is made into a complementary signature write signal, and is transmitted to the corresponding serial input/output complementary common data lines CDS1 to DS8 and DSP.

Timing control episode 1i! 1) TC is a row address strobe signal π, a column address strobe signal CAS, a write enable signal W, a data transfer control signal 5/σ, and a serial output control signal σ, which are supplied as control signals from the outside. The various timing signals mentioned above are formed and supplied to each circuit.The timing signal φC for synchronizing the serial input/output operation is formed by the serial clock signal SC supplied from the outside, and the timing signal φC for synchronizing the serial input/output operation is Supplied to the input/output circuit s■o.

FIG. 1 shows a circuit block diagram of an embodiment of the random input/output circuit RIO and the Ia function control circuit FC of the dual port memory of this embodiment.

In FIG. 1, data input/output terminals 101 to 108 and IOP are respectively coupled to input terminals of a data driver sofa DIB of a random input/output circuit RIO, and
are respectively coupled to output terminals of data output buffer DOB. The data input/output terminal 7DIB is composed of a 9-bit data input circuit and a data input register DIR (not shown), and has data input/output terminals 101 to 108 and an I/O terminal.
Captures and holds write data supplied via OP. Further, in a random read cycle of the dual port memory, the data output buffer DOB is put into an operating state according to the timing signal φrr supplied from the timing control circuit TC, and outputs read data transmitted via the read amplifier circuit RA. Data is output from the data input/output terminals 101 to 108 and the IOP to an external device. When the timing signal φrr is at a low level, the output of the data output buffer DOB is placed in a high impedance state.

The write data held in the data input cover sofa DIB is supplied to one input terminal of the arithmetic and logic unit 7) ALU, and is also supplied to the mask data latch ME)L. The other input terminal of the arithmetic logic Uniso I-ALU is
The output signal of data latch DL is also supplied. This data latch DL holds storage data that is read out from a pre-designated memory cell via the read amplifier circuit RA in an operation write cycle.

The arithmetic logic unit ALU is provided with various operation modes for performing operations such as AND, OR, and EXCLUSIVE OR. These calculation modes are selected by the calculation mode selection signal a m O% a m 15 supplied from the calculation code decoder FCD of the function control circuit FC.

The arithmetic logic unit ALU receives data from the outside according to these arithmetic mode selection signals.
An operation is performed between the write data held in the data input register DIR of B and the stored data read from the memory cell at the designated address and held in the data latch DL. The output signal of the arithmetic logic unit ALU is supplied to one input terminal of the data merging circuit DM.

The mask data latch MDL is a dual port
In a memory operation mode setting cycle, mask data supplied from an external device via data input/output terminals 101 to 108 and IOP is captured and held in accordance with a timing signal φIs supplied from a timing control circuit TC. The mask data held in the mask data latch MDL is supplied to corresponding bits of the data merge circuit DM as selection signals of the data merge circuit DM.

The other input terminal of the data merge circuit DM is supplied with stored data held in the data latch DL. The data merge circuit DM is constituted by a 9-bit selection circuit, and each selection circuit is supplied with mask data held in a corresponding bit of the mask data latch MDL as a selection signal. The data merge circuit DM selects the output signal of the arithmetic logic unit 1-ALU or the storage data supplied from the data latch DL according to this mask data,
It is sent to the parity addition circuit PC. That is, when the corresponding mask data is logic "1", the data merging circuit D
Each of the M selection circuits selects storage data supplied from a corresponding bit of data latch DL. Further, when the corresponding mask data is logic "0", each selection circuit of the data merge circuit DM selects the output signal of the corresponding bit of the arithmetic logic unit ALIJ. Thereby, the output signal of the arithmetic logic unit ALU is selectively transmitted to the memory cells according to the mask data. In other words, the output signal of the arithmetic logic unit ALU is masked by mask data of logic "1", and the memory cell corresponding to the masked bit is rewritten with the memory data stored in that memory cell. .

As mentioned above, in the dual port memory of this embodiment, a new parity bit is added to write data that has been subjected to arithmetic processing by the arithmetic logic unit ALU and masked by the data merging circuit DM. A parity addition circuit PC is provided for adding parity. The parity addition circuit PC is the data merging circuit DM.
It receives the output signal of and forms a parity bit for 8-bit write data. That is, although not particularly limited, a system including this dual port memory is of an odd parity type. Therefore, the parity addition circuit P
C is logic “1” included in 8-bit write data
If the number of bits in is even, the parity bit is set to logic “
If the number of logic "1" bits included in the 8-pin write data is an odd number, the parity bit is set to logic "0".

The corrupted data output from the parity addition circuit PC, including the parity bit, is transmitted to the write amplifier circuit WA. The write amplifier circuit WA is activated by the timing signal φrw supplied from the timing control circuit TC during the operation write cycle of the dual port memory, and receives a total of 9 bits of signed data supplied from the parity addition circuit PC. is used as a complementary signature input signal, and complementary common data is input to the corresponding memory cell via -CDI-CD8 and DP. timing signal φ
When rw is at a low level, the output signal of the write amplifier circuit WA is placed in a high impedance state.

The function control circuit FC is composed of an operation code register FCR and an operation code decoder FCD.

The operation code register FOR takes in and holds the operation code supplied via the address buses AO to A3 in accordance with the timing signal φms supplied from the timing control circuit TC in the operation mode setting cycle of the dual port memory.

The output signal of the operational code register NCR is supplied to the operational code decoder FCD. Arithmetic code decoder FCD
decodes the 4-bit arithmetic code to form arithmetic mode selection signals a m O to a m l5, and supplies them to the arithmetic logic unit ALU of the random input/output circuit RIO.

As described above, in the dual port memory of this embodiment, a new parity bit is added to write data that has been subjected to arithmetic processing by the arithmetic logic unit ALU and masked by the data merge circuit DM. A parity addition circuit PC is provided. For this reason, even though the write data is updated through arithmetic processing and mask processing without being aware of the parity bit input from the outside via the data bus, the write data actually written to the memory cell is is appended with updated normal parity bits. This results in
This dual port memory can be connected to a system having an error detection function using parity bits, thereby improving the reliability of the system.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a dual port memory having an arithmetic write function, the following effects can be obtained.

In other words, (in a semiconductor storage device such as a dual port memory having a D-operation write function and/or a mask function, write data that has been subjected to logical operation processing or mask processing is further subjected to error detection or error correction). By providing a code addition circuit that adds a code, it is possible to add a normal error detection code or error correction code to write data that has been subjected to logical operation processing or mask processing.

(2) The effect of item (1) above is that a semiconductor storage device such as a dual port memory having an arithmetic write function and/or a mask function can be connected to a system having an error detection function or an error correction function. is obtained.

(3) According to the above (1) and (2), dual port
An effect can be obtained in that the reliability of a system including a semiconductor storage device such as a memory and having an error detection function or an error correction function can be improved.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. For example, the system to which the dual port memory of this embodiment is connected is assumed to have an error detection function using an odd parity method.
For example, it may have an error correction function using a cyclic code. In this case, a new cyclic code is added to the updated write data between the data merge circuit DM and the write amplifier circuit WA of the dual port memory. In addition, a parity check circuit can be provided to check the write data supplied to the dual port memory via the input/output terminal and the stored data read from the memory array. may be provided. The random input/output circuit RIO in Fig. 1 is
It may have only one of the calculation write function and the mask function, and the number of calculation modes and the number of bits of write data are not limited to the embodiment shown in FIG. The dual port memory shown in the figure has several features, such as sharing the column address decoder RCD for the random access boat and the column address decoder SCD for the serial access port, or configuring each memory array with multiple memory cloaks. Various embodiments can be adopted for block configurations and combinations of control signals.

The above explanation mainly describes the invention made by the present inventor in the field of application, which is the dual port
Although the case where the present invention is applicable to a memory has been described, the present invention is not limited thereto, and can also be applied to various semiconductor storage devices such as a static type RAM. The present invention is applicable to at least a semiconductor memory device that inputs/outputs storage data in units of multiple bits and has an arithmetic write function, a mask function, or the like.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a semiconductor storage device such as a dual port memory having an arithmetic write function and/or a mask function, a code for error detection or error correction is further added to write data that has been subjected to logical arithmetic processing or mask processing. By providing a code addition circuit, it is possible to add a normal error detection code or error correction code to write data after logical operation processing or mask processing, and it is possible to add a normal error detection code or error correction code to write data after logical operation processing or mask processing. The reliability of a system including a semiconductor memory device having an error detection function or an error correction function can be improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit block diagram showing an embodiment of a random input/output circuit and a function control circuit of a dual port memory to which the present invention is applied, and FIG. FIG. 3 is a circuit block diagram of a random input/output circuit and a function control circuit of a conventional dual port memory. It is. RIO...Random input/output circuit, FC...Function control circuit, PC...Parity addition circuit, DIB...Data person cover sofa, DOB...Data output cover sofa, D
L...Data latch, MDL...Mask data latch 7
ALU... Arithmetic logic unit, DM... Data merging circuit, RA... Read amplification circuit, WA...
Write amplifier circuit, FCR... operation code register,
FCD... Arithmetic code decoder. M-ARY l...Memory array, SAI...
Sense amplifier, C3WI...column inch, DRI
...Data register, DSLI...Data selector, PNT...Pointer, RD...Row address decoder, RCD...Column address decoder for random access port, SCD...Serial access・Port column address decoder, CADB...
・Column address buffer, RADB... Row address buffer, AMX... Address multiplexer, S
lO: Serial input/output circuit, TC: Timing control circuit, REFC: Refresh address counter. Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A logic operation circuit that performs an operation on stored data read from a designated address and write data supplied from the outside, and/or a mask circuit that selectively masks the write data according to mask data. , a code addition circuit that receives the output signal of the logic operation circuit or the mask circuit and forms a code for error or error correction; and a code addition circuit that receives the output signal of the logic operation circuit or the mask circuit and the output signal of the code addition circuit and designates it. 1. A semiconductor memory device comprising: a write circuit for writing to a specified address. 2. The semiconductor storage device is a dual port memory, and the logical operation circuit has a data latch circuit that holds the stored data and a data latch circuit that holds the stored data according to an externally supplied operation mode signal. The mask circuit includes an arithmetic logic unit that performs various operations on the write data, and the mask circuit includes a mask data latch circuit that holds the mask data supplied from the outside, and an output signal of the data latch circuit or the arithmetic logic unit that stores the mask data. 2. The semiconductor memory device according to claim 1, further comprising a data merging circuit that selectively transmits data to the code adding circuit according to mask data held in a latch circuit.