JP2009070456A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can reduce a testing cost. <P>SOLUTION: A SDRAM outputs a test signal QT0 which indicates whether data signals Q0 to Q3 read out from four memory cells MC of a memory mat M0 coincide or not to an data input/output terminal DQ0 among the data input/output terminals DQ0 to DQ3 in a first testing mode, and sequentially outputs the data signals Q0 to Q3 to the data input/output terminal DQ0 in a second testing mode. Therefore, it is possible to determine whether the four memory cells are correct or not and four output buffers 4 corresponding to the data input/output terminals DQ0 to DQ3 are correct or not, only by connecting the data input/output terminal DQ0 to a tester, thereby reducing the testing cost. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a test mode.

  Since semiconductor memory for SIP (System In Package) is often shipped to customers in the wafer state, testing of the semiconductor memory in the wafer state (hereinafter referred to as wafer test) is an important factor for ensuring the quality. It has become. Wafer testing is divided into pre-test and post-test. In the pretest, a number of tests are performed to detect defective bits in the semiconductor memory. The defective bit detected by the pretest is relieved by fuse blow. The post test is for testing a repaired chip and is positioned as a final test in a wafer state.

  In such a wafer test, it is necessary to increase the number of semiconductor memories that can be simultaneously connected to one tester (hereinafter referred to as the same measurement number) to reduce the test cost. A technique often used to increase the number of measurements is a multi-bit test. When testing a semiconductor memory that has multiple data input / output terminals and can simultaneously write multiple bits of data signals to multiple memory cells and simultaneously read multiple data signals from multiple memory cells, multiple Of these data input / output terminals, only predetermined data input / output terminals are connected to the tester.

During a write operation, data signals input to predetermined data input / output terminals are simultaneously written into a plurality of memory cells via an input buffer. Further, during the read operation, it is determined whether or not the logics of a plurality of data signals simultaneously read from a plurality of memory cells match, and a signal indicating the determination result is input to a predetermined data input via the output buffer. Output from the output terminal. When the logic of a plurality of data signals read from a plurality of memory cells to which the same logic data signal has been written is matched, the memory cells are determined to be normal. At least one of is determined to be defective. According to such a multi-bit test, it is possible to reduce the test cost by increasing the number of measurements (for example, see Patent Document 1).
JP-A-10-228800

  However, in the conventional multi-bit test, circuits corresponding to the predetermined data input / output terminals are tested, but circuits corresponding to other data input / output terminals are not tested. For this reason, the final test of the wafer test must be performed with all the data input / output terminals connected to the tester, and the test is expensive.

  Therefore, a main object of the present invention is to provide a semiconductor memory device capable of reducing a test cost.

A semiconductor memory device according to the present invention includes a memory array, a read circuit, a match / mismatch determination circuit, first to Nth output terminals, and an output circuit. The memory array includes a plurality of memory cell groups each having first to Nth memory cells (where N is an integer equal to or greater than 2). The read circuit reads the first to Nth data signals from the first to Nth memory cells belonging to the selected memory cell group among the plurality of memory cell groups. The match / mismatch determination circuit determines whether or not the logic levels of the first to Nth data signals match, and outputs a test signal indicating the determination result. The output circuit receives the first to N-th data signals and the test signal, and outputs the first to N-th data signals to the first to N-th output terminals, respectively, during the normal operation. When a test signal is output to a predetermined n-th output terminal (where n is an integer between 1 and N) among the first to N-th output terminals, and in the second test mode, The first to Nth data signals are sequentially output to the nth output terminal.

  Another semiconductor memory device according to the present invention includes a memory array, first to Nth input terminals, an input circuit, and a write circuit. The memory array includes a plurality of memory cell groups each having first to Nth memory cells (where N is an integer equal to or greater than 2). During normal operation, the input circuit supplies the first to Nth data signals input via the first to Nth input terminals to the first to Nth nodes, respectively, and during the first test mode. , A data signal applied via a predetermined nth input terminal (where n is an integer of 1 to N) among the first to Nth input terminals. In the second test mode, the first to Nth data signals sequentially input via the nth input terminal are applied to the first to Nth nodes, respectively. The write circuit writes N data signals applied to the first to Nth nodes to the first to Nth memory cells belonging to the selected memory cell group among the plurality of memory cell groups, respectively. .

  In the semiconductor memory device according to the present invention, in the first test mode, the first test signal indicating whether or not the first to Nth data signals read from the first to Nth memory cells coincide with each other is the first. Are output to the nth output terminal of the Nth output terminals, and the first to Nth data signals are sequentially output to the nth output terminal in the second test mode. Therefore, it is determined whether or not the first to Nth memory cells are normal in a state where only the nth output terminal is connected to the tester, and whether or not the circuit corresponding to the first to Nth output terminals is normal. It is possible to reduce the test cost.

  Further, in another semiconductor memory device according to the present invention, in the first test mode, the data signal supplied through the nth input terminal among the first to Nth input terminals is supplied to the first to first data signals. In the second test mode, the first to Nth data signals sequentially input via the nth input terminal are written to the first to Nth memory cells, respectively. Therefore, in a state where only the nth input terminal is connected to the tester, one data signal is written to the first to Nth memory cells, and the first to Nth data signals are respectively written to the first to Nth memories. The cell can be written, and the test cost can be reduced.

[Embodiment 1]
FIG. 1 is a circuit block diagram showing a portion related to data reading of an SDRAM (Synchronous Dynamic Randam Access Memory) according to Embodiment 1 of the present invention. In FIG. 1, the SDRAM includes four memory mats M0 to M3 and 16 data input / output terminals DQ0 to DQ15. Data input / output terminals DQ0 to DQ3, DQ4 to DQ7, DQ8 to DQ11, DQ12 to DQ15 are provided corresponding to memory mats M0 to M3, respectively.

The memory mat M0 includes a memory array MA, a row decoder 6, a column decoder 7, and a sense amplifier + input / output control circuit 8, as shown in FIG. Memory array MA includes a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of bits provided corresponding to the plurality of columns, respectively. Line pair BLP. The memory cell MC is a well-known one composed of one transistor and one capacitor, and stores a 1-bit data signal. In each row, a plurality of memory cells MC are grouped in advance by four. Each memory cell group is assigned a unique address in advance. Each word line WL is assigned a unique row address in advance. The plurality of bit line pairs BLP are each divided into a plurality of bit line groups corresponding to a plurality of memory cell groups, and a unique column address is assigned to each bit line group in advance. The address of each memory cell group is specified by a row address and a column address.

  The row decoder 6 selects one of the plurality of word lines WL according to the row address signal RA, sets the selected word line WL to the selection level, and sets each memory cell in the row corresponding to the word line WL. Activate MC. The column decoder 7 selects one of the plurality of bit line groups according to the column address signal CA.

  In the write operation, the sense amplifier + input / output control circuit 8 sends 4-bit write data signals D0 to D3 via four bit line pairs BLP belonging to the bit line group selected by the column decoder 7. Each of the four memory cells MC belonging to the memory cell group activated by the decoder 6 is written.

  In the read operation, the sense amplifier + input / output control circuit 8 passes through the four bit line pairs BLP belonging to the bit line group selected by the column decoder 7 to the memory cell group activated by the row decoder 6. Four-bit read data signals Q0 to Q3 are read from the four memory cells MC to which they belong, respectively.

  Returning to FIG. 1, the memory mats M1 to M3 have the same configuration as the memory mat M0. Data signals Q4 to Q7, Q8 to Q11, and Q12 to Q15 are read from the memory mats M1 to M3, respectively. Corresponding to each of the memory mats M0 to M3, an amplifier 1, a match / mismatch determination circuit 2, a switch 3, four output buffers 4, and a shift register circuit 5 are provided.

  Data signals Q0 to Q3 read from the memory mat M0 are amplified by the corresponding amplifier 1. The match / mismatch determination circuit 2 determines whether the logic of the 4-bit data signals Q0 to Q3 amplified by the amplifier 1 matches, and outputs a test signal QT0 indicating the determination result. As shown in FIG. 3, the match / mismatch determination circuit 2 includes an ER-OR gate 2a. The ER-OR gate 2a receives 4-bit data signals Q0 to Q3 read from the corresponding memory mat M0 and amplified by the amplifier 1. The output signal QT0 of the ER-OR gate 2a is at "L" level when the logic of the 4-bit data signals Q0 to Q3 matches, and at "H" level when they do not match.

  When the logic of the data signals Q0 to Q3 read from the four memory cells MC into which the data signals D0 to D3 having the same logic are written coincides and the output signal QT0 of the ER-OR gate 2a becomes the “L” level, These four memory cells MC are determined to be normal. However, when the logics of the data signals Q0 to Q3 read from the four memory cells MC do not match and the output signal QT0 of the ER-OR gate 2a becomes the “H” level, the four memory cells MC At least one of the memory cells MC is determined to be defective. Note that the memory cell group including the defective memory cell MC is replaced with a spare memory cell group in a later step.

Similarly, the match / mismatch determination circuit 2 corresponding to the memory mat M1 determines whether or not the logic of the 4-bit data signals Q4 to Q7 amplified by the amplifier 1 matches, and a test signal indicating the determination result QT4 is output. The match / mismatch determination circuit 2 corresponding to the memory mat M2 determines whether or not the logics of the 4-bit data signals Q8 to Q11 amplified by the amplifier 1 match, and outputs a test signal QT8 indicating the determination result. To do. The match / mismatch determination circuit 2 corresponding to the memory mat M3 determines whether or not the logic of the 4-bit data signals Q12 to Q15 amplified by the amplifier 1 matches, and outputs a test signal QT12 indicating the determination result. To do.

  The switch 3 corresponding to the memory mat M0 receives the output signal QT0 of the coincidence / mismatch judgment circuit 2 and the read data signal Q0 amplified by the amplifier 1, and in the first test mode, the switch 3 receives the test signal QT0. 4 and the read data signal Q0 is applied to the output buffer 4 in the subsequent stage during normal operation and in the second test mode. The output buffer 4 transmits the signal QT0 or Q0 given from the switch 3 to the shift register circuit 5 at the subsequent stage. Each of the other read data signals Q1 to Q3 amplified by the corresponding amplifier 1 is applied to the corresponding shift register circuit 5 via the corresponding output buffer 4.

  Similarly, switch 3 corresponding to memory mat M1 receives output signal QT4 from coincidence / noncoincidence decision circuit 2 and read data signal Q4 amplified by amplifier 1, and receives test signal QT4 in the subsequent stage in the first test mode. The read data signal Q4 is applied to the subsequent output buffer 4 during normal operation and in the second test mode. The output buffer 4 transmits the signal QT4 or Q4 given from the switch 3 to the shift register circuit 5 at the subsequent stage. Each of the other read data signals Q4 to Q7 amplified by the corresponding amplifier 1 is applied to the corresponding shift register circuit 5 through the corresponding output buffer 4.

  The switch 3 corresponding to the memory mat M2 receives the output signal QT8 of the coincidence / noncoincidence determination circuit 2 and the read data signal Q8 amplified by the amplifier 1, and receives the test signal QT8 in the subsequent stage in the first test mode. The read data signal Q8 is applied to the output buffer 4 and is supplied to the output buffer 4 in the subsequent stage during normal operation and in the second test mode. The output buffer 4 transmits the signal QT8 or Q8 supplied from the switch 3 to the shift register circuit 5 at the subsequent stage. Each of the other read data signals Q9 to Q11 amplified by the corresponding amplifier 1 is applied to the corresponding shift register circuit 5 via the corresponding output buffer 4.

  The switch 3 corresponding to the memory mat M3 receives the output signal QT12 of the coincidence / non-coincidence decision circuit 2 and the read data signal Q12 amplified by the amplifier 1, and receives the test signal QT12 in the subsequent stage in the first test mode. The read data signal Q12 is applied to the output buffer 4 and supplied to the output buffer 4 in the subsequent stage during normal operation and in the second test mode. The output buffer 4 transmits the signal QT12 or Q12 supplied from the switch 3 to the shift register circuit 5 at the subsequent stage. Each of the other read data signals Q13 to Q15 amplified by the corresponding amplifier 1 is applied to the corresponding shift register circuit 5 via the corresponding output buffer 4.

  FIG. 4 is a circuit diagram showing a configuration of the output buffer 4. 4, output buffer 4 includes an inverter 10 that inverts activation signal φA, a NAND gate 11 that receives read data signal (for example, Q0) and activation signal φA, an output signal of inverter 10, and read data signal Q0. And a NOR gate 12 for receiving. The output buffer 4 is connected between the power supply potential VDD line and the output node N13, the P channel MOS transistor 13 whose gate receives the output signal of the NAND gate 11, the output node N13 and the ground potential VSS. And an N channel MOS transistor 14 having a gate connected to the line and receiving an output signal of NOR gate 12.

When activation signal φA is at the activation level “H” level, each of NAND gate 11 and NOR gate 12 operates as an inverter. When data signal Q0 is at "H" level, P channel MOS transistor 13 is rendered conductive, N channel MOS transistor 14 is rendered non-conductive, and output node N13 is at "H" level. When data signal Q0 is at "L" level, P channel MOS transistor 13 is rendered non-conductive, N channel MOS transistor 14 is rendered conductive, and output node N13 is at "L" level. Therefore, the logic level of read data signal Q0 is transmitted to output node N13 as it is.

  When activation signal φA is at “L” level, the output signal of NAND gate 11 is fixed at “H” level, P channel MOS transistor 13 is turned off, and the output signal of NOR gate 12 is at “L” level. N channel MOS transistor 14 becomes non-conductive. Therefore, output node N13 is set to a high impedance state regardless of the logic level of read data signal Q0.

  Returning to FIG. 1, shift register circuit 5 corresponding to memory mat M0 provides read data signals Q0-Q3 to data input / output terminals DQ0-DQ3, respectively, during normal operation, and matches / mismatches are determined in the first test mode. Output signal QT0 of circuit 2 is applied to data input / output terminal DQ0, and read data signals Q0 to Q3 are sequentially output to data input / output terminal DQ0 in the second test mode.

  The shift register circuit 5 corresponding to the memory mat M1 supplies read data signals Q4 to Q7 to the data input / output terminals DQ4 to DQ7, respectively, during normal operation, and the output of the coincidence / mismatch determination circuit 2 during the first test mode. Signal QT4 is applied to data input / output terminal DQ4, and read data signals Q4-Q7 are sequentially output to data input / output terminal DQ4 in the second test mode.

  Shift register circuit 5 corresponding to memory mat M2 provides read data signals Q8-Q11 to data input / output terminals DQ8-DQ11, respectively, during normal operation, and outputs from match / mismatch determination circuit 2 in the first test mode. Signal QT8 is applied to data input / output terminal DQ8, and read data signals Q8-Q11 are sequentially output to data input / output terminal DQ8 in the second test mode.

  Shift register circuit 5 corresponding to memory mat M3 provides read data signals Q12-Q15 to data input / output terminals DQ12-DQ15, respectively, during normal operation, and outputs from match / mismatch determination circuit 2 in the first test mode. Signal QT12 is applied to data input / output terminal DQ12, and read data signals Q12-Q15 are sequentially output to data input / output terminal DQ12 in the second test mode.

  FIG. 5 is a circuit diagram showing a configuration of shift register circuit 5 corresponding to memory mat M0. In FIG. 5, the shift register circuit 5 includes switches 20 to 24 and registers 25 to 28. The common terminal 20 c of the switch 20 receives the signal Q 0 or QT 0, one switching terminal 20 a is connected to one switching terminal 21 a of the switch 21, and the other switching terminal 20 b is connected to the parallel input terminal of the register 25. The common terminal 21 c of the switch 21 is connected to the data input / output terminal DQ 0, and the other switching terminal 21 b is connected to the output terminal of the register 25.

The read data signal Q1 is directly input to the data input / output terminal DQ1, and is also input to the parallel input terminal of the register 26 via the switch 22. The read data signal Q2 is directly input to the data input / output terminal DQ2 and is input to the parallel input terminal of the register 27 via the switch 23. Read data signal Q3 is directly input to data input / output terminal DQ3 and is also input to the parallel input terminal of register 28 via switch 24. The serial input terminals of registers 25-27 receive the output signals of registers 26-28, respectively. The shift register circuit 5 corresponding to the memory mats M1 to M3 has the same configuration as the shift register circuit 5 corresponding to the memory mat M0 except that the input signal and the data input / output terminal to be connected are different.

  Next, the operation of this SDRAM will be described. During normal operation, as shown in FIG. 6, the terminals 20a and 20c of the switch 20 of the level shift circuit 5 are conductive, the terminals 21a and 21c of the switch 21 are conductive, and the switches 22 to 24 are nonconductive. Put into a state. Further, the switching terminal on the right side of each switch 3 in FIG. 1 is electrically connected to the common terminal. In this case, as shown in FIGS. 7A to 7D, the 16-bit data signals Q0 to Q15 read from the four memory mats M0 to M3 are synchronized with the rising edge of the clock signal CLK. Are respectively output from data input / output terminals DQ0 to DQ15.

  In the first test mode (degeneration mode), only four data input / output terminals DQ0, DQ4, DQ8, and DQ12 out of the 16 data input / output terminals DQ0 to DQ15 are connected to the tester. The switches 20 to 24 of the level shift circuit 5 are set to the same state as in the normal operation shown in FIG. In addition, the switching terminal on the left side of each switch 3 in FIG. 1 is electrically connected to the common terminal. In this case, as shown in FIGS. 8A to 8D, the output signals QT0, QT4, QT8, and QT12 of the four match / mismatch determination circuits 2 corresponding to the four memory mats M0 to M3 are clock signals. In synchronization with the rising edge of CLK, data is output from the data input / output terminals DQ0, DQ4, DQ8, and DQ12 to the tester.

  When test signals QT0, QT4, QT8, and QT12 are all at "L" level, it is determined that the selected 16 memory cells MC are normal. When test signals QT0, QT4, QT8, or QT12 are at “H” level, it is determined that at least one of the four memory cells MC corresponding to the test signal at “H” level is defective. .

  In the second test mode, only four data input / output terminals DQ0, DQ4, DQ8, and DQ12 out of the 16 data input / output terminals DQ0 to DQ15 are connected to the tester. 9, the terminals 20b and 20c of the switch 20 of the level shift circuit 5 are electrically connected, the terminals 21b and 21c of the switch 21 are electrically connected, and each of the switches 22 to 24 is made conductive. Further, the switching terminal on the right side of each switch 3 in FIG. 1 is electrically connected to the common terminal. In this case, as shown in FIGS. 10A to 10E, in response to the rising edge of the first cycle of the clock signal CLK, the data signals Q0 to Q3 are output to the data input / output terminals DQ0 to DQ3, respectively. And are taken into the registers 25 to 28, respectively.

  Next, in response to the rising edge of the second cycle of the clock signal CLK, the data signals Q1 to Q3 held in the registers 26 to 28 are shifted to the registers 25 to 27, respectively, and the data signal Q1 is transferred from the register 25 to the data. Output to the input / output terminal DQ0. Next, in response to the rising edge of the third cycle of the clock signal CLK, the data signals Q2 and Q3 held in the registers 26 and 27 are shifted to the registers 25 and 26, respectively, and the data signal Q2 is input from the register 25 to the data. It is output to the output terminal DQ0. Further, in response to the rising edge of the fourth cycle of the clock signal CLK, the data signal Q3 held in the register 26 is shifted to the register 25, and the data signal Q3 is output from the register 25 to the data input / output terminal DQ0. . In this way, the data signals Q0 to Q3 read from the memory mat M0 are sequentially output from the data input / output terminal DQ0.

  Similarly, data signals Q4 to Q7 read from the memory mat M1 are sequentially output from the data input / output terminal DQ4. Data signals Q8 to Q11 read from the memory mat M2 are sequentially output from the data input / output terminal DQ8. Data signals Q12 to Q15 read from the memory mat M3 are sequentially output from the data input / output terminal DQ12.

  When the selected normal memory cell MC outputs a data signal having the same logic as the data signal written to the memory cell MC, it is determined that the output buffer 4 corresponding to the memory cell MC is normal. When the selected normal memory cell MC outputs a data signal having a logic different from the data signal written to the memory cell MC, the output buffer 4 corresponding to the memory cell MC is determined to be defective.

  In the second test mode, only a test using a simple data pattern is sufficient. This is because the memory array MA having a complicated configuration has already been tested in the first test mode, and only the output buffer 4 having a simple configuration needs to be tested in the second test. Moreover, four cycles are required to read the data signals of the four memory cells MC from one memory mat, which takes time.

  In the first embodiment, the selected 16 memory cells with only four data input / output terminals DQ0, DQ4, DQ8, DQ12 out of the 16 data input / output terminals DQ0 to DQ15 connected to the tester. It is possible to determine whether the MC is normal and to determine whether the 16 output buffers 4 corresponding to the 16 data input / output terminals DQ0 to DQ15 are normal, thereby reducing the test cost. Can do.

  FIG. 11 is a block diagram showing a portion related to data writing of an SDRAM as a comparative example of the first embodiment, and is a diagram to be compared with FIG. Referring to FIG. 11, this SDRAM is different from the SDRAM of FIG. 1 in that there is no shift register circuit 5. Therefore, in the comparative example, since the second test mode cannot be performed, in order to test whether or not the 16 output buffers 4 are normal, 16 data input / output terminals DQ0 to DQ15 are connected to a tester and 16 It is necessary to read the data signals Q0 to Q15 from the memory cells MC. For this reason, the number of SDRAMs that can be connected to one tester and can be tested simultaneously is reduced, and the test cost is increased.

[Embodiment 2]
FIG. 12 is a circuit block diagram showing a portion related to data writing of the SDRAM according to the second embodiment of the present invention. In FIG. 12, the SDRAM includes four memory mats M0 to M3 and 16 data input / output terminals DQ0 to DQ15. The configuration of each of the memory mats M0 to M3 is as described with reference to FIG. Data input / output terminals DQ0 to DQ3, DQ4 to DQ7, DQ8 to DQ11, DQ12 to DQ15 are provided corresponding to memory mats M0 to M3, respectively. A shift register circuit 30, four input buffers 31 to 34, a switching circuit 35, and a write driver (WD) 36 are provided corresponding to each of the memory mats M0 to M3.

  FIG. 13 is a circuit diagram showing a configuration of shift register circuit 30 corresponding to memory mat M0. In FIG. 13, the shift register circuit 30 includes switches 40 to 44 and registers 45 to 48. The common terminal 40 c of the switch 40 is connected to the data input / output terminal DQ 0, one switching terminal 40 a is connected to one switching terminal 41 a of the switch 41, and the other switching terminal 40 b is connected to the input terminal of the register 45. The common terminal 41 c of the switch 41 is connected to the input buffer 31, and the other switching terminal 41 b is connected to the parallel output terminal of the register 45.

The input node of the input buffer 32 is directly connected to the data input / output terminal DQ 1 and is connected to the parallel output terminal of the register 46 via the switch 42. The input node of the input buffer 33 is directly connected to the data input / output terminal DQ 2 and is connected to the parallel output terminal of the register 47 through the switch 43. The input node of the input buffer 34 is directly connected to the data input / output terminal DQ 3 and is connected to the parallel output terminal of the register 48 via the switch 44. The serial output terminals of the registers 45 to 47 are connected to the input terminals of the registers 46 to 48, respectively.

  During normal operation, as shown in FIG. 14, the terminals 40a and 40c of the switch 40 of the level shift circuit 30 are conductive, the terminals 41a and 41c of the switch 41 are conductive, and the switches 42 to 44 are nonconductive. Put into a state. In this case, write data signals D0-D3 applied to data input / output terminals DQ0-DQ3 are applied to input buffers 31-34, respectively.

  In the first test mode (degeneration mode), only one data input / output terminal DQ0 out of the four data input / output terminals DQ0 to DQ3 is connected to the tester. The switches 40 to 44 of the level shift circuit 5 are set to the same state as in the normal operation shown in FIG. In this case, test signal DT0 applied to data input / output terminal DQ0 is applied to input buffer 31.

  In the second test mode, only one data input / output terminal DQ0 out of the four data input / output terminals DQ0 to DQ3 is connected to the tester. As shown in FIG. 15, the terminals 40b and 40c of the switch 40 of the level shift circuit 30 are conducted, the terminals 41b and 41c of the switch 41 are conducted, and each of the switches 42 to 44 is turned on. In this case, the write data signals D3 to D0 are sequentially input to the data input / output terminal DQ0 in synchronization with the clock signal. Write data signal D3 is sequentially shifted to registers 45-48 in synchronization with the clock signal. Write data signal D2 is sequentially shifted to registers 45-47 in synchronization with the clock signal. Write data signal D1 is sequentially shifted to registers 45 and 46 in synchronization with the clock signal. Write data signal D0 is held in register 45 in synchronization with the clock signal. In this way, the write data signals D0 to D3 are held in the registers 45 to 48, respectively, and supplied from the registers 45 to 48 to the input buffers 31 to 34.

  The shift register circuit 30 corresponding to the memory mats M1 to M3 has the same configuration as the shift register circuit 5 corresponding to the memory mat M0 except that the data input / output terminals to be connected are different.

  That is, shift register circuit 30 corresponding to memory mat M1 passes write data signals D4 to D7 input from outside via data input / output terminals DQ4 to DQ7 to input buffers 31 to 34, respectively, during normal operation. Let The shift register circuit 30 passes the test signal DT4 input from the tester via the data input / output terminal DQ4 to the input buffer 31 in the first test mode, and receives data from the tester in the second test mode. Write data signals D4 to D7 sequentially input via output terminal DQ4 are held and applied to input buffers 31 to 34, respectively.

  Further, the shift register circuit 30 corresponding to the memory mat M2 passes the write data signals D8 to D11 input from the outside via the data input / output terminals DQ8 to DQ11 to the input buffers 31 to 34, respectively, during normal operation. Let The shift register circuit 30 passes the test signal DT8 input from the tester via the data input / output terminal DQ8 to the input buffers 31 to 34 in the first test mode, and from the tester in the second test mode. Write data signals D8 to D11 sequentially input via data input / output terminal DQ8 are held and applied to input buffers 31 to 34, respectively.

Further, the shift register circuit 30 corresponding to the memory mat M3 passes the write data signals D12 to D15 input from the outside via the data input / output terminals DQ12 to DQ15 to the input buffers 31 to 34, respectively, during normal operation. Let The shift register circuit 30
In the first test mode, the test signal DT12 input from the tester through the data input / output terminal DQ12 is passed through the input buffer 31, and in the second test mode, the tester sequentially inputs the data through the data input / output terminal DQ12. Write data signals D12 to D15 to be held are applied to input buffers 31 to 34, respectively.

  Input buffers 31 to 34 transmit signals applied via corresponding data input / output terminals and shift register circuit 30 to corresponding switching circuit 35.

  Switching circuit 35 corresponding to memory mat M0 receives write data signals D0-D3 input via corresponding input buffers 31-34 at output nodes N1-N4, respectively, during normal operation and in the second mode. give. In the first test mode, switching circuit 35 provides test signal DT0 input via input buffer 31 to each of output nodes N1-N4.

  Further, switching circuit 35 corresponding to memory mat M1 receives write data signals D4 to D7 input via corresponding input buffers 31 to 34, respectively, at output nodes N1 to N1 during normal operation and in the second mode. Give to N4. In the first test mode, switching circuit 35 provides test signal DT4 input via input buffer 31 to each of output nodes N1-N4.

  The switching circuit 35 corresponding to the memory mat M2 receives the write data signals D8 to D11 input via the corresponding input buffers 31 to 34 during the normal operation and the second mode, respectively, as output nodes N1 to N1. Give to N4. In the first test mode, switching circuit 35 provides test signal DT8 input via input buffer 31 to each of output nodes N1-N4.

  In addition, switching circuit 35 corresponding to memory mat M3 receives write data signals D12-D15 input via corresponding input buffers 31-34 in output node N1-in the normal operation and in the second mode, respectively. Give to N4. In the first test mode, switching circuit 35 provides test signal DT12 input via input buffer 31 to each of output nodes N1-N4.

  The ride driver 36 corresponding to the memory mat M0 receives the write data signals D0 to D3 supplied from the corresponding switching circuit 36 in the four selected memories of the memory mat M0 during the normal operation and the second mode. Write to each cell MC. In the first test mode, the write driver 36 writes the four test signals DT0 supplied from the switching circuit 36 to the four selected memory cells MC of the memory mat M0.

  The ride driver 36 corresponding to the memory mat M1 receives the write data signals D4 to D7 supplied from the corresponding switching circuit 36 during the normal operation and the second mode. Each memory cell MC is written. In the first test mode, the write driver 36 writes the four test signals DT4 supplied from the switching circuit 36 to the four selected memory cells MC of the memory mat M1, respectively.

  In the normal operation and the second mode, the ride driver 36 corresponding to the memory mat M2 receives the write data signals D8 to D11 supplied from the corresponding switching circuit 36 in the selected memory mat M2. Each memory cell MC is written. In the first test mode, the write driver 36 writes the four test signals DT4 given from the switching circuit 36 to the four selected memory cells MC of the memory mat M2, respectively.

  In the normal operation and the second mode, the ride driver 36 corresponding to the memory mat M3 receives the write data signals D12 to D15 supplied from the corresponding switching circuit 36 in the selected memory mat M3. Each memory cell MC is written. In the first test mode, the write driver 36 writes the four test signals DT12 supplied from the switching circuit 36 into the selected four memory cells MC of the memory mat M3.

  Next, the operation of this SDRAM will be described. During normal operation, write data signals D0 to D3, D4 to D7, D8 to D11, and D12 to D15 are applied to data input / output terminals DQ0 to DQ3, DQ4 to DQ7, DQ8 to DQ11, and DQ12 to DQ15, respectively. Data signals D0 to D3, D4 to D7, D8 to D11, and D12 to D15 are written in four selected memory cells MC of memory mats M0 to M3, respectively.

  In the first test mode (degeneration mode), test signals DT0, DT4, DT8, and DT12 are applied to data input / output terminals DQ0, DQ4, DQ8, and DQ12, respectively. Test signals DT0, DT4, DT8, and DT12 are written to four selected memory cells MC of memory mats M0 to M3, respectively.

  In the second test mode, as shown in FIGS. 16A to 16K, the write data signal D3 is applied to the data input / output terminals DQ0, DQ4, DQ8, and DQ12 in one cycle period of the clock signal CLK, respectively. , D7, D11, and D15 are supplied to the corresponding shift register circuit 30, respectively. Next, in the two-cycle period of the clock signal CLK, the write data signals D2, D6, D10, and D14 are applied to the data input / output terminals DQ0, DQ4, DQ8, and DQ12, respectively, and each is taken into the corresponding shift register circuit 30. At the same time, the write data signals D 3, D 7, D 11, D 15 are shifted in the shift register circuit 30.

  Next, write data signals D1, D5, D9, and D13 are applied to data input / output terminals DQ0, DQ4, DQ8, and DQ12, respectively, and taken into the corresponding shift register circuit 30 during the three-cycle period of clock signal CLK. At the same time, the write data signals D3, D7, D11, D15; D2, D6, D10, D14 are shifted in the shift register circuit 30.

  Next, in the four-cycle period of the clock signal CLK, write data signals D0, D4, D8, and D10 are applied to the data input / output terminals DQ0, DQ4, DQ8, and DQ12, respectively, and each is taken into the corresponding shift register circuit 30. At the same time, the write data signals D1, D5, D9, D13; D3, D7, D11, D15; D2, D6, D10, D14 are shifted in the shift register circuit 30. As a result, the write data signals D0 to D3, D4 to D7, D8 to D11, and D12 to the nodes N1 to N4 corresponding to the data input / output terminals DQ0 to DQ3, DQ4 to DQ7, DQ8 to DQ11, and DQ12 to DQ15, respectively. D15 is given. These data signals D0 to D3, D4 to D7, D8 to D11, and D12 to D15 are respectively written in the selected four memory cells MC of the memory mats M0 to M3.

  In the second embodiment, only four data input / output terminals DQ0, DQ4, DQ8, and DQ12 out of the 16 data input / output terminals DQ0 to DQ15 are connected to the tester, and the test signals DT0, DT4, DT8, DT12 can be written to four selected memory cells MC of memory mats M0 to M3, and 16-bit data signals D0 to D15 can be written to selected 16 memory cells MC, thereby reducing test costs. Can be achieved.

[Embodiment 3]
FIG. 17 is a block diagram showing the overall structure of the SDRAM according to the third embodiment of the present invention. 17, the SDRAM includes 32 data input / output terminals DQ0 to DQ31, four memory units 50 to 53, four shift register circuits 60 to 63, and a control unit 64. Data input / output terminals DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, and DQ24 to DQ31 are provided corresponding to the memory units 50 to 53, respectively. All data input / output terminals DQ0 to DQ31 are used in the normal operation, and only four data input / output terminals DQ7, DQ15, DQ23, and DQ31 are used in the test mode.

  As shown in FIG. 18, memory unit 50 includes an input / output buffer 54, a write / read circuit 55, and a memory mat 56. Input / output buffer 54 includes eight input buffers for transmitting 8-bit write data signals D0-D7 applied to data input / output terminals DQ0-DQ7 to write / read circuit 55, and write / read circuit 55. And eight output buffers for transmitting the read 8-bit data signals Q0 to Q7 to the data input / output terminals DQ0 to DQ7. The memory mat 56 has the same configuration as the memory mat M0 shown in FIG. However, in memory mat 56, each memory cell group includes eight memory cells MC.

  Write / read circuit 55 selects 8-bit data signals D0-D7 applied via data input / output terminals DQ0-DQ7 and input / output buffer 54 in memory mat 56 during a normal write operation. In addition, the data is written into eight memory cells MC. Write / read circuit 55 reads 8-bit data signals Q0-Q7 from eight selected memory cells MC of memory mat 56 during a normal read operation.

  Write / read circuit 55 receives test signal DT7 applied via data input / output terminal DQ7 and input / output buffer 54 in memory mat 56 during the write operation in the first test mode (degeneration mode). Are written in the selected eight memory cells MC. Write / read circuit 55 includes a match / mismatch determination circuit. During a read operation in the first test mode, 8-bit data signal is output from selected eight memory cells MC of memory mat 56. Q0 to Q7 are read, it is determined whether or not the logics of these data signals Q0 to Q7 match, and a signal QT7 indicating the determination result is output to the data input / output terminal DQ7 via the input / output buffer 54. The operation of the write / read circuit 55 in the second test mode is the same as the normal operation. Each of the other memory units 51 to 53 is the same as the memory unit 50 except that the connected data input / output terminals are different.

  During the write operation in the second test mode, the shift register circuit 60 holds the data signals D0 to D7 that are sequentially input from the tester through the data input / output terminal DQ7, and the data signals D0 to D7 are stored as data. Input / output terminals DQ0 to DQ7. In the read operation in the second test mode, shift register circuit 60 latches data signals Q0-Q7 read from memory unit 50 and applied to data input / output terminals DQ0-DQ7, and the data The signals Q0 to Q7 are sequentially output to the tester via the data input / output terminal DQ7. Each of the other shift register circuits 61 to 63 is the same as the shift register circuit 64 except that the connected data input / output terminals are different.

Control unit 64 controls the entire SDRAM according to clock signal CLK, command signal CMD, external address signal EXTADD, data mask signals DQM0 to DQM3, and the like. The data mask signals DQM0 to DQM3 are provided corresponding to the memory units 50 to 53, respectively. During normal write operation, for example, when data mask signal DQM0 is set to the activation level “H” level, write data signals D0 to D7 to memory unit 50 are masked. In a normal read operation, for example, when data mask signal DQM0 is set to the activation level “H” level, read data signals Q0 to Q7 from memory unit 50 are masked. In the SDRAM, in the second test mode, the shift register circuits 60 to 63 are controlled using the input terminals of the data mask signals DQM0 to DQM3.

  FIG. 19 is a block diagram showing a configuration of the shift register circuit 60. 19, shift register circuit 60 includes a register 70, a transfer circuit 71, and a latch circuit 72 provided corresponding to each of data input / output terminals DQ0 to DQ7.

  The eight registers 70 are connected in a ring shape. Each register 70 shifts the held data signal to the next-stage register 70 in response to the control signal φ0 input from the input terminal of the data mask signal DQM0 being raised to the “H” level. The data signal output from the previous register 70 is held. Each register 70 gives the data signal held to the corresponding transfer circuit 71 and also holds the data signal given from the latch circuit 72.

  In response to the control signal φ3 input from the input terminal of the data mask signal DQM3 being raised to the “H” level, the transfer circuit 71 inputs the data signal held by the corresponding register 70 into the corresponding data input. Transfer to output terminal.

  Of the data input / output terminals DQ0 to DQ7, the latch circuit 72 corresponding to the data input / output terminal DQ7 is always activated, and the latch circuits corresponding to the other data input / output terminals DQ0 to DQ6 are connected to the data mask signal DQM1. It is activated when the control signal φ1 input from the input terminal is at “H” level, and deactivated when the control signal φ1 is at “L” level. The activated latch circuit 72 is applied to the corresponding data input / output terminal in response to the control signal φ2 input from the input terminal of the data mask signal DQM2 being raised to the “H” level. The data signal is latched and the data signal is applied to the corresponding register.

  FIGS. 20A to 20I and FIGS. 21A to 21I are time charts showing the write operation in the second test mode of the SDRAM. Here, only the operation of the portion related to the eight data input / output terminals DQ0 to DQ7 out of the 32 data input / output terminals DQ0 to DQ31 will be described. The operations related to the other data input / output terminals DQ8 to DQ15, DQ16 to DQ23, and DQ24 to DQ31 are the same as the operations related to the data input / output terminals DQ0 to DQ7 except that the numbers of the data input / output terminals are different. The same.

  20A to 20I, first, in synchronization with the rising edge of the clock signal CLK at time t0, the TENT command is applied to the input terminal of the command signal CMD and the signal TADD is applied to the input terminal of the external address signal EXTADD. In synchronization with the rising edge of the clock signal CLK at time t2 after two clock cycles, the TMRS command is given to the input terminal of the command signal CMD and the signal TM_KEY is given to the input terminal of the external address signal EXTADD to set the SCAN test mode To do.

  Further, in synchronization with the rising edge of the clock signal CLK at time t4 after two clock cycles, the ACT command is applied to the input terminal of the command signal CMD and the row address signal X0 is applied to the input terminal of the external address signal EXTADD. The circuit of is activated.

Next, at time t5, write data signal D0 is applied to data input / output terminal DQ7, and signal φ2 is set to “H” level for a half clock cycle, and write data signal D0 corresponds to data input / output terminal DQ7. The data is taken into the latch circuit 72 and transferred to the corresponding register 70. Next, at time t6, the signal φ0 is set to “H” level for half a clock cycle, and the write data signal D0 is transferred from the register 70 corresponding to the data input / output terminal DQ7 to the next stage register 70 corresponding to the data input / output terminal DQ6. Forward. Similarly, time t7 to t17
Write data signals D1 to D6 are input, and write data signals D0 to D6 are held in registers 70 corresponding to data input / output terminals DQ0 to DQ6, respectively.

  Next, at time t19, write data signal D7 is applied to data input / output terminal DQ7, and signal φ2 is set to “H” level for a half clock cycle, and write data signal D7 corresponds to data input / output terminal DQ7. The data is taken into the latch circuit 71 and transferred to the corresponding register 70. Thereby, the write data signals D0 to D7 are held in the registers 70 corresponding to the data input / output terminals DQ0 to DQ7, respectively.

  In this mode, control signal φ1 is fixed at “L” level, and latch circuit 72 corresponding to data input / output terminals DQ to DQ6 is inactivated. In the data input period (time t5 to t21), the clock signal CLK is fixed at the “L” level.

  Next, at time t21 to t23, the clock signal CLK is activated, the control signal φ3 is set to “H” level for 1.5 clock cycles from time t21 to activate each transfer circuit 71, and the eight registers 70 are activated. The held write data signals D0 to D7 are transferred to the data input / output terminals DQ0 to DQ7, respectively. In synchronization with the rising edge of the clock signal CLK at time t22, the WRIT command is applied to the input terminal of the command signal CMD, the column address signal Y0 is applied to the input terminal of the external address signal EXTADD, the row address signal X0 and the column address Data signals D0 to D7 are respectively written in the eight memory cells MC belonging to the memory cell group specified by the signal Y0.

  When the burst length BL is 1, this is the end, but when BL is 2 or more, as shown in FIGS. 21A to 21I, data shift and data transfer are performed again. In the second and subsequent write operations, the column address signal Y is generated inside the SDRAM, so there is no need to provide the column address signal Y from the outside.

  FIGS. 22A to 22J and FIGS. 23A to 23J are time charts showing the read operation of the SDRAM in the second test mode. Here, only the operation of the portion related to the eight data input / output terminals DQ0 to DQ7 out of the 32 data input / output terminals DQ0 to DQ31 will be described.

  22A to 22J, first, in synchronization with the rising edge of the clock signal CLK at time t0, the TENT command is applied to the input terminal of the command signal CMD and the signal TADD is applied to the input terminal of the external address signal EXTADD. In synchronization with the rising edge of the clock signal CLK at time t2 after two clock cycles, the TMRS command is given to the input terminal of the command signal CMD and the signal TM_KEY is given to the input terminal of the external address signal EXTADD to set the SCAN test mode To do.

  Further, in synchronization with the rising edge of the clock signal CLK at time t4 after two clock cycles, the ACT command is applied to the input terminal of the command signal CMD and the row address signal X0 is applied to the input terminal of the external address signal EXTADD. The circuit of is activated.

Next, in synchronization with the rising edge of the clock signal CLK at time t6 after two clock cycles, the READ command is applied to the input terminal of the command signal CMD and the column address signal Y0 is applied to the input terminal of the external address signal EXTADD. Thereby, data signals Q0 to Q7 are read from eight memory cells MC belonging to the memory cell group specified by row address signal X0 and column address signal Y0, and read data signals Q0 to Q7 are input to data at time t9. Output to output terminals DQ0 to DQ7. This SDRA
In M, since / CAS latency CL is 3, read data signals Q0 to Q7 are output 3 clock cycles after the READ command and column address signal Y0 are input. Further, since the burst length BL is 1, data signals Q0 to Q7 are read from only one memory cell group.

  Further, in one clock cycle period centered on time t9, the control signal φ1 is set to the “H” level to activate the eight latch circuits 71 of the shift register circuit 60, and a half clock cycle period centered on time t9. , The control signal φ2 is set to the “H” level, and the read data signals Q0 to Q7 are transferred from the data input / output terminals DQ0 to DQ7 to the eight registers 70 of the shift register circuit 60. Thus, read data signals Q0 to Q7 are held in eight registers 70 corresponding to data input / output terminals DQ0 to DQ7, respectively.

  Next, as shown in FIGS. 23A to 23J, when the control signal φ0 is set to “H” level for half a clock cycle at time t10, each register 70 stores the read data signal held in the next stage register. And the read data signal output from the previous register 70 is taken in. Thus, read data signals Q1-Q7, Q0 are held in eight registers 70 corresponding to data input / output terminals DQ0-DQ7, respectively.

  Then, at time t11, when control signal φ3 is set to “H” level for one clock cycle, read data signal Q0 is transferred from register 70 to data input / output terminal DQ7 by transfer circuit 71 corresponding to data input / output terminal DQ7. . Further, after a predetermined time from time t11, signal STRB indicating the timing at which the read data signal is output to the data input / output terminal is pulsed to the “H” level. Similarly, read data signals Q1-Q7 are sequentially output to data input / output terminal DQ7.

  In the third embodiment, only four data input / output terminals DQ7, DQ15, DQ23, and DQ31 among the 32 data input / output terminals DQ0 to DQ31 are connected to the tester, and the test signals DT7, DT15, DT23, DT31 can be written to the selected eight memory cells MC of the memory units 50 to 53, respectively, and 32-bit data signals D0 to D31 can be written to the selected 32 memory cells MC, thereby reducing the test cost. Can be achieved.

  In this state, it can be determined whether or not the selected 32 memory cells MC are normal, and whether or not the circuits corresponding to the 32 data input / output terminals DQ0 to DQ31 are normal. The test cost can be reduced.

  Further, when the control signals of the shift register circuits 60 to 63 are generated by the control unit 64 in the same manner as the control signals of the other circuit units, a switching gate or the like is added in the control unit 64 and an access delay occurs. On the other hand, in the third embodiment, the shift register circuits 60 to 63 are controlled by using the input terminals of the data mask signals DQM0 to DQM3 that do not greatly affect the access speed, so that an access delay is avoided. Note that an input terminal other than the input terminals of the data mask signals DQM0 to DQM3 may be used as long as the input terminal is a signal that does not significantly affect the access speed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a circuit block diagram showing a configuration of a portion related to data reading of an SDRAM according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a memory mat illustrated in FIG. 1. FIG. 2 is a diagram illustrating a configuration of a match / mismatch determination circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of an output buffer illustrated in FIG. 1. FIG. 2 is a circuit block diagram illustrating a configuration of a shift register circuit illustrated in FIG. 1. FIG. 6 is a circuit block diagram showing operations of the shift register circuit shown in FIG. 5 during normal operation and in a first test mode. 3 is a time chart showing a normal read operation of the SDRAM shown in FIG. 3 is a time chart showing a read operation in a first test mode of the SDRAM shown in FIG. 1. FIG. 6 is a circuit block diagram illustrating an operation of the shift register circuit illustrated in FIG. 5 in a second test mode. 6 is a time chart showing a read operation in a second test mode of the SDRAM shown in FIG. 1. 3 is a circuit block diagram illustrating a comparative example of the first embodiment. FIG. FIG. 10 is a circuit block diagram showing a configuration of a part related to data writing of an SDRAM according to a second embodiment of the present invention. FIG. 13 is a circuit block diagram illustrating a configuration of the shift register circuit illustrated in FIG. 12. FIG. 14 is a circuit block diagram showing operations of the shift register circuit shown in FIG. 13 during normal operation and in a first test mode. FIG. 14 is a circuit block diagram showing an operation of the shift register circuit shown in FIG. 13 in a second test mode. 13 is a time chart showing a write operation in a second test mode of the SDRAM shown in FIG. It is a block diagram which shows the structure of SDRAM by Embodiment 3 of this invention. FIG. 18 is a block diagram illustrating a configuration of a memory unit illustrated in FIG. 17. FIG. 18 is a block diagram illustrating a configuration of the shift register circuit illustrated in FIG. 17. 18 is a part of a time chart showing a writing operation in a second test mode of the SDRAM shown in FIG. 21 is the remaining part of the time chart shown in FIG. 20. 18 is a part of a time chart showing a read operation in a second test mode of the SDRAM shown in FIG. It is the remaining part of the time chart shown in FIG.

Explanation of symbols

  DQ0 to DQ31 Data input / output terminals, M0 to M3, 56 Memory mat, 1 amplifier, 2 Match / mismatch determination circuit, 2a EX-OR gate, 3, 20 to 24, 40 to 44 switch, 4 output buffer, 5, 30 , 60 to 63 shift register circuit, MA memory array, MC memory cell, WL word line, BLP bit line pair, 6 row decoder, 7 column decoder, 8 sense amplifier + input / output control circuit, 10 inverter, 11 NAND gate, 12 NOR gate, 13 P channel MOS transistor, 14 N channel MOS transistor, 25 to 28, 45 to 48, 70 register, 31 to 34 input buffer, 35 switching circuit, 36 write driver, 50 to 53 memory unit, 54 input / output buffer 55 Write / read circuit 71 Transfer circuit 72 latch circuit.

Claims (6)

A memory array including a plurality of memory cell groups each having first to Nth (where N is an integer greater than or equal to 2) memory cells;
A readout circuit for reading out first to Nth data signals from first to Nth memory cells belonging to a selected memory cell group of the plurality of memory cell groups, respectively.
A match / mismatch determination circuit for determining whether or not the logic levels of the first to Nth data signals match, and outputting a test signal indicating a determination result;
First to Nth output terminals;
The first to Nth data signals and the test signal are received, and during the normal operation, the first to Nth data signals are output to the first to Nth output terminals, respectively. When the test signal is output to a predetermined n-th output terminal (where n is an integer not less than 1 and not more than N) among the first to N-th output terminals, the second test mode An output circuit for sequentially outputting the first to Nth data signals to the nth output terminal. The output circuit is
First to Nth output buffers for transmitting the first to Nth data signals to the first to Nth output terminals, respectively, during the normal operation and the second test mode;
The first to Nth data signals output from the first to Nth output buffers are received, and the first to Nth data signals are sequentially supplied to the nth output terminal in the second test mode. A shift register circuit for outputting;
The n-th data signal and the test signal are received, the n-th data signal is selected during the normal operation and the second test mode, and the test signal is selected during the first test mode. And a switching circuit that
The semiconductor memory device according to claim 1, wherein the nth output buffer transmits the nth data signal or the test signal selected by the switching circuit to the nth output terminal. An input terminal for inputting a control signal for masking the first to Nth data signals during the normal operation;
The semiconductor memory device according to claim 2, wherein the shift register circuit can be controlled from the input terminal in the second test mode. A memory array including a plurality of memory cell groups each having first to Nth (where N is an integer greater than or equal to 2) memory cells;
First to Nth input terminals;
During normal operation, the first to Nth data signals input via the first to Nth input terminals are applied to the first to Nth nodes, respectively, and during the first test mode, the first to Nth data signals are applied. A data signal applied via a predetermined nth input terminal (where n is an integer of 1 to N) among the 1st to Nth input terminals is used as the first to Nth nodes. And an input circuit for supplying first to Nth data signals sequentially input via the nth input terminal to the first to Nth nodes, respectively, in the second test mode.
Write circuits for writing N data signals applied to the first to Nth nodes to first to Nth memory cells belonging to a selected memory cell group of the plurality of memory cell groups, respectively. A semiconductor memory device. The input circuit is
First to Nth input buffers;
A shift register circuit for supplying first to Nth data signals sequentially input via the nth input terminal to the first to Nth input buffers in the second test mode;
In the normal operation and in the first test mode, the first to Nth input terminals are connected to the first to Nth input buffers, respectively, and in the second test mode, the first test mode is used. A first switching circuit that connects the shift register circuit between the input terminal of the first and Nth input buffers;
In the normal operation and in the second test mode, the first to Nth data signals given through the first to Nth input buffers are given to the first to Nth nodes, respectively. 5. The circuit according to claim 4, further comprising: a second switching circuit that applies a data signal supplied via the nth input buffer to each of the first to Nth nodes in the first test mode. Semiconductor memory device. An input terminal for inputting a control signal for masking the first to Nth data signals during the normal operation;
The semiconductor memory device according to claim 5, wherein the shift register circuit is controllable from the input terminal in the second test mode.

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