WO2014175057A1

WO2014175057A1 - Semiconductor device

Info

Publication number: WO2014175057A1
Application number: PCT/JP2014/060162
Authority: WO
Inventors: 畠山　淳; 石川　透
Original assignee: ピーエスフォールクスコエスエイアールエル
Priority date: 2013-04-23
Filing date: 2014-04-08
Publication date: 2014-10-30
Also published as: TW201510996A

Abstract

[Problem] To test whether or not an input buffer or an output buffer performs normally. [Solution] The present invention is provided with: a microbump (MFBa); a test pad (TP); an output buffer (OB) in which an output node is connected to the microbump (MFBa); an input buffer (IB) in which an input node is connected to the microbump (MFBa); a memory cell array (60); a data comparison circuit (65) in which an output node is connected to the test pad (TP); a read/write bus (RWBS) which connects an input node of the output buffer (OB) with the memory cell array (60); and a test bus (TBS) which connects an output node of the input buffer (IB) with an input node of the data comparison circuit (65). According to the present invention, it is possible to assess, by way of a performance test, whether or not the output buffer (OB) and the input buffer (IB) are performing normally, without using the microbump (MFBa).

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of performing an operation test of an input buffer and an output buffer.

Recently, as a kind of DRAM (Dynamic Random Access Memory), “wide IO DRAM”, which is a next-generation DRAM standard for mobile devices such as smartphones and tablet PCs, has attracted attention (see Patent Document 1).

Wide IO type DRAM expands the I / O bit width of conventional mobile DRAM such as 16 bits and 32 bits to 512 bits and realizes a high data transfer rate of 12.8 GB / sec. Such an I / O bit width cannot be realized in a conventional mobile DRAM package, but in a wide IO type DRAM, a DRAM memory chip and a controller chip called SOC (System on Chip) are stacked to form a single package, The stacked chips are connected by through electrodes called TSV (Through Substrate Via). As a result, the memory chip and the controller chip can be connected by a large number of wires, and the I / O bit width of the input / output interface connecting the chips can be increased. Further, it is possible to increase the capacity by stacking many memory chips.

Since the wide IO type DRAM has an extremely large number of terminals connected to the controller chip as compared with a normal DRAM, each terminal is constituted by a microelectrode called a micro bump. Since a large number of micro bumps are arranged at a very narrow pitch, it is difficult to bring the tester probe into direct contact with the micro bumps during a test operation. For this reason, in the wide IO type DRAM, a test pad electrode called a direct access terminal is provided separately from the micro bump, and the tester probe is brought into contact with the test pad electrode during the test operation. Signal input / output.

JP2012-243251A

In an operation test using a pad electrode for a test, test data is usually input via a pad electrode for address input, and a determination signal indicating the test data or a test result is output via a pad electrode for data output. Is done. However, in this case, since the input buffer and the output buffer used in the normal operation mode are not used, there is a problem that it is impossible to test whether the input buffer and the output buffer operate normally.

The above problem is not limited to the wide IO type DRAM, and is a problem that occurs in all semiconductor devices that do not use the input buffer and output buffer used in the normal operation mode during the operation test.

A semiconductor device according to an aspect of the present invention includes first and second terminals, an output buffer having an output node connected to the first terminal, and an input buffer having an input node connected to the first terminal. The memory cell array, a data comparison circuit whose output node is connected to the second terminal, a first wiring connecting the input node of the output buffer and the memory cell array, and the first wiring are independent of each other. And a second wiring that connects the output node of the input buffer and the input node of the data comparison circuit.

A semiconductor device according to another aspect of the present invention includes a first terminal, first and second wirings, an output buffer having an output node connected to the first terminal, and an input node serving as the first terminal. An output buffer of the input buffer is connected to the first or second wiring based on a switching signal and an input buffer connected to the memory cell array, a data comparison circuit connected to the second wiring, and a switching signal. A switching circuit, wherein the first wiring interconnects the memory cell array, the input node of the output buffer, and the switching circuit, and the second wiring connects the switching circuit and the data comparison circuit. It is characterized by being connected to each other.

According to the present invention, a path for supplying data read from the memory cell array to the data comparison circuit via the output buffer and the input buffer is provided, so whether or not the output buffer and the input buffer are operating normally. This can be determined by an operation test.

It is typical sectional drawing for demonstrating the structure of the semiconductor device 10 by preferable embodiment of this invention. It is typical sectional drawing for demonstrating the structure of 10 A of semi-finished products. 3 is a plan view of a main surface 20F of the memory chip 20. FIG. 4 is a block diagram for explaining a circuit configuration of a memory chip 20. FIG. It is a block diagram for demonstrating the circuit structure of channel ChA by the 1st Embodiment of this invention. 3 is a circuit diagram showing a configuration of a main part of a data comparison circuit 65. FIG. 3 is a circuit diagram showing a configuration of a main part of a data input / output circuit 64. FIG. 4 is a timing chart for explaining an operation test of the memory chip 20. FIG. It is a block diagram for demonstrating the circuit structure of channel ChA by the 2nd Embodiment of this invention. It is a block diagram for demonstrating the circuit structure of channel ChA by the 3rd Embodiment of this invention. It is a typical sectional view for explaining the structure of semiconductor device 100 by a 4th embodiment of the present invention. It is typical sectional drawing for demonstrating the structure of 100 A of semi-finished products. It is a schematic diagram for demonstrating the connection state of penetration electrode TSV1, TSV2. It is sectional drawing which shows the structure of penetration electrode TSV1. It is a typical sectional view for explaining the structure of semiconductor device 200 by a 5th embodiment of the present invention. It is a typical sectional view for explaining the structure of semiconductor device 300 by a 6th embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

As shown in FIG. 1, the semiconductor device 10 according to the present embodiment has a configuration in which a memory chip 20 and a control chip 30 are stacked. The memory chip 20 is a so-called wide IO type DRAM, and a main surface 20F is provided with a plurality of surface micro bumps MFB and a plurality of test pads TP. The main surface 20F is the surface on which circuit elements such as transistors are formed. In the example shown in FIG. 1, the main surface 20F of the memory chip 20 faces downward. That is, in the present embodiment, the memory chip 20 is stacked on the control chip 30 in a face-down manner.

The control chip 30 is a semiconductor chip (SOC) that controls the operation of the memory chip 20 and is mounted on the circuit board 40 in a face-down manner. That is, the control chip 30 is mounted such that the main surface 30F faces the circuit board 40 side and the back surface 30B faces the memory chip 20 side. A plurality of front surface micro bumps CFB are formed on the main surface 30F of the control chip 30, and a plurality of back surface micro bumps CBB are formed on the back surface 30B of the control chip 30. The front surface microbump CFB is bonded to the substrate electrode 41 provided on the circuit board 40, and the back surface microbump CBB is bonded to the front surface microbump MFB provided on the memory chip 20. The internal circuit provided in the control chip 30 is connected to the front surface microbump CFB and also connected to the back surface microbump CBB through the through electrode TSV (Through Substrate Via) provided through the control chip 30. Has been.

The circuit board 40 has a structure in which a substrate electrode 41 is provided on the upper surface side on which the memory chip 20 and the control chip 30 are mounted, and an external terminal 42 is provided on the lower surface side. The substrate electrode 41 and the external terminal 42 are connected to each other via a through-hole conductor (not shown) provided through the circuit substrate 40. Further, a sealing resin 50 is provided on the upper surface of the substrate electrode 41 so as to cover the memory chip 20 and the control chip 30, thereby providing the semiconductor device 10 as one package.

With this configuration, a signal (address signal, command signal, clock signal, write data, etc.) input via the external terminal 42 is first input to the control chip 30, and after undergoing necessary signal processing by the control chip 30, the memory It is supplied to the chip 20. On the other hand, a signal (such as read data) output from the memory chip 20 is input to the control chip 30 and is output to the outside from the external terminal 42 through necessary signal processing by the control chip 30.

In the manufacturing process of the semiconductor device 10, after mounting the control chip 30 and the memory chip 20 on the circuit board 40, these

chips

20 and 30 may be sealed with a sealing resin 50, as shown in FIG. The semi-finished product 10A may be prepared and connected to the control chip 30 and the circuit board 40. The semi-finished product 10A shown in FIG. 2 includes a sealing resin 50 that covers each surface except the memory chip 20 and its main surface 20F. If such a semi-finished product 10A is used, it is possible to appropriately connect the control chips 30 that differ depending on the specifications and applications, so that versatility can be improved.

FIG. 3 is a plan view of the main surface 20F of the memory chip 20. FIG.

As shown in FIG. 3, the main surface 20F of the memory chip 20 is provided with four channels ChA to ChD arranged in a matrix in the X and Y directions. Each of the channels ChA to ChD is a circuit block that can operate as a single DRAM. Therefore, the memory chip 20 has a configuration in which four independent DRAMs are integrated into one chip.

The main surface 20F of the memory chip 20 is provided with a plurality of micro bumps MFBa to MFBd corresponding to the channels ChA to ChD. The number of data micro-bumps MFBa to MFBd assigned to each channel ChA to ChD is very large, for example, 128, and a large number of micro-bumps MFBa to MFBd for power supply are required. For example, about 300 micro bumps MFBa to MFBd are provided for each ChD. For this reason, more than 1000 micro bumps MFB are used in the entire chip.

These micro bumps MFB include test terminals called direct access terminals. However, since the size of the micro bump MFB is very small, it is difficult to bring the tester probe into contact with the direct access terminal. For this reason, each direct access terminal is assigned a test pad TP for contacting a tester probe. The test pad TP has a larger plane size than the micro bump MFB so that the tester probe can be easily brought into contact with the test pad TP. With this configuration, an operation test can be performed using the test pad TP before the stacking, for example, the wafer state memory chip 20, and direct access using the control chip 30 after stacking on the control chip 30. An operation test can be performed through the microbump MFB.

FIG. 4 is a block diagram for explaining the circuit configuration of the memory chip 20.

In FIG. 4, the double circles indicate the micro bumps MFB, and the double squares indicate the test pads TP. The signal having “DA” at the head of the signal name and the test signal TEST are signals that are input (or output) through the direct access terminal. As shown in FIG. 4, each direct access terminal is provided with a corresponding test pad TP. Further, signals having “a” to “d” at the end of the signal names are signals corresponding to the channels ChA to ChD, respectively.

For example, the signal SIGa shown in FIG. 4 is an input signal supplied to the channel ChA and includes an address signal ADDa, a command signal CMDa, a chip select signal CS0a, a clock signal CLKa, a clock enable signal CKE0a, and the like. The channel ChA receives these input signals SIGa and performs a read operation, a write operation, and the like. When the channel ChA performs a read operation, the read data DQa that has been read is output via the micro bump MFBa. On the other hand, when the channel ChA performs a write operation, the read data DQa input via the micro bump MFBa is supplied to the channel ChA.

The same applies to the other channels ChB to ChD, which respectively receive the corresponding input signals SIGb to SIGd and output the read data DQb to DQd or input the write data DQb to DQd.

On the other hand, a signal input via the direct access terminal is input in common to each channel ChA to ChD. Signals input via the direct access terminal include an address signal DA_ADD, a command signal DA_CMD, a chip select signal DA_CS0, a clock signal DA_CLK, a clock enable signal DA_CKE0, a test signal TEST, and the like. Since these signals are commonly assigned to the channels ChA to ChD, the channels ChA to ChD operate in parallel during the test operation, and the signals DA_DQa to DA_DQd, which are test results, are respectively used for direct access. To the micro bump MFB or the test pad TP.

FIG. 5 is a block diagram for explaining the circuit configuration of the channel ChA according to the first embodiment of the present invention. The other channels ChB to ChD also basically have the same circuit configuration as that of the channel ChA, and thus redundant description is omitted.

As shown in FIG. 5, the channel ChA includes a memory cell array 60 and an access control circuit 61 that performs an access operation to the memory cell array 60. The access control circuit 61 performs an access operation to the memory cell array 60 based on an input signal SIG including an address signal ADD, a command signal CMD, a chip select signal CS, a clock signal CLK, and a clock enable signal CKE. The input signal SIG is supplied from the input switching circuit 62. The input switching circuit 62 receives the input signal SIGa for normal operation and the input signal DA_SIG for test operation, and outputs one selected based on the test signal TEST to the access control circuit 61 as the input signal SIG. Thus, the normal operation input signal SIGa is supplied to the access control circuit 61 during the normal operation, and the test operation input signal DA_SIG is supplied to the access control circuit 61 during the test operation.

In both the normal operation and the test operation, when the read operation is executed, the read data DQa read from the memory cell array 60 is supplied to the data input / output circuit 64 via the switching circuit 63. In the normal operation, read data DQa is output to the outside via the output buffer OB included in the data input / output circuit 64. On the other hand, in the test operation, the output buffer included in the data input / output circuit 64 is output. Test read data tRD is supplied to the data comparison circuit 65 via OB and the input buffer IB. Details of the test operation will be described later.

In addition, when a write operation is executed during normal operation, write data DQa input from the outside is supplied to the memory cell array 60 via the input buffer IB and the switching circuit 63. On the other hand, when the write operation is executed during the test operation, the test write data tWD held in the test data register 66 is supplied to the memory cell array 60 via the switching circuit 63. The test data register 66 is activated by the enable signal TPen and serves to temporarily hold the test write data tWD input via the address direct access terminal.

Test write data tWD held in the test data register 66 and test read data tRD read from the memory cell array 60 are compared by the data comparison circuit 65. The data comparison circuit 65 compares them in response to the enable signal CMPen, and outputs a pass / fail signal P / F generated according to the result to the output circuit 67.

The enable signals TPen and CMPen are generated by the test mode control circuit 68. The test mode control circuit 68 generates enable signals TPen and CMPen based on the address signal ADD and the command signal CMD during the test operation, and also selects the selection signal SWC that controls the switching circuit 63 and the data input / output circuit 64. A signal BLCTL and the like are generated. The data input / output circuit 64 is also supplied with a clock signal SCLK, boundary scan signals BSCTL1, 2 and the like.

FIG. 6 is a circuit diagram showing a configuration of a main part of the data comparison circuit 65.

As shown in FIG. 6, the data comparison circuit 65 compares each bit of the test write data tWD composed of a plurality of bits W0 to Wn with each bit of the test read data tRD composed of a plurality of bits R0 to Rn. Non-OR circuits ENOR0 to ENORn are provided. The output signals of these exclusive OR circuits ENOR0 to ENORn are input to an AND gate circuit 65a, and the output signal is used as a pass / fail signal P / F. With this configuration, when all the bits of the test write data tWD and the test read data tRD match, the pass / fail signal P / F becomes high level (pass signal), and the test write data tWD and the test read data tRD are 1 bit. However, if they do not match, the pass / fail signal P / F is at a low level (fail signal). The pass / fail signal P / F is output to the outside from the micro bump MFB or the test pad TP for direct access via the output circuit 67.

FIG. 7 is a circuit diagram showing a configuration of a main part of the data input / output circuit 64.

As shown in FIG. 7, the data input / output circuit 64 includes an output buffer OB and an input buffer IB connected in parallel between the read / write bus RWBS and the data input / output micro bump MFBa. The output node of the output buffer OB and the input node of the input buffer IB are commonly connected to the corresponding microbump MFBa.

The read / write bus RWBS is a bidirectional data bus that connects the data input / output circuit 64 and the switching circuit 63. The read / write bus RWBS includes buses RWBS0 to RWBSn for internal data D0 to Dn, and these are connected to micro bumps MFBa for data DQa0 to DQan via corresponding output buffers OB and input buffers IB, respectively.

As shown in FIG. 7, data latch circuits DQOL and DQIL and selector circuits OSL and ISL are connected between the read / write bus RWBS and the data input / output micro bump MFBa.

More specifically, a data latch circuit DQOL and a selector circuit OSL are connected in this order between the read / write bus RWBS and the input node of the output buffer OB. The data latch circuit DQOL latches the read data D0 to Dn on the read / write bus RWBS in synchronization with the clock signal CLK, and supplies the output signal to the normal input node nom of the selector circuit OSL. The selector circuit OSL has a boundary scan input node bs in addition to the normal input node nom, and outputs a signal input to one of the nodes based on the boundary scan signal BSCTL2.

On the other hand, a selector circuit ISL, a data latch circuit DQIL, and a write switch 69 are connected in this order between the output node of the input buffer IB and the read / write bus RWBS. The selector circuit ISL has a normal input node nom and a boundary scan input node bs, and outputs a signal input to one of the nodes based on the boundary scan signal BSCTL1. As shown in FIG. 7, the normal input node nom is connected to the output node of the input buffer IB, and the boundary scan input node bs is connected to the output node of the previous data latch circuit DQIL. The boundary scan input data SDI is input to the boundary scan input node bs of the first-stage selector circuit ISL, and the boundary scan output data SDO is output from the output node of the final-stage data latch circuit DQIL.

The data latch circuit DQIL latches the write data DQa0 to DQan output from the selector circuit ISL in synchronization with the clock signal CLK or SCLK, and outputs the output signal to the read / write bus RWBS via the write switch 69. The selection of the clock signal CLK or SCLK is performed by the selector circuit CSL based on the selection signal BLCTL. Although not particularly limited, an address terminal that is not used at the time of column access, for example, a terminal for inputting the ADD 12 can be used as the clock signal SCLK.

The write switch 69 is a circuit for switching whether to output the write data DQa0 to DQan output from the data latch circuit DQIL to the read / write bus RWBS, and the selection is a write control signal supplied from the access control circuit 61. Performed by WCTL. The write control signal WCTL is a signal that is at a high level during a write operation, whereby the write data DQa0 to DQan output from the data latch circuit DQIL is output to the read / write bus RWBS during the write operation. At other operation timings, the output node of the data latch circuit DQIL is disconnected from the read / write bus RWBS.

On the other hand, the output node of the data latch circuit DQIL is connected to the test bus TBS regardless of the write control signal WCTL. Therefore, the data (test read data tRD) output from the data latch circuit DQIL is supplied to the data comparison circuit 65 via the test bus TBS. The test bus TBS is a test data bus provided independently of the read / write bus RWBS.

With this configuration, during normal operation, the write data DQa0 to DQan input in parallel from the data input / output micro bumps MFBa are passed through the input buffer IB, the selector circuit ISL, the data latch circuit DQIL, and the write switch 69. Are output to the read / write bus RWBS. As a result, the write data DQa0 to DQan are written in the memory cell array 60. The read data D0 to Dn read in parallel from the memory cell array 60 are output from the data input / output micro bumps MFBa via the data latch circuit DQOL, the selector circuit OSL, and the output buffer OB.

On the other hand, in the boundary scan test, four operations of the serial in mode, the parallel out mode, the parallel in mode, and the serial out mode are selectively executed. Here, in the serial-in mode, the boundary scan input data SDI is serially input and sequentially shifted through the selector circuit ISL and the data latch circuit DQIL. As a result, the serially input boundary scan input data SDI is latched by the plurality of data latch circuits DQIL. In the parallel out mode, the data latched in the data latch circuit DQIL is output as DQa0 to DQan via the selector circuit OSL and the output buffer OB, respectively. In the parallel-in mode, the input data DQa0 to DQan can be latched in the corresponding data latch circuit DQIL via the input buffer IB and the selector circuit ISL. In the serial-out mode, the data latched by the data latch circuit DQIL can be output as the boundary scan output data SDO by sequentially shifting the data via the selector circuit ISL and the data latch circuit DQIL.

Furthermore, in the present embodiment, with the configuration shown in FIG. 7, data output from the output buffer OB in synchronization with the clock signal CLK can be latched in synchronization with the clock signal SCLK via the input buffer IB. . As a result, it is possible to confirm whether or not the output buffer OB and the input buffer IB are operating correctly by an operation test.

FIG. 8 is a timing chart for explaining an operation test of the memory chip 20 according to the present embodiment.

In the example shown in FIG. 8, the read command Read and the column address Yadd are input at time t0 via the direct access terminal. Although not shown, the test mode TEST is entered by the test signal TEST before time t0, and the test write data tWD is written to the memory cell array 60. The test write data tWD written in the memory cell array 60 is held in the test data register 66 and supplied to the data comparison circuit 65 as an expected value.

When a read command Read is input at time t0, test read data tRD is read from the memory cell array 60. After a predetermined read latency RL has elapsed, data input / output is performed in synchronization with the clock signal CLK (DA_CLK). Is output to the micro bump MFBa. In the example shown in FIG. 8, the read latency RL = 4. Therefore, the test read data tRD (Q0) is output to the micro bump MFBa in synchronization with the time t4.

The access control circuit 61 automatically generates an internal read command iRead in synchronization with times t1, t2, and t3 and automatically generates a column address iYadd. As a result, the test read data tRD (Q1, Q2, Q3) is automatically output in synchronization with the times t5, t6, t7. In the example shown in FIG. 8, the burst length BL is set to 4 bits by repeating such an automatic read operation three times.

Here, it is desirable that the test read data tRD output at adjacent timings, for example, the data Q0 and Q1 have logic levels opposite to each other. This is because, if these logic levels are the same, even if the previous data is erroneously held, the value of the test read data tRD shows a correct value, and the operation test may be inaccurate. Because there is.

The test read data tRD (Q0 to Q3) read in this way is output to the test bus TBS in synchronization with the rising edge of the clock signal SCLK and supplied to the data comparison circuit 65. In the example shown in FIG. 8, the clock signal SCLK changes from the low level to the high level at the timing when the test read data Q1 appears on the microbump MFBa, and therefore the data Q1 is supplied to the data comparison circuit 65. As described above, the clock signal SCLK is input from an address terminal that is not used during column access, for example, a terminal for ADD12.

The data comparison circuit 65 compares the test write data tWD held in the test data register 66 with the test read data tRD (Q1 in the example shown in FIG. 8) supplied via the test bus TBS. In response to this, a pass / fail signal P / F is generated. That is, if all these bits match, a pass signal is generated, and if even one bit is different, a fail signal is generated. Therefore, if this operation is repeatedly executed while changing the rising timing of the clock signal SCLK, all the test read data tRD (Q0 to Q3) can be evaluated.

In such an operation test, the test read data tRD is supplied to the data comparison circuit 65 via the output buffer OB and the input buffer IB. Therefore, not only the memory cell array 60 and the access control circuit 61 but also the output buffer OB. It is also possible to evaluate whether or not the input buffer IB operates normally. As a result, it is possible to test whether or not these circuit blocks operate normally using the micro bump MFB or the test pad TP for direct access.

In addition, in the present embodiment, since the above-described operation test is performed using a circuit provided in the data input / output circuit 64 in advance for the boundary scan test, the circuit configuration of the data input / output circuit 64 is complicated. It does not become.

Next, a second embodiment of the present invention will be described.

FIG. 9 is a block diagram for explaining the circuit configuration of the channel ChA according to the second embodiment of the present invention.

As shown in FIG. 9, the channel ChA according to the second embodiment of the present invention is different from the channel ChA according to the first embodiment shown in FIG. 5 in that an AND gate circuit 70 is inserted in the test bus TBS. It is different. Since the other points are the same as those of the channel ChA according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

In the AND gate circuit 70, one input node is connected to the test bus TBS, the enable signal CMPen is supplied to the other input node, and the test read data tRD that is the output signal is supplied to the data comparison circuit 65. . With this configuration, the load capacity of the test bus TBS is reduced as compared with the first embodiment, so that it is possible to reduce the signal delay during the write operation caused by the load capacity of the test bus TBS.

Next, a third embodiment of the present invention will be described.

FIG. 10 is a block diagram for explaining the circuit configuration of the channel ChA according to the third embodiment of the present invention.

As shown in FIG. 10, the channel ChA according to the third embodiment of the present invention is different from that shown in FIG. 9 in that a holding circuit 80 is inserted between the data comparison circuit 65 and the output circuit 67. This is different from the channel ChA according to the embodiment. Since the other points are the same as those of the channel ChA according to the second embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

The holding circuit 80 is activated by the enable signal LCTen supplied from the test mode control circuit 68 and plays a role of generating the test result signal TPF by holding the pass / fail signal P / F. Specifically, after the enable signal LCTen is activated, if all the pass fail signals P / F are at a high level (pass signal), the test result signal TPF is set to the pass level, and the pass fail signal P / F is low even once. If the level (fail signal) is indicated, the test result signal TPF is set to the fail level. The test result signal TPF generated in this way is output to the outside via the output circuit 67.

According to the present embodiment, if the pass / fail signal P / F becomes low level (fail signal) even once, the test result signal TPF at the fail level is output to the outside, so the tester always outputs the test result signal TPF. There is no need to monitor. Thereby, the operation of the tester can be simplified as compared with the first and second embodiments.

Next, a fourth embodiment of the present invention will be described.

FIG. 11 is a schematic cross-sectional view for explaining the structure of a semiconductor device 100 according to the fourth embodiment of the present invention.

As shown in FIG. 11, the semiconductor device 100 according to the present embodiment has a configuration in which four memory chips 21 to 24 are stacked on a control chip 30. The memory chips 21 to 24 are chips having the same circuit configuration as the memory chip 20 described above. The main surfaces 21F to 24F of the memory chips 21 to 24 are provided with a plurality of front surface micro bumps MFB and a plurality of test pads TP, and the back surfaces 21B to 23B of the memory chips 21 to 23 are provided with a plurality of back surface micro bumps MBB. ing. The back surface micro-bump MBB is not provided on the back surface 24B of the memory chip 24 located in the uppermost layer.

The memory chips 21 to 23 are provided with through electrodes TSV that connect the front surface micro bumps MFB and the back surface micro bumps MBB. Then, the back surface micro bump MBB of the control chip 30 or the memory chips 21 to 23 located in the lower layer and the front surface micro bump MFB of the memory chips 21 to 24 located in the upper layer are joined to each other.

The reason why the back micro bump MBB and the through silicon via TSV are not provided in the memory chip 24 is that the memory chip 24 is a chip located at the uppermost stage of the semiconductor device 100, so that the signal supplied to the memory chip 24 is further transferred to another chip. This is because there is no need to transfer. Thus, when the through silicon via TSV and the back micro bump MBB are not formed on the memory chip 24, the memory chip 24 can be made thicker than the other memory chips 21 to 23 as illustrated in FIG. As a result, it is possible to suppress chip deformation due to thermal stress (thermal stress generated when the memory chips 21 to 24 are stacked) when the semiconductor device 100 is manufactured. However, as a matter of course, a chip having the same structure as the memory chips 21 to 23 may be used as the memory chip 24.

In the manufacturing process of the semiconductor device 100, after mounting the control chip 30 and the memory chips 21 to 24 on the circuit board 40, these chips 21 to 24, 30 may be sealed with a sealing resin 50. A semi-finished product 100 </ b> A shown in FIG. 12 may be prepared and connected to the control chip 30 and the circuit board 40. A semi-finished product 100A shown in FIG. 12 includes a sealing resin 50 that covers each surface except the memory chip 21 and the main surface 21F. If such a semi-finished product 100A is used, it becomes possible to appropriately connect the control chips 30 that differ depending on the specifications and applications.

The through electrodes TSV provided in the memory chips 21 to 23 include a first type of through electrode TSV1 and a second type of through electrode TSV2.

FIGS. 13A and 13B are schematic diagrams for explaining the connection state of the through silicon vias TSV1 and TSV2, respectively.

The through silicon via TSV1 shown in FIG. 13A is short-circuited with the through silicon via TSV1 in the other layer provided in the same plane position in a plan view seen from the stacking direction, that is, when seen from the arrow A shown in FIG. ing. That is, as shown in FIG. 13A, the upper and lower through electrodes TSV1 provided at the same position in plan view are short-circuited, and one signal path is configured by these through electrodes TSV1. This signal path is connected to the internal circuit 2 of each of the memory chips 21 to 24. Therefore, input signals (command signal, address signal, clock signal, write data, etc.) supplied from the control chip 30 via the main surface 21F of the memory chip 21 to this signal path are transmitted to the memory chips 21 to 24, respectively. It is input to the internal circuit 2 in common. Further, an output signal (read data or the like) supplied to the signal path from the internal circuit 2 of each of the memory chips 21 to 24 is wired or output from the main surface 21F of the memory chip 21 to the control chip 30.

FIG. 14 is a cross-sectional view showing the structure of the through silicon via TSV1.

As shown in FIG. 14, the through silicon via TSV1 is provided through the semiconductor substrate 90 and the interlayer insulating film 91 on the surface thereof. An insulating film 92 is provided between the through silicon via TSV1 and the semiconductor substrate 90, thereby ensuring insulation between the through silicon via TSV1 and the semiconductor substrate 90.

The lower end of the through silicon via TSV1 is provided on the main surface of the memory chips 21 to 23 via the pads P0 to P3 provided in the wiring layers L0 to L3 and the plurality of through hole electrodes TH1 to TH3 connecting the pads. Are connected to the surface micro-bump MFB. On the other hand, the upper end of the through silicon via TSV1 is connected to the backside micro bumps MBB of the memory chips 21 to 23. The back surface micro bumps MBB are connected to the front surface micro bumps MFB provided in the upper memory chips 22 to 24. Thereby, two penetration electrode TSV1 provided in the same position by planar view will be in the state where it mutually short-circuited. Connection to the internal circuit 2 shown in FIG. 13A is made through internal wiring (not shown) drawn from the pads P0 to P3 provided in the wiring layers L0 to L3.

The through silicon via TSV2 shown in FIG. 13B is short-circuited with the through silicon via TSV2 of another memory chip provided at a different position in plan view. Specifically, each of the memory chips 21 to 23 is provided with four through electrodes TSV2 at the same position in plan view, and the N (N = 1 to 3) th through holes provided in the lower memory chip. The electrode TSV2 is connected to the (N + 1) th through electrode TSV2 provided in the upper memory chip. The fourth through electrode TSV2 (the rightmost through electrode TSV2 in FIG. 13B) provided in the lower memory chip is the first through electrode TSV2 (FIG. 13B) provided in the upper memory chip. Then, it is connected to the leftmost through silicon via TSV2). Such a cyclic connection forms four independent signal paths.

Of the four through electrodes TSV2, the through electrode TSV2 (the leftmost through electrode TSV2 in FIG. 13B) provided at a predetermined position in plan view is an internal circuit in the memory chips 21 to 23. 3 is connected. The internal circuit 3 included in the uppermost memory chip 24 is connected to the rightmost through silicon via TSV <b> 2 included in the memory chip 23.

With this configuration, the signals S1 to S4 shown in FIG. 13B are selectively input to the internal circuits 3 of the memory chips 21 to 24, respectively. Examples of such signals include a chip select signal CS and a clock enable signal CLK.

As described above, the semiconductor device according to the present invention can be applied to the stacked semiconductor device 100 in which the plurality of memory chips 21 to 24 are stacked.

After the semi-finished product 100A shown in FIG. 12 is formed by stacking a plurality of memory chips 21 to 24, the test pads TP of the memory chips 22 to 24 are covered with the sealing resin 50, so that the tester probe is contacted. However, it is possible to perform an operation test on each of the memory chips 21 to 24 through the through silicon via TSV by bringing a tester probe into contact with the test pad TP of the lowermost memory chip 21. is there. Further, after the configuration of the semiconductor device 100 shown in FIG. 11, the operation test of each of the memory chips 21 to 24 is performed via the control chip 30 and the direct access micro bumps MFB and MBB and the through silicon via TSV. Can do.

Next, a fifth embodiment of the present invention will be described.

FIG. 15 is a schematic cross-sectional view for explaining the structure of a semiconductor device 200 according to the fifth embodiment of the present invention.

As shown in FIG. 15, the semiconductor device 200 according to the fifth embodiment of the present invention is similar to the fourth embodiment shown in FIG. 11 in that the control chip 30 is mounted on the circuit board 40 in a face-up manner. This is different from the semiconductor device 100 according to the form. The stacked structure of the memory chips 21 to 24 is the same as that of the semiconductor device 100 according to the fourth embodiment. In the present embodiment, the connection between the control chip 30 and the circuit board 40 is performed using the bonding wire BW. For this reason, it is not necessary to form the through silicon via TSV in the control chip 30.

Next, a sixth embodiment of the present invention will be described.

FIG. 16 is a schematic cross-sectional view for explaining the structure of a semiconductor device 300 according to the sixth embodiment of the present invention.

As shown in FIG. 16, in the semiconductor device 300 according to the sixth embodiment of the present invention, the memory chips 21 to 24 and the control chip 30 are mounted on different planes on the silicon interposer SI. The semiconductor device 100 is different from the semiconductor device 100 according to the fourth embodiment shown in FIG. 11 in that it is mounted on the substrate 40. The stacked structure of the memory chips 21 to 24 is the same as that of the semiconductor device 100 according to the fourth embodiment.

The silicon interposer SI has a front surface micro bump SMB, a back surface micro bump SBB, and a through electrode TSV connecting them. The front surface microbump SMB is connected to the front surface microbump MFB of the memory chip 21 and the front surface microbump CFB of the control chip 30, and the back surface microbump SBB is connected to the substrate electrode 41 provided on the circuit board 40. With this configuration, it is not necessary to form the through silicon via TSV in the control chip 30 also in the present embodiment.

As described above, various connection methods can be used as the connection method between the memory chip 20 (21 to 24) and the control chip 30, and in the present invention, these connection methods are not limited to specific connection methods. .

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2,3

Internal circuit

10, 100, 200, 300

Semiconductor device

10A, 100A Semi-finished product 20-24 Memory chip 20F-24F Main surface 21B-24B of memory chip Back surface 30 of memory chip Control chip 30F Main surface 30B of control chip Chip back surface 40 Circuit board 41 Substrate electrode 42 External terminal 50 Sealing resin 60 Memory cell array 61 Access control circuit 62 Input switching circuit 63 Switching circuit 64 Data input / output circuit 65 Data comparison circuit 65a AND gate circuit 66 Test data register 67 Output circuit 68 Test Mode Control Circuit 69 Light Switch 70 AND Gate Circuit 80 Holding Circuit 90 Semiconductor Substrate 91 Interlayer Insulating Film 92 Insulating Film BW Bonding Wire CBB Back Microvan CFB surface micro bump ChA to ChD channel CSL selector circuit DQOL, DQIL data latch circuit ENOR0 to ENORn exclusive OR circuit IB input buffer ISL selector circuit L0 to L3 wiring layer MBB back surface micro bump MFB surface micro bump OB output buffer OSL selector Circuit RWBS Read / write bus SI Silicon interposer SBB Back micro bump SMB Front micro bump TBS Test bus TH1 to TH3 Through hole electrode TP Test pad TSV, TSV1, TSV2 Through electrode

Claims

First and second terminals;
An output buffer having an output node connected to the first terminal;
An input buffer having an input node connected to the first terminal;
A memory cell array;
A data comparison circuit having an output node connected to the second terminal;
A first wiring connecting the input node of the output buffer and the memory cell array;
A second wiring that is provided independently of the first wiring and connects an output node of the input buffer and an input node of the data comparison circuit;
A semiconductor device comprising:
The semiconductor device according to claim 1, further comprising a first switching circuit that connects the output node of the input buffer to the first or second wiring.
A data register that is provided independently of the memory cell array and holds test write data;
2. The semiconductor device according to claim 1, wherein the data comparison circuit compares the test write data held in the data register with test read data supplied via the second wiring. .
A third wiring provided independently of the first and second wirings and supplied with the test write data from the data register;
4. The semiconductor device according to claim 3, further comprising: a second switching circuit that connects one of the first and third wirings to the memory cell array. 5.
The test write data and the test read data are both composed of parallel data of a plurality of bits,
4. The data comparison circuit according to claim 3, wherein the data comparison circuit outputs a pass signal in response to the fact that a plurality of bits constituting the test write data and a plurality of bits constituting the test read data all match. Semiconductor device.
The data comparison circuit outputs a fail signal in response to the fact that at least one bit of the plurality of bits constituting the test write data and the plurality of bits constituting the test read data do not match. The semiconductor device according to claim 5.
The semiconductor device according to claim 6, further comprising a holding circuit connected between the data comparison circuit and the second terminal and holding the fail signal.
A third terminal to which an address signal designating any of the plurality of memory cells included in the memory cell array is input;
The semiconductor device according to claim 3, wherein the test write data is supplied to the data register through the third terminal.
2. The semiconductor device according to claim 1, further comprising a gate circuit for fixing the second wiring to a predetermined logic level.
The data comparison circuit is activated in response to the enable signal being at a first logic level;
The semiconductor device according to claim 9, wherein the gate circuit fixes the second wiring to the predetermined logic level in response to the enable signal being a second logic level.
The semiconductor device according to claim 1, wherein the first terminal has a smaller planar size than the second terminal.
The semiconductor device according to claim 11, further comprising a fourth terminal connected in parallel to the second terminal and having the same planar size as the first terminal.
A first terminal;
First and second wirings;
An output buffer having an output node connected to the first terminal;
An input buffer having an input node connected to the first terminal;
A memory cell array;
A data comparison circuit connected to the second wiring;
A switching circuit for connecting an output node of the input buffer to the first or second wiring based on a switching signal;
The first wiring connects the memory cell array, the input node of the output buffer, and the switching circuit to each other,
The semiconductor device, wherein the second wiring connects the switching circuit and the data comparison circuit to each other.
A data register that is provided independently of the memory cell array and holds test write data;
The semiconductor device according to claim 13, wherein the data comparison circuit compares the test write data held in the data register with test read data supplied via the second wiring. .
15. The semiconductor device according to claim 14, further comprising a second terminal connected to the data comparison circuit and outputting a signal indicating a result of the comparison.
The semiconductor device according to claim 15, wherein the first terminal has a smaller plane size than the second terminal.