JP2018137486A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device.SOLUTION: A semiconductor device includes first and second semiconductor components which are mounted on an interposer mounted on a wiring board and electrically connected with each other via the interposer. The interposer has a plurality of wiring layers including first, second and third wiring layers which are sequentially laminated from a reference principal surface side. The interposer sandwiched by the first semiconductor component and the second semiconductor component has a first region in which a ratio of reference potential wiring in the third wiring layer is greater than a ratio of reference potential wiring in the first wiring layer. Further, in the first region, a ratio of signal wiring in the first wiring layer is greater than a ratio of signal wiring in the third wiring layer.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a semiconductor device, for example, to a technique effective when applied to a semiconductor device in which a plurality of semiconductor components such as a semiconductor chip are electrically connected to each other via an interposer.

  JP 2010-538358 (Patent Document 1), JP 2013-138177 A (Patent Document 2), JP 2014-11169 (Patent Document 3), US Pat. No. 8,653,676 (Patent Document 4) ) And Japanese Patent Application Laid-Open No. 2014-11284 (Patent Document 5) describe a semiconductor device in which a plurality of semiconductor chips are electrically connected to each other through an interposer.

Japanese translation of PCT publication 2010-538358 JP 2013-138177 A JP 2014-11169 A US Pat. No. 8,653,676 JP 2014-11284 A

  There is a technique for electrically connecting a plurality of semiconductor components to each other via an interposer. In addition, when an interposer is mounted on a wiring board serving as a base material of a semiconductor package, the package strength can be secured by the wiring board, so that the arrangement density of a plurality of wirings formed on the interposer can be improved. Further, when a plurality of wiring layers are provided in the interposer, the number of wirings connecting the plurality of semiconductor components can be further increased. However, it has been found that when a plurality of wiring layers are provided in the interposer, there is a problem from the viewpoint of signal transmission reliability.

  For example, depending on the degree of insulation of the members constituting the interposer base material against high-frequency signals, a part of the current flowing through the signal transmission path may be consumed by the interposer base material, causing the signal to attenuate.

  For example, when signals are transmitted between a plurality of semiconductor components via the interposer, it is preferable to shorten the signal transmission path formed in the interposer.

  Further, for example, when a plurality of wiring layers are provided in the interposer, the thickness of each wiring layer is reduced, so that a technique for continuously setting the impedance value of the signal transmission path to a predetermined value is required.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes first and second semiconductor components mounted on an interposer mounted on a wiring board and electrically connected to each other through the interposer. The interposer includes a base material and a plurality of wiring layers arranged on the main surface of the base material. The plurality of wiring layers include a first wiring layer, a second wiring layer that is farther from the main surface of the substrate than the first wiring layer, and a third that is farther from the main surface than the second wiring layer. And a wiring layer. In the first area of the interposer sandwiched between the first semiconductor component and the second semiconductor component in a plan view, the ratio of the reference potential wiring that constitutes a part of the reference potential transmission path is The ratio of the reference potential wiring in the third wiring layer is larger than the ratio of the reference potential wiring in the first wiring layer. In the first region, the ratio of the signal wiring constituting a part of the signal transmission path is the ratio of the signal wiring in the first wiring layer to the ratio of the signal wiring in the third wiring layer. More than.

  According to the one embodiment, the reliability of the semiconductor device can be improved.

It is a top view of the semiconductor device which is one embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is explanatory drawing which shows the example of a circuit structure when the semiconductor device shown in FIGS. 1-3 is mounted in a mounting substrate. It is an expanded sectional view of the A section of FIG. It is an expanded sectional view of the B section of FIG. It is explanatory drawing which shows the relationship between the operating frequency of a signal transmission path | route, and signal loss. It is principal part sectional drawing which shows typically the state through which an electric current flows into a silicon substrate. FIG. 2 is an enlarged plan view showing an area around an area between a logic chip and a memory chip shown in FIG. 1 in an enlarged manner. FIG. 7 is a cross-sectional view of an essential part showing an example of an arrangement ratio for each type of transmission target in each wiring layer of the interposer shown in FIGS. FIG. 11 is a cross-sectional view of a main part showing an example of an arrangement ratio for each type of transmission target in each wiring layer of an interposer that is an example of examination different from FIG. 10. It is an enlarged plan view of the B section shown in FIG. FIG. 7 is an enlarged cross-sectional view of a semiconductor device which is a modified example with respect to FIG. 6. FIG. 14 is a modification of FIG. 12 and is an enlarged plan view of the semiconductor device shown in FIG. 13. It is an expanded sectional view along the AA line of FIG. FIG. 11 is a modification of FIG. 10, and is a cross-sectional view of a main part showing an example of an arrangement ratio for each type of transmission target in each wiring layer of the interposer shown in FIGS. FIG. 7 is an enlarged plan view showing a structure example of a wiring layer below a layer in which a plurality of surface electrodes of the interposer shown in FIG. 6 is formed. FIG. 11 is a main part cross-sectional view illustrating a modification example of FIG. 10, illustrating an example of a distance between each wiring layer of the interposer and an arrangement ratio according to the type of transmission target. It is principal part sectional drawing which shows the other modification with respect to FIG. FIG. 20 is an explanatory diagram illustrating an outline of a manufacturing process of the semiconductor device described with reference to FIGS. FIG. 7 is an enlarged cross-sectional view of a semiconductor device which is a modified example with respect to FIG. 6. FIG. 22 is a modification of FIG. 10, and is a cross-sectional view of a main part illustrating an example of an arrangement ratio for each type of transmission target in each wiring layer of the interposer illustrated in FIG. 21. FIG. 23 is a modification of FIG. 22, and is a cross-sectional view of a main part illustrating an example of an arrangement ratio for each type of transmission target in each wiring layer of the interposer.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

(Embodiment 1)
In the present embodiment, as an example of a semiconductor device in which a plurality of semiconductor components are electrically connected to each other via an interposer, a plurality of semiconductor chips are formed on a so-called silicon interposer in which a plurality of wiring layers are formed on a silicon substrate. The mounted embodiment will be described. Specifically, the semiconductor device described by taking as an example in this embodiment includes a memory chip in which a memory circuit is formed, and a logic chip in which a control circuit for controlling the memory chip and an arithmetic processing circuit are formed. . Further, the memory chip and the logic chip are electrically connected via a silicon interposer, and a system is formed in one package. A semiconductor device in which a system is formed in one package is called SiP (System in Package). A semiconductor device in which a plurality of semiconductor chips are mounted in one package is called an MCM (Multi Chip Module).

<Overview of semiconductor devices>
First, the outline of the structure of the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 1 is a top view of the semiconductor device of the present embodiment, and FIG. 2 is a bottom view of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view taken along line AA in FIG. FIG. 4 is an explanatory diagram showing a circuit configuration example when the semiconductor device shown in FIGS. 1 to 3 is mounted on a mounting substrate.

  2 and 3 show an embodiment in which the number of terminals is small for ease of viewing. However, the number of terminals includes various modifications in addition to the modes shown in FIGS. For example, the number of solder balls 11 shown in FIG. 2 may be larger than the number shown in FIG. Further, in FIG. 3, one of the plurality of wirings 13 formed in each wiring layer is exemplarily shown for easy viewing. Further, in the example illustrated in FIG. 4, a typical transmission path among the many transmission paths included in the semiconductor device PKG1 is exemplarily illustrated.

  As shown in FIGS. 1 and 3, the semiconductor device PKG1 of the present embodiment is mounted on a wiring board (package board) 10, an interposer (relay board) 20A mounted on the wiring board 10, and an interposer 20A. A plurality of semiconductor chips 30 are provided. The plurality of semiconductor chips 30 are mounted side by side on the interposer 20A.

  Further, as shown in FIG. 2, a plurality of solder balls (external terminals, electrodes, external electrodes) 11 as external terminals are arranged in a matrix (array) on the lower surface 10b of the wiring board 10 which is a mounting surface of the semiconductor device PKG1. Are arranged in a matrix). Each of the plurality of solder balls 11 is connected to a land (external terminal, electrode, external electrode) 12 (see FIG. 3).

  A semiconductor device in which a plurality of external terminals (solder balls 11 and lands 12) are arranged in a matrix on the mounting surface side like the semiconductor device PKG1 is referred to as an area array type semiconductor device. Since the area array type semiconductor device PKG1 can effectively use the mounting surface (lower surface 10b) side of the wiring substrate 10 as a space for arranging external terminals, the mounting area of the semiconductor device PKG1 is increased even if the number of external terminals increases. It is preferable at the point which can suppress increase of this. In other words, the semiconductor device PKG1 in which the number of external terminals increases with higher functionality and higher integration can be mounted in a space-saving manner.

  As shown in FIG. 3, the wiring board 10 includes an upper surface (surface, chip mounting surface) 10t on which a plurality of semiconductor chips 30 are mounted via an interposer 20A, and a lower surface (surface, mounting) opposite to the upper surface 10t. Surface) 10b, and a side surface 10s disposed between the upper surface 10t and the lower surface 10b. Further, the wiring board 10 has a rectangular outer shape in plan view as shown in FIG.

  3, the interposer 20A includes an upper surface (surface, chip mounting surface) 20t on which a plurality of semiconductor chips (semiconductor components) 30 are mounted, and a lower surface (surface, mounting surface) opposite to the upper surface 20t. 20b, and a side surface 20s disposed between the upper surface 20t and the lower surface 20b. Further, the interposer 20A has a quadrangular outer shape in plan view as shown in FIG.

  As shown in FIG. 3, each of the plurality of semiconductor chips 30 includes a front surface (main surface, upper surface) 30t, a rear surface (main surface, lower surface) 30b opposite to the front surface 30t, and a front surface 30t and a rear surface 30b. Side surface 30s located between the two. Each of the plurality of semiconductor chips 30 has a quadrangular outer shape in plan view as shown in FIG.

  In the example shown in FIGS. 1 and 3, one of the plurality of semiconductor chips 30 is a memory chip 30A including a memory circuit, and the other is a logic chip 30B including a control circuit that controls the memory circuit. It is. In the example shown in FIGS. 1 and 3, each of the memory chip 30A and the logic chip 30B is directly connected to the interposer 20A. In other words, no substrate or other chip component is inserted between the memory chip 30A and the interposer 20A and between the logic chip 30B and the interposer 20A.

  Also, as shown in FIG. 4, the semiconductor device PKG1 of the present embodiment includes a system that operates by transmitting signals between the logic chip 30B and the memory chip 30A. The memory chip 30A includes a main memory circuit (memory circuit) that stores data communicated with the logic chip 30B. The logic chip 30B includes a control circuit that controls the operation of the main memory circuit of the memory chip 30A. Further, the logic chip 30B includes an arithmetic processing circuit that performs arithmetic processing on the input data signal. In FIG. 4, as an example, main circuits such as an arithmetic processing circuit and a control circuit are shown as a core circuit (main circuit) CORE1. However, the circuit included in the core circuit CORE1 may include circuits other than those described above. For example, the logic chip 30B may be formed with an auxiliary storage circuit (storage circuit) having a storage capacity smaller than that of the main storage circuit of the memory chip 30A, such as a cache memory that temporarily stores data.

  The logic chip 30B is formed with an external interface circuit (input / output circuit, external input / output circuit) IF1 that inputs and outputs signals to and from the external device 40. A signal line SIG for transmitting a signal between the logic chip 30B and the external device 40 is connected to the external interface circuit IF1. The external interface circuit IF1 is also connected to the core circuit CORE1, and the core circuit CORE1 can transmit signals to the external device 40 via the external interface circuit IF1.

  The logic chip 30B is formed with an internal interface circuit (input / output circuit, internal input / output circuit) IF2 for inputting / outputting signals to / from an internal device (for example, the memory chip 30A). The internal interface circuit IF2 is connected to a data line (signal line) DQ for transmitting a data signal and a control signal line (signal line) CMD for transmitting a control data signal such as an address signal and a command signal. The data line DQ and the control signal line CMD are each connected to the internal interface circuit IF2 of the memory chip 30A.

  In addition, the logic chip 30B includes a power supply circuit DRV1 that supplies a potential for driving the core circuit CORE1 and the input / output circuit. In the example shown in FIG. 4, a power supply line VD1 that supplies a power supply potential and a reference potential line VS1 that supplies a reference potential are connected to the power supply circuit DRV1.

  4 illustrates an example in which the pair of power supply line VD1 and the reference potential line VS1 are connected to the logic chip 30B, but the potential supplied to the logic chip 30B is not limited to the above two types. For example, the power supply circuit DRV1 supplies a voltage for driving the external interface circuit IF1 of the logic chip 30B, and supplies a voltage for driving the core circuit CORE1 of the logic chip 30B. And may be included. The power supply circuit DRV1 may include an internal interface power supply circuit that supplies a voltage for driving the internal interface circuit IF2 of the logic chip 30B. In this case, a plurality of power supply lines VD1 that supply a plurality of different power supply potentials are connected to the logic chip 30B.

  Further, the potential supplied to the reference potential line VS1 shown in FIG. 4 is, for example, a ground potential. However, since the drive voltage is defined by the difference between the first potential and the second potential that are different from each other, the potential supplied to the reference potential line VS1 may be a potential other than the ground potential.

  A circuit in which circuits necessary for the operation of a certain device or system are formed on one semiconductor chip 30 like the logic chip 30B is called SoC (System on a Chip). By the way, if the main memory circuit shown in FIG. 4 is formed in the logic chip 30B, the system can be configured by one logic chip 30B. However, the required capacity of the main memory circuit differs depending on the device or system to be operated. Therefore, the versatility of the logic chip 30B can be improved by forming the main memory circuit in the semiconductor chip 30 (that is, the memory chip 30A) different from the logic chip 30B. Further, by connecting a plurality of memory chips 30A according to the required storage capacity of the main memory circuit, the degree of freedom in designing the capacity of the memory circuit included in the system is improved.

  In the example illustrated in FIG. 4, the memory chip 30 </ b> A includes a main memory circuit. In FIG. 4, the main memory circuit is shown as the core circuit (main circuit) CORE2 of the memory chip 30A. However, the circuit included in the core circuit CORE2 may include a circuit other than the main memory circuit.

  The memory chip 30A is formed with an internal interface circuit (internal input / output circuit) IF2 for inputting / outputting signals to / from an internal device (for example, the logic chip 30B).

  Further, the memory chip 30A includes a power supply circuit (drive circuit) DRV2 that supplies a potential for driving the core circuit CORE2. In the example shown in FIG. 4, a power supply line VD2 that supplies a power supply potential and a reference potential line VS1 that supplies a reference potential are connected to the power supply circuit DRV2. In the example shown in FIG. 4, the power supply potential supplied to the power supply line VD1 and the power supply potential supplied to the power supply line VD2 are supplied from the power supply 50 provided outside the semiconductor device PKG1, respectively.

  FIG. 4 shows an example in which the pair of power supply line VD2 and reference potential line VS1 are connected to the memory chip 30A. In the example shown in FIG. 4, the logic chip 30B and the memory chip 30A are electrically connected through the power supply line VD3 for supplying the power supply potential for driving the internal interface circuit IF2 and the reference potential line VS2, respectively. Yes. However, the method of supplying a potential to the memory chip 30A has various modifications other than the above. For example, the power supply potential for driving the internal interface circuit IF2 of the logic chip 30B and the power supply potential for driving the internal interface circuit IF2 of the memory chip 30A may be supplied independently. In this case, the power supply 50 and the memory chip 30A shown in FIG. 4 are electrically connected via the power supply line VD3.

  In the example shown in FIG. 4, the plurality of transmission paths that electrically connect the logic chip 30B and the memory chip 30A include the reference potential line VS2 in addition to the data line DQ and the control signal line CMD. The reference potential line VS2 is a path for transmitting a reference signal of a data signal transmitted through the data line DQ, for example. For example, a ground potential is supplied as a reference potential to the reference potential line VS2. When supplying the ground potential to the reference potential line VS2 and the reference potential line VS1, respectively, the potential is more stable when the reference potential line VS2 and the reference potential line VS1 are connected. Therefore, as shown with a dotted line in FIG. 4, it is preferable that the reference potential line VS2 and the reference potential line VS1 are connected in the interposer 20A. However, the reference reference potential line VS2 may be supplied with a potential other than the ground potential as long as variation in potential in the transmission path can be reduced. For example, the power supply potential of the input / output power supply circuit may be used as a reference potential for reference.

  In the example shown in FIG. 4, the power supply line VD2 for supplying the power supply potential to the memory chip 30A and the reference potential line VS1 for supplying the reference potential to the memory chip 30A are not connected to the memory chip 30A. It is connected to the. However, as a modification to FIG. 4, the power supply line VD1 and the reference potential line VS2 may be connected to the memory chip 30A via the logic chip 30B.

<Configuration of each part>
Next, main components constituting the semiconductor device PKG1 shown in FIGS. FIG. 5 is an enlarged cross-sectional view of a portion A in FIG. FIG. 6 is an enlarged cross-sectional view of a portion B in FIG.

  The wiring board 10 shown in FIGS. 1 to 5 is a board provided with a transmission path for supplying an electric signal and a potential between the semiconductor device PKG1 and the mounting board 60 (see FIG. 4). The wiring board 10 has a plurality of wiring layers (eight layers in the example shown in FIG. 3) that electrically connect the upper surface 10t side and the lower surface 10b side. The plurality of wirings 13 provided in each wiring layer are covered with an insulating layer 14 that insulates between the plurality of wirings 13 and between adjacent wiring layers.

  The wiring substrate 10 shown in FIG. 3 has a plurality of laminated insulating layers 14, and the middle insulating layer 14 is a core in which a fiber material such as glass fiber is impregnated with a resin material such as an epoxy resin, for example. It is a layer (core material). The insulating layers 14 formed on the upper surface and the lower surface of the core layer are formed by, for example, a buildup method. However, as a modified example with respect to FIG. 3, a so-called coreless substrate that does not have the insulating layer 14 serving as a core layer may be used.

  In addition, the wiring board 10 includes via wirings 15 that are interlayer conductive paths that are provided between the wiring layers and connect the stacked wiring layers in the thickness direction. A plurality of bonding pads (terminals, chip mounting surface side terminals, electrodes) 16 are formed on the upper surface 10 t of the wiring substrate 10. Of the plurality of wiring layers of the wiring substrate 10, the wiring 13 provided in the uppermost wiring layer (the wiring layer on the uppermost surface 10 t side) is formed integrally with the bonding pad 16. In other words, the bonding pad 16 can be considered as a part of the wiring 13. Further, when the bonding pad 16 and the wiring 13 are considered separately, the portion exposed from the insulating film 17 on the upper surface 10t of the wiring substrate 10 is defined as the bonding pad 16 and the portion covered with the insulating film 17 is defined as the wiring 13. Can do.

  On the other hand, a plurality of lands (terminals, solder connection pads) 12 are formed on the lower surface 10 b of the wiring substrate 10. Solder balls 11 are connected to each of the plurality of lands 12, and the mounting substrate 60 and the semiconductor device PKG1 shown in FIG. 4 are electrically connected via the solder balls 11 shown in FIG. That is, the plurality of solder balls 11 function as external connection terminals of the semiconductor device PKG1.

  The plurality of solder balls 11 and the plurality of lands 12 are electrically connected to the plurality of bonding pads 16 on the upper surface 10 t side via the plurality of wirings 13 of the wiring substrate 10. Of the plurality of wiring layers of the wiring board 10, the wiring 13 provided in the lowermost wiring layer (the wiring layer on the lowermost surface 10 b side) is formed integrally with the land 12. In other words, the land 12 can be considered as a part of the wiring 13. Further, when the land 12 and the wiring 13 are distinguished from each other, the portion exposed from the insulating film 17 on the lower surface 10 b of the wiring substrate 10 can be defined as the land 12, and the portion covered with the insulating film 17 can be defined as the wiring 13. .

  Further, as a modification to FIG. 3, the land 12 itself may function as an external connection terminal. In this case, the solder balls 11 are not connected to the lands 12, and each of the lands 12 is exposed from the insulating film 17 on the lower surface 10 b of the wiring substrate 10. As another modification to FIG. 3, a thin solder film may be connected instead of the ball-shaped solder ball 11, and this solder film may function as an external connection terminal.

  The upper surface 10 t and the lower surface 10 b of the wiring substrate 10 are covered with an insulating film (solder resist film) 17. The wiring 13 formed on the upper surface 10 t of the wiring substrate 10 is covered with an insulating film 17. An opening is formed in the insulating film 17, and at least a part (bonding region) of the plurality of bonding pads 16 is exposed from the insulating film 17 in the opening. Further, the wiring 13 formed on the lower surface 10 b of the wiring substrate 10 is covered with an insulating film 17. An opening is formed in the insulating film 17, and at least a part of the plurality of lands 12 (joined portions with the solder balls 11) is exposed from the insulating film 17 in the opening.

  As shown in FIG. 5, the semiconductor device PKG1 includes an interposer 20A mounted on the wiring board 10. The interposer 20 </ b> A is a relay board that is interposed between the wiring board 10 and the plurality of semiconductor chips 30. In the present embodiment, the interposer 20A includes a silicon substrate (base material) 21 having a main surface 21t and a plurality of wiring layers M1, M2, and M3 arranged on the main surface 21t. As shown in FIG. 5, when a layer in which a plurality of surface electrodes 25 are formed is regarded as a wiring layer M4, in the example shown in FIG. 5, four wiring layers are laminated. A plurality of wirings (conductor patterns) 22 are formed in each of the plurality of wiring layers M1, M2, and M3. The plurality of wirings 22 are covered with an insulating layer 23 that insulates between the plurality of wirings 22 and between adjacent wiring layers. The insulating layer 23 is an inorganic insulating layer made of an oxide of a semiconductor material such as silicon oxide (SiO).

  A plurality of surface electrodes (electrode pads, terminals) 25 are formed on the wiring layer M3 of the interposer 20A. A part of each of the plurality of surface electrodes 25 is exposed from the passivation film 26 which is a protective insulating film on the upper surface 20t of the interposer 20A. The surface electrode 25 is electrically connected to an electrode (surface electrode, pad) 33 of the semiconductor chip 30 via a bump electrode 35 connected to an exposed portion of the surface electrode 25.

  A plurality of backside electrodes (electrodes, pads, terminals) 27 are formed on the lower surface 20b of the interposer 20A. The plurality of back surface electrodes 27 are exposed on the lower surface 20b of the interposer 20A located on the opposite side of the main surface 21t of the silicon substrate 21. The back electrode 27 is electrically connected to the bonding pad 16 of the wiring substrate 10 via the bump electrode 28 connected to the back electrode 27.

  The interposer 20A includes a plurality of through electrodes 24 that penetrate the silicon substrate 21 in the thickness direction (the direction from one surface to the other surface of the main surface 21t and the lower surface 20b). The plurality of through electrodes 24 are conductive paths formed by embedding a conductor such as copper (Cu) in a through hole formed to penetrate the silicon substrate 21 in the thickness direction. Each of the plurality of through electrodes 24 has one end connected to the back electrode 27 and the other end connected to the wiring 22 of the wiring layer M1. That is, the plurality of front surface electrodes 25 and the plurality of back surface electrodes 27 of the interposer 20 </ b> A are electrically connected via the plurality of wirings 22 and the plurality of through electrodes 24, respectively.

  The wiring board 10 described above is a support base material for the semiconductor device PKG1. In order to exhibit the function as a support substrate, it is preferable to improve rigidity and strength. For this reason, it is difficult to finely process the plurality of wirings 13 formed on the wiring board 10.

  On the other hand, since the interposer 20 </ b> A is a relay board mounted on the wiring board 10, the rigidity and strength of the board may be lower than that of the wiring board 10. For this reason, the wiring density of the plurality of wirings 22 formed in the interposer 20 </ b> A can be improved as compared with the wirings 13 of the wiring board 10.

  In particular, the interposer 20A of the present embodiment has a silicon substrate (base material) 21 that is a semiconductor substrate as shown in FIG. 5, and a plurality of wiring layers M1, M2, M3 on the main surface 21t of the silicon substrate 21. Have a laminated structure. As described above, when forming the plurality of wirings 22 on the semiconductor substrate, the wiring density can be improved by using the same process as the process of forming the wirings on the semiconductor wafer.

  When a process for forming wiring on a semiconductor wafer is used, the thickness of each wiring layer and the distance between wiring layers are also reduced. For example, the thickness of the wiring layers M1, M2, and M3 shown in FIGS. 5 and 6, that is, the thickness of each of the plurality of wirings 22 is thinner than the thickness of the wiring 13 of the wiring board 10. In FIGS. 5 and 6, the wiring 13 of the wiring board 10 and the wiring 22 of the interposer 20 </ b> A are shown in one figure, so that the thickness of the wiring 13 is less than twice the thickness of the wiring 22. However, the thickness of the wiring 13 is several times to several tens of times the value of the thickness of the wiring 22 described above.

  In addition, the distance between each of the wiring layers M1, M2, and M3 and the distance between the main surface 21t of the silicon substrate 21 and the wiring layer M1 are smaller than the thickness of the wiring 22. The distance between each of the wiring layers M1, M2, and M3 and the distance between the main surface 21t of the silicon substrate 21 and the wiring layer M1 are about half of the thickness of the wiring 22 formed in the wiring layers M1, M2, and M3. It is. Note that the distance between the uppermost wiring layer M4 on which the plurality of surface electrodes 25 are formed and the wiring layer M3 is larger than the distance between the wiring layers M1, M2, and M3. For example, the distance between the wiring layer M4 and the wiring layer M3 is about the same as the thickness of the wiring 22.

  As described above, the interposer 20A can improve the wiring density as compared with the wiring substrate 10, and is particularly effective in increasing the number of signal transmission paths connecting the plurality of semiconductor chips 30. In particular, as in the example shown in FIG. 4 of the present embodiment, when the number of signal transmission paths for connecting the logic chip 30B and the memory chip 30A is increased, the interposer 20A is provided to form the wiring board 10. The number of wirings 13 (see FIG. 3) to be performed can be reduced.

  In the present embodiment, the silicon substrate 21 widely used in the semiconductor wafer manufacturing process is used as a base material. Therefore, the silicon substrate 21 shown in FIG. 5 uses silicon, which is a semiconductor material, as a base material (main component). In general, a semiconductor substrate used for manufacturing a semiconductor chip is generally doped with an impurity element constituting p-type or n-type conductive characteristics in a semiconductor material as a base material. For this reason, when a general-purpose semiconductor wafer is used as the silicon substrate 21, the silicon substrate 21 contains an impurity element constituting p-type or n-type conductive characteristics.

  However, various modifications can be applied to the silicon substrate 21 of the present embodiment. For example, a semiconductor material other than silicon may be used as a base material for the semiconductor substrate. In addition, a semiconductor in which no impurity element is doped in a semiconductor material can be used as a semiconductor substrate.

  As shown in FIG. 6, the semiconductor device PKG1 includes a plurality of semiconductor chips 30 mounted on the upper surface 20t of the interposer 20A. Each of the plurality of semiconductor chips 30 includes a silicon substrate (base material) 31 having a main surface 31t, and a wiring layer 32 disposed on the main surface 31t. In FIGS. 5 and 6, one wiring layer 32 is shown for the sake of clarity. For example, the wiring layer 32 shown in FIGS. 5 and 6 includes the wiring layers M1, M2, and the like of the interposer 20A. A plurality of wiring layers that are thinner than M3 are stacked. Although not shown for ease of viewing, a plurality of wirings are formed in each of the plurality of wiring layers 32. The plurality of wirings are covered with an insulating layer that insulates between the plurality of wirings and between adjacent wiring layers. The insulating layer is an inorganic insulating layer made of an oxide of a semiconductor material such as silicon oxide (SiO).

  Also, a plurality of semiconductor elements such as transistor elements or diode elements are formed on the main surface 31t of the silicon substrate 31 provided in each of the plurality of semiconductor chips 30. The plurality of semiconductor elements are electrically connected to the plurality of electrodes 33 formed on the surface 30 t side through the plurality of wirings of the wiring layer 32.

  In the present embodiment, each of the plurality of semiconductor chips 30 is mounted on the upper surface 20t of the interposer 20A with the surface 30t and the upper surface 20t of the interposer 20A facing each other. Such a mounting method is called a face-down mounting method or a flip-chip connection method. In the flip chip connection method, the semiconductor chip 30 and the interposer 20A are electrically connected as follows.

  A plurality of electrodes (surface electrodes, pads, terminals) 33 are formed on the wiring layer 32 of the semiconductor chip 30. A part of each of the plurality of electrodes 33 is exposed from the passivation film 34 which is a protective insulating film on the surface 30 t of the semiconductor chip 30. The electrode 33 is electrically connected to the surface electrode 25 of the interposer 20 </ b> A via the bump electrode 35 connected to the exposed portion of the electrode 33.

  In the present embodiment, as shown in FIG. 4, a part of the plurality of transmission paths connected to the memory chip 30A is not connected to the wiring board 10, and the logic chip 30B is connected via the interposer 20A. Connected to. In the example shown in FIG. 4, the data line DQ and the control signal line CMD are electrically separated from the wiring board 10. On the other hand, among the plurality of transmission paths connected to the memory chip 30A, the power supply line VD2 and the reference potential line VS1 for supplying the power supply potential for driving the circuit of the memory chip 30A are electrically connected to the wiring board 10. ing. In the transmission path for electrically connecting the logic chip 30B and the memory chip 30A, the reference potential line VS2 used for reference of the signal line may be separated from the wiring board 10.

<Details of transmission path for electrically connecting semiconductor chips>
Next, the details of the signal transmission path for electrically connecting the logic chip 30B and the memory chip 30A as shown in FIG. 4 will be described.

  As a typical example of the SiP type semiconductor device, there is a configuration in which a logic chip 30B and a memory chip 30A are mounted in one package as in the present embodiment. In order to improve the performance of the SiP type semiconductor device having such a configuration, a technique for improving the transmission speed of the signal transmission path connecting the logic chip 30B and the memory chip 30A is required. For example, in the signal transmission path shown in FIG. 4, each of the plurality of data lines DQ is designed to transmit a data signal at a transmission rate of 1 Gbps (1 gigabit per second) or more. In order to increase the transmission speed of each of the plurality of signal transmission paths, it is necessary to increase the number of transmissions per unit time (hereinafter referred to as high clocking).

  As another method for improving the signal transmission speed between the logic chip 30B and the memory chip 30A, there is a method of increasing the amount of data transmitted at a time by increasing the width of the data bus of the internal interface ( (Hereinafter referred to as bus width expansion). Further, there is a method of applying a combination of the above-described bus width expansion and high clock. In this case, many high-speed signal transmission paths are required. Therefore, a method of electrically connecting the logic chip 30B and the memory chip 30A via the interposer 20A as in the present embodiment is effective.

  For example, the memory chip 30A shown in FIG. 4 is a so-called wide I / O memory having a data bus width of 512 bits or more. Specifically, the memory chip 30A includes, for example, four channels having a data bus width of 128 bits, and the total bus width of the four channels is 512 bits. In addition, the number of transmissions per unit time of each channel is increased to a high clock, for example, 1 Gbps or more.

  However, as a result of examining the configuration in which the logic chip 30B and the memory chip 30A are electrically connected through an interposer having a plurality of wiring layers, the present inventor has a problem from the viewpoint of signal transmission reliability. I found out.

  First, according to the study of the present inventor, when high-speed signal transmission is performed on an interposer having a silicon substrate, part of the signal energy is converted into heat energy and consumed, and transmission loss (hereinafter referred to as signal loss). It was found that there is a case where At this time, as shown in FIG. 7, it was found that the degree of signal loss is small when the signal frequency is low, but the degree of signal loss increases rapidly as the signal frequency increases.

  FIG. 7 is an explanatory diagram showing the relationship between the operating frequency of the signal transmission path and the signal loss. FIG. 8 is a cross-sectional view of a principal part schematically showing a state where a current flows through the silicon substrate. In FIG. 7, the frequency at which a signal is transmitted is shown logarithmically on the horizontal axis, and the degree of signal loss at each frequency is shown on the vertical axis. In FIG. 7, the operating frequency band of the data line DQ shown in FIG. 4 is shown as a frequency band F2, and the operating frequency band of the control signal line CMD is shown as a frequency band F1. In FIG. 8, the surface electrode 25 is indicated by a dotted line in order to clearly show that the wiring layer M4 is a layer for forming the surface electrode 25.

  Here, the behavior when a signal current flows through the wiring 22 shown in FIG. 8 will be examined. The silicon substrate 21 shown in FIG. 8 contains an impurity element that constitutes p-type or n-type conductive characteristics, like the silicon substrate 21 included in the interposer 20A of the present embodiment shown in FIG.

  When a signal current flows through the wiring 22 illustrated in FIG. 8, an electromagnetic field is generated around the wiring 22. When the frequency of the signal current flowing through the wiring 22 is low, the current CF shown in FIG. For this reason, for example, when a signal current is transmitted in the frequency band F1 shown in FIG. 7, even if the frequency changes, the degree of signal loss hardly changes.

  However, according to the study by the present inventor, for example, when a signal current is transmitted at a high frequency as in the frequency band F2 shown in FIG. 7, the current CF easily flows through the silicon substrate 21 shown in FIG. It was. In addition, since the silicon substrate 21 acquires conductivity by doping a semiconductor material as a base material with impurities, a current CF flows through the silicon substrate 21 as compared with a conductor such as the wiring 22. The resistance value is large. For this reason, the electric energy (electromagnetic field and current CF generated thereby) generated by the flow of the current CF is converted into heat energy and consumed. As a result, the current value of the signal current flowing through the wiring 22 decreases. That is, signal loss occurs in the signal transmission path. According to the study by the inventor of the present application, when the operating frequency of the signal transmission path becomes 1 GHz (gigahertz) or more, the degree of signal loss increases rapidly.

  Therefore, from the viewpoint of improving the reliability of signal transmission, it is preferable to take measures to suppress an increase in signal loss in the frequency band F2 where the degree of signal loss is large. According to the present embodiment, it is possible to suppress the increase in signal loss described above. Hereinafter, the reason will be described in order.

  FIG. 9 is an enlarged plan view showing an area around the logic chip and the memory chip shown in FIG. 1 in an enlarged manner. FIG. 10 is a cross-sectional view of the main part showing an example of the arrangement of wirings according to the type of transmission target in the cross section taken along the line AA of FIG. In FIG. 9, a plurality of wirings 22 that electrically connect the memory chip 30 </ b> A and the logic chip 30 </ b> B, and a plurality of surface electrodes 25 of the interposer 20 </ b> A connected to both ends of the wiring 22 are indicated by dotted lines. FIG. 9 schematically shows that the memory chip 30A and the logic chip 30B are electrically connected via a plurality of wirings 22. The numbers and positions of the wirings 22 and the surface electrodes 25 are shown in FIG. The embodiment shown in FIG. In FIG. 9, a region 22 </ b> A sandwiched between adjacent semiconductor chips and a peripheral portion of a region 22 </ b> B where a plurality of wirings 22 that electrically connect adjacent semiconductor chips are formed are indicated by two-dot chain lines. Moreover, since the region 22A and the region 22B overlap, the region 22A is provided with a pattern for easy viewing. FIG. 10 is a cross-sectional view. In order to identify the type of transmission path formed by the plurality of wirings 22, different patterns are given according to the type of transmission target. Specifically, hatching is applied to the data signal wiring 22DQ constituting a part of the data line DQ shown in FIG. 4, and a dot pattern is applied to the control signal wiring 22CMD constituting a part of the control signal line CMD shown in FIG. , Respectively. In addition, the reference potential wiring 22VS serving as a reference potential transmission path is blank without any pattern. Also, the silicon substrate 21 is blank without any pattern. In FIG. 10, the surface electrode 25 is indicated by a dotted line in order to clearly show that the wiring layer M <b> 4 is a layer for forming the surface electrode 25.

  First, from the viewpoint of improving the reliability of signal transmission between adjacent semiconductor chips, an area where the wiring structure needs to be studied will be described. As shown in FIG. 9, the memory chip 30A and the logic chip 30B included in the semiconductor device PKG1 of the present embodiment are electrically connected through a plurality of wirings 22 of the interposer 20A. When performing high-speed signal transmission, it is preferable to shorten the signal transmission path. For this reason, in plan view, the wiring 22 that electrically connects the memory chip 30A and the logic chip 30B is mainly disposed in a region 22A of the interposer 20A sandwiched between the memory chip 30A and the logic chip 30B. For this reason, when the electrical characteristics of the wiring 22 are examined, the wiring structure in the region 22A shown in FIG. 9 may be examined, and the wiring structure in other regions is not particularly limited.

  Strictly speaking, the region to which the plurality of wirings 22 electrically connecting the memory chip 30A and the logic chip 30B are connected is a plurality of wirings connected to both ends of the plurality of wirings 22, as shown in FIG. A region 22 </ b> B between the surface electrodes 25. However, in order to shorten the signal transmission path, each of the plurality of surface electrodes 25 connected to both ends of the plurality of wirings 22 is often formed close to the opposite sides of the adjacent semiconductor chip. . In this case, as shown in FIG. 9, most of the region 22B overlaps with the region 22A. Therefore, at least by improving the wiring structure of the region 22A, the reliability of signal transmission between adjacent semiconductor chips can be improved. However, for example, when the length of the wiring 22 connecting the adjacent semiconductor chips is long and each of the plurality of surface electrodes 25 is separated from the opposite sides of the adjacent semiconductor chip, the wiring in the region 22B In some cases, it is preferable to consider the structure.

  Hereinafter, the wiring structure in the region 22A shown in FIG. 9 will be described. However, the wiring structure described below can also be applied when considering the wiring structure in the region 22B.

  As shown in FIG. 10, the interposer 20A included in the semiconductor device PKG1 of the present embodiment includes a wiring layer M1, a wiring layer M2 that is farther from the main surface 21t of the silicon substrate 21 than the wiring layer M1, and a wiring layer M2. Also includes a wiring layer M3 separated from the main surface 21t.

  In the region 22A (see FIG. 9), the ratio (occupancy) of the reference potential wiring 22VS constituting a part of the reference potential transmission path among the plurality of wirings 22 is the reference potential wiring in the wiring layer M3. The ratio of 22VS is larger than the ratio (occupancy) of the reference potential wiring 22VS in the wiring layer M1. The ratio of the reference potential wiring 22VS in the wiring layer M1 (or wiring layer M3) is the ratio of the reference potential wiring 22VS to the total plane area of the conductor patterns formed in the wiring layer M1 (or wiring layer M3). Occupancy rate. Further, the ratio of the signal wiring in the wiring layer M1 (or wiring layer M3) means the occupation ratio of the signal wiring with respect to the total plane area of the conductor pattern formed in the wiring layer M1 (or wiring layer M3). To do. Hereinafter, in this specification, when it is described as the ratio of a certain type of wiring in a certain wiring layer, it has the same meaning as described above, unless it is explained that it is used in a different meaning.

  In the region 22A (see FIG. 9), the ratio (occupancy) of the signal wiring (data signal wiring 22DQ and control signal wiring 22CMD) that constitutes a part of the signal transmission path among the plurality of wirings 22. The ratio of the signal wiring in the wiring layer M1 is larger than the ratio (occupancy) of the signal wiring in the wiring layer M3.

  The configuration of the interposer 20A of the present embodiment can also be expressed as follows. That is, in the wiring layer M1 having a relatively short distance to the main surface 21t of the silicon substrate 21, signal wiring (data signal wiring 22DQ or control signal wiring 22CMD) is mainly provided, and the main surface of the silicon substrate 21 is provided. In the wiring layer M3 whose distance up to 21t is relatively long, the reference potential wiring 22VS is mainly provided. Thereby, the following effects are acquired.

  That is, the distribution of the electromagnetic field generated when a signal is supplied to the wiring 22 can be controlled by the reference potential wiring 22VS. When the area of the reference potential wiring 22VS provided below the wiring 22 through which the signal current flows is small and the area of the reference potential wiring 22VS provided above the wiring 22 is large, the electromagnetic field is mainly the same as the wiring 22. It becomes distributed in layers or above. For this reason, even when the signal current flowing through the wiring 22 is a high-frequency signal, signal loss due to the current CF (see FIG. 8) flowing through the silicon substrate 21 can be suppressed.

  Note that the reference potential supplied to the reference potential wiring 22VS shown in FIG. 10 is, for example, the same potential as the potential (eg, ground potential) supplied to the reference potential line VS1 shown in FIG. Further, controlling the distribution of the electromagnetic field generated when a signal is passed through the wiring 22 may be a transmission path to which a potential other than the ground potential is supplied. For example, the power supply potential supplied for driving the input / output circuit shown in FIG. 4 may be used.

  By the way, the inventor of the present application has studied the study example shown in FIG. 11 as another method for suppressing signal loss. FIG. 11 is a cross-sectional view of the main part showing an example of the arrangement ratio for each type of transmission target in each wiring layer of the interposer, which is an examination example different from FIG. The interposer 20H shown in FIG. 11 is different from the interposer 20A shown in FIG. 10 in the following points. That is, in the wiring layer M1 that is relatively close to the main surface 21t of the silicon substrate 21, the reference potential wiring 22VS is mainly provided, and the wiring layer that is relatively far from the main surface 21t of the silicon substrate 21. In M3, signal wiring is mainly provided. In other words, in the interposer 20H shown in FIG. 11, the reference potential wiring 22VS is provided between the plurality of signal wirings and the silicon substrate 21.

  The inventor of the present application provides a reference potential wiring 22VS between a plurality of signal wirings and the silicon substrate 21, thereby shielding an electromagnetic field generated when a high frequency signal flows through the signal wiring by the reference potential wiring 22VS. We examined the configuration to do. However, in the case of the interposer 20H shown in FIG. 11, the shield becomes a mesh shape for the sake of manufacturing, and the shielding effect is diminished, so that it is difficult to suppress signal loss compared to the interposer 20A shown in FIG. I understood. The reason for this will be described below.

  When a plurality of wiring layers are stacked on the silicon substrate 21, the density of the wirings 22 can be increased by using a process of forming the wiring layers on the semiconductor wafer. However, when the flatness of the surface of each wiring layer as a base is low, the wiring width of the wiring 22 cannot be made sufficiently small. For this reason, as a preparation for laminating the wiring layers, it is necessary to flatten the wiring layer as a base. As a planarization technique, for example, there is a polishing technique called CMP (Chemical Mechanical Polishing). CMP is a technique in which a polishing surface is flattened by embedding a soft insulating layer 23 (see FIG. 6) between metal patterns, so that a gap is required between the metal patterns in which the insulating layer 23 is embedded. Therefore, it is necessary to provide a plurality of gaps between the metal films, such as a mesh pattern, and the coverage of the metal film (the occupation ratio of the metal film on the surface on which the metal film is formed) needs to be limited to about 50%, for example.

  In order to shield the electromagnetic field generated when the high frequency signal flows through the signal wiring (for example, the data signal wiring 22DQ) shown in FIG. 11 by the reference potential wiring 22VS, the reference potential wiring provided in the wiring layer M1. Although it is necessary to increase the area of 22VS, it is difficult to form the planar shape of the reference potential wiring 22VS into a sheet shape. For this reason, the electromagnetic field described above wraps around the silicon substrate 21 through the gap between the conductor patterns constituting the reference potential wiring 22VS. That is, it is difficult to obtain a sufficient shielding effect by the reference potential wiring 22VS.

  On the other hand, in the present embodiment shown in FIG. 10, the reference potential wiring 22VS is used as a conductor pattern for controlling the distribution of the electromagnetic field. Therefore, for example, the planar shape of the reference potential wiring 22VS shown in FIG. 10 is a linear pattern extending from one of the memory chip 30A and the logic chip 30B to the other like the wiring 22 shown by a dotted line in FIG. Even in some cases, signal loss can be suppressed. For example, even if the planar shape of the reference potential wiring 22VS shown in FIG. 10 is a mesh pattern, signal loss can be suppressed. The reference potential wiring 22VS shown in FIG. 10 need not be used exclusively for controlling the distribution of the electromagnetic field. Therefore, a part of the electromagnetic field may be shielded by the reference potential wiring 22VS. Further, the reference potential wiring 22VS shown in FIG. 10 may constitute a part of the return current path of the high-speed signal.

  In the expression of the wiring structure described with reference to FIG. 10, the expression “the ratio of A is greater than the ratio of B” includes the case where the ratio of B is 0%. The expression “the ratio of A is smaller than the ratio of B” includes the case where the ratio of A is 0%. Hereinafter, when the expression “the ratio of A is greater (or less than the ratio of B)” is used in the present specification, the same meaning is used. For example, in the example shown in FIG. 10, the reference potential wiring 22VS is not formed in the wiring layer M1, and the ratio of the signal wiring in the wiring 22 formed in the wiring layer M1 in the region 22A (see FIG. 9) is 100%.

  However, as a modification to FIG. 10, the reference potential wiring 22VS may be formed in the wiring layer M1 in the region 22A (see FIG. 9). In this case, as described above, the ratio (occupancy) of the reference potential wiring 22VS constituting a part of the reference potential transmission path among the plurality of wirings 22 is the ratio of the reference potential wiring 22VS in the wiring layer M3. Is larger than the ratio (occupancy) of the reference potential wiring 22VS in the wiring layer M1. As a result, the electromagnetic field generated when high-speed signal transmission is performed is mainly distributed in the same layer as or above the wiring 22 and signal loss can be suppressed.

  Further, the wiring structure of the interposer 20A shown in FIG. 10 can also be expressed as follows. In the plurality of wirings (conductor patterns) 22 arranged in the wiring layer M1, the ratio of the reference potential wiring (reference potential conductor) 22VS constituting a part of the reference potential transmission path is the ratio of the signal transmission path. It is smaller than the proportion of the signal wiring (data signal wiring 22DQ or control signal wiring 22CMD) constituting a part. In the plurality of wirings 22 arranged in the wiring layer M3, the ratio of the reference potential wiring 22VS that forms part of the reference potential transmission path is the ratio of the signal wiring that forms part of the signal transmission path. More than

  When the above condition is satisfied, “in the wiring layer M1 whose distance to the main surface 21t of the silicon substrate 21 is relatively short, signal wiring (data signal wiring 22DQ or control signal wiring 22CMD) is mainly provided. In the wiring layer M3 that is relatively far from the main surface 21t of the silicon substrate 21, the reference potential wiring 22VS is mainly provided. Therefore, an electromagnetic field generated when high-speed signal transmission is performed is mainly distributed in the same layer as or above the wiring 22. As a result, according to the above configuration, signal loss can be suppressed.

  As shown in FIG. 10, in the present embodiment, a control signal wiring 22CMD for transmitting a signal in a relatively low frequency band F1 (see FIG. 7) and a control signal are connected to the plurality of signal wirings. And a data signal wiring 22DQ through which a signal is transmitted in a higher frequency band F2 (see FIG. 7) than the wiring for wiring 22CMD. For example, in the example shown in FIG. 4, control data signals such as an address signal and a command signal transmitted through the control signal line CMD are transmitted at a frequency equal to or less than half that of the data signal transmitted through the data line DQ. As can be seen from FIG. 7, the degree of signal loss is lower in the frequency band F1 than in the frequency band F2.

  When there are three or more wiring layers and the frequency differs depending on the type of signal as in this embodiment, the following configuration is preferable in consideration of the results shown in FIG. That is, the data signal wiring 22DQ transmitted at high frequency is preferably provided in the wiring layers M2 and M3, which are relatively far from the main surface 21t of the silicon substrate 21. On the other hand, it is preferable to provide a control signal wiring 22CMD having a low signal loss level in the wiring layer M1 that is relatively close to the main surface 21t of the silicon substrate 21.

  Note that the distance between the wiring layer M1 and the main surface 21t of the silicon substrate 21 is smaller than the thickness of the wiring 22 of the wiring layer M1, and is, for example, about 0.5 μm to 0.6 μm. In other words, the thickness of the insulating layer 23 between the wiring layer M1 and the main surface 21t of the silicon substrate 21 is thinner than the thickness of the wiring 22 of the wiring layer M1, for example, about 0.5 μm to 0.6 μm. . Therefore, from the viewpoint of reducing signal loss, it is particularly preferable that the data signal wiring 22DQ is not formed in the wiring layer M1, as shown in FIG. However, for example, a case where the data signal wiring 22DQ is formed in the wiring layer M1 in order to increase the number of signal lines may be considered. In this case, it is preferable to increase the separation distance between the wiring layer M1 and the main surface 21t of the silicon substrate 21.

  Specifically, in the plurality of signal wirings (conductor patterns) arranged in the wiring layer M1, the ratio of the control signal wiring 22CMD in which the signal (control signal) is transmitted in the first frequency band (for example, the frequency band F1). Is larger than the ratio of the data signal wiring 22DQ in which a signal (data signal) is transmitted in a second frequency band (for example, frequency band F2) higher than the first frequency band. In the plurality of signal wirings arranged in the wiring layer M2, the ratio of the control signal wiring 22CMD that transmits a signal (control signal) in the first frequency band (for example, the frequency band F1) is the second It is less than the ratio of the data signal wiring 22DQ through which a signal (data signal) is transmitted in a frequency band (for example, frequency band F2).

  As described above, the expression “the ratio of A is larger than the ratio of B” includes the case where the ratio of B is 0%. The expression “the ratio of A is smaller than the ratio of B” includes the case where the ratio of A is 0%. For example, in the example shown in FIG. 10, the data signal wiring 22DQ is not formed in the wiring layer M1, and the control signal wiring 22CMD among the wirings 22 formed in the wiring layer M1 in the region 22A (see FIG. 9). The ratio is 100%. In the example shown in FIG. 10, the data signal wiring 22DQ is not formed in the wiring layers M2 and M3.

  Further, according to the present embodiment, it is possible to shorten the return current path (return path) of the data signal transmitted through the data line DQ shown in FIG.

  For example, as shown in FIG. 6, when signals are transmitted between the plurality of semiconductor chips 30 via the interposer 20A, it is preferable to shorten the return current path formed in the interposer 20A. In other words, the return current path for connecting the semiconductor chips 30 is preferably provided at a position close to the semiconductor chip 30. The reference potential line VS2 for reference shown in FIG. 4 is supplied with, for example, a ground potential, which is also a return current path for a data signal transmitted through the data line DQ.

  When the reference potential wiring 22VS shown in FIG. 10 forms part of the reference reference potential line VS2, the reference potential wiring 22VS is provided at a position close to the semiconductor chip 30 shown in FIG. Can be shortened.

  Here, in the interposer 20A of the present embodiment shown in FIG. 10, the reference potential wiring 22VS is mainly formed in the wiring layer M3 close to the surface electrode 25. Therefore, the transmission distance of the reference signal can be shortened compared to the interposer 20H shown in FIG.

  In the example shown in FIG. 10, the wiring layer M2 closer to the surface electrode 25 than the wiring layer M1 is mainly formed with the data signal wiring 22DQ transmitted mainly in the high frequency band F2 (see FIG. 7). ing. For this reason, even when the reference potential wiring 22VS is mainly formed in the wiring layer M3, an increase in the transmission distance of the high-frequency signal can be suppressed.

  Further, from the viewpoint of improving the electrical characteristics of the transmission path connected to the logic chip 30B shown in FIG. 6, the following configuration is preferable. FIG. 12 is an enlarged plan view of a portion B shown in FIG. In FIG. 12, the outline of the electrode 33A of the memory chip 30A, the electrode 33B of the logic chip 30B, and the surface electrode 25 of the interposer 20A is indicated by dotted lines in order to show the planar shape of the connection portion between the semiconductor chip 30 and the interposer 20A. . In the example shown in FIG. 12, the contour of the electrode 33A and the contour of the surface electrode 25 connected to the electrode 33A, and the contour of the electrode 33B and the contour of the surface electrode 25 connected to the electrode 33B are substantially overlapped. ing. Further, as described above, the passivation film 26 that covers the surface of the interposer 20A is provided with a plurality of openings, and a part of the surface electrode 25 is exposed from the passivation film 26 in the openings. In FIG. 12, the outline of the opening that exposes a part of the surface electrode 25 of the interposer 20A is indicated by a solid circle.

  As shown in FIG. 4, the logic chip 30B includes an external interface circuit IF1 that inputs / outputs signals to / from the external device 40 in addition to the internal interface circuit IF2 that inputs / outputs signals to / from the memory chip 30A. Have. For this reason, the number of signal lines (signal line SIG, data line DQ, and control signal line CMD) connected to the logic chip 30B is the same as the number of signal lines (data line DQ and control signal line CMD) connected to the memory chip 30A. More than the number. Further, the transmission speed of the signal line SIG shown in FIG. 4 is faster than the transmission speed of the data line DQ. For this reason, the signal line SIG connected to the logic chip 30B or the power supply lines VD1 and VS1 that supply the drive voltage for the logic chip 30B needs to have a strengthened transmission path.

  Therefore, in the example of the present embodiment, as shown in FIGS. 5 and 6, in the case of the plurality of electrodes 33 included in the logic chip 30 </ b> B, a plurality of (two in FIG. 6) through-electrodes with respect to one electrode 33. 24 is connected. On the other hand, as shown in FIG. 6, in the case of the plurality of electrodes 33 included in the memory chip 30 </ b> A, one through electrode 24 is connected to one electrode 33. That is, the number of through electrodes 24 connected to each of the plurality of electrodes 33 of the logic chip 30B is larger than the number of through electrodes 24 connected to each of the plurality of electrodes 33 of the memory chip 30A. Accordingly, when a plurality of through electrodes 24 (see FIG. 6) are connected in parallel as the transmission path of the signal line SIG shown in FIG. 4, the electrical resistance of the transmission path of the electrical signal can be reduced, so that the input / output voltage of the signal Can be suppressed. Further, when a plurality of through electrodes 24 (see FIG. 6) are connected in parallel as transmission paths such as the power supply line VD1 and the reference potential line VS1 shown in FIG. 4 for supplying a driving voltage to the logic chip 30B, the power supply potential and the reference Since the electric resistance of the potential transmission path can be reduced, the voltage drop of the drive voltage can be suppressed. As shown in FIG. 6, among the plurality of electrodes 33, a path for signal transmission between the semiconductor chips such as the data line DQ is not connected to the through electrode 24.

  Further, the signal line SIG connected to the logic chip 30B shown in FIG. 4 or the power supply lines VD1 and VS1 for supplying a driving voltage for the logic chip 30B preferably have the following configuration from the viewpoint of strengthening the transmission path. As shown in FIG. 12, the area of the surface electrode 25B of the electrode 33B of the logic chip 30B is preferably larger than the area of the surface electrode 25A of the electrode 33A of the memory chip 30A. By increasing the plane area of the surface electrode 25B, a plurality of transmission paths of the interposer 20A can be connected to one electrode 33B.

  Specifically, the diameter D1 of the electrode (surface electrode, pad) 33B of the logic chip 30B is larger than the diameter D2 of the electrode (surface electrode, pad) 33A of the memory chip 30A. FIG. 12 shows a case where the planar shape of the electrode 33A and the electrode 33B is a quadrangle, and the diagonal of the quadrangle is the value of the diameter D2 or the diameter D1. However, the planar shape of the electrode 33A and the electrode 33B may be a shape other than a quadrangle. For example, when the planar shape of the electrode 33A and the electrode 33B is circular, the diameter of the circle is a value of the diameter D2 or the diameter D1.

  Further, among the plurality of electrodes 33B, the separation distance P1 between the adjacent electrodes 33B is larger than the separation distance P2 between the adjacent electrodes 33A among the plurality of electrodes 33A. When there are a large number of electrodes 33B and a large number of electrodes 33A and the separation distance P1 and the separation distance P2 take a plurality of values, the separation distance P1 and the separation distance P2 described above are the smallest of the separation distances. Evaluate by value.

  As shown in FIG. 12, when the diameter D1 of the electrode 33B of the logic chip 30B is large, the diameter of the surface electrode 25 of the interposer 20A connected to the electrode 33 of the logic chip 30B may be increased as shown in FIG. it can. Thereby, as shown in FIG. 6, a plurality (two in FIG. 6) of through electrodes 24 can be connected to one electrode 33 of the logic chip 30B.

<Modification 1>
Next, a modification of the present embodiment will be described. First, as a first modification, an embodiment in which a reference potential wiring 22VS constituting a part of a reference potential transmission path is formed in the uppermost wiring layer (electrode pad layer) M4 in which a plurality of surface electrodes 25 are formed. Will be described. FIG. 13 is an enlarged cross-sectional view of a semiconductor device which is a modification to FIG. FIG. 14 is a modified example of FIG. 12, and is an enlarged plan view of the semiconductor device shown in FIG. FIG. 15 is a modification of FIG. 10 and is a cross-sectional view of the main part showing an example of the arrangement ratio for each type of transmission target in each wiring layer of the interposer shown in FIGS. FIG. 16 is a cross-sectional view of a main part showing another modification example of FIG. FIG. 17 is an enlarged plan view showing a structure example of the wiring layer below the layer on which the plurality of surface electrodes of the interposer shown in FIG. 6 are formed.

  In FIG. 14, in order to show the planar shape of the connecting portion between the semiconductor chip 30 and the interposer 20B, the surface electrode 25A of the interposer 20B connected to the memory chip 30A, the surface electrode 25B of the interposer 20B connected to the logic chip 30B, and The outline of the reference potential wiring 22VS is indicated by a dotted line. The passivation film 26 (see FIG. 13) covering the surface of the interposer 20B is provided with a plurality of openings, and a part of the surface electrode 25 is exposed from the passivation film 26 in the openings. In FIG. 14, the outline of the opening that exposes a part of the surface electrode 25 of the interposer 20B is indicated by a solid circle, and the type of transmission path that each exposed portion constitutes is indicated with an underline. 14 and 17, a pattern (dot pattern) is provided on the reference potential wiring 22VS so that the boundary between the conductor pattern constituting the reference potential wiring 22VS and the conductor pattern constituting another transmission path can be easily seen. It is attached.

  A semiconductor device PKG2 shown in FIG. 13 is different from the semiconductor device PKG1 shown in FIG. 6 in the wiring layout of the interposer 20B. Specifically, in the interposer 20B included in the semiconductor device PKG2, the reference potential wiring 22VS that constitutes a part of the reference potential transmission path is formed in the uppermost wiring layer M4 on which the plurality of surface electrodes 25 are formed. This is different from the interposer 20A shown in FIG.

  In other words, the interposer 20B differs from the interposer 20A in that many of the reference potential wirings 22VS are formed in the same layer as the plurality of surface electrodes 25.

  In a region 22A (see FIG. 14) sandwiched between adjacent semiconductor chips 30, a reference potential wiring 22VS constituting a part of a reference potential transmission path in the wiring 22 arranged in the wiring layer M4 of the interposer 20B. This ratio is larger than the ratio of the signal wiring constituting a part of the signal transmission path. In the example shown in FIG. 14, no conductor pattern other than the reference potential wiring 22VS is formed in the region 22A.

  In the present modification, the reference potential line VS2 (in the region where the surface electrode 25 is not disposed in the uppermost layer, that is, the wiring layer M4 which is the wiring layer formed farthest from the main surface 21t of the silicon substrate 21. A reference potential wiring 22VS that constitutes FIG. 14) is provided.

  Further, as shown in FIG. 14, the surface electrode 25 and the reference potential wiring 22VS constituting the reference potential line VS2 of the interposer 20B are integrally formed. In other words, the surface electrode 25 and the reference potential wiring 22VS constituting the reference potential line VS2 are connected to each other. Therefore, in the region 22A of the uppermost wiring layer M4 of the interposer 20B, the reference potential wiring 22VS is formed so as to cover most of the wiring layer M3 (see FIG. 13), and a part of the reference potential wiring 22VS is formed. It functions as a surface electrode 25 for transmitting a reference potential. Further, in the peripheral region of the region 22A, a surface electrode 25 constituting a transmission path other than the reference potential line VS2, for example, the signal line SG shown in FIG. 4 or the transmission path for the power supply lines VD1 and VD2 is arranged. An opening is formed in the reference potential wiring 22VS2 at a position, and a surface electrode 25 is formed in the opening.

  In the case of the interposer 20B, by providing the reference potential wiring 22VS in the uppermost layer, the electromagnetic field can be distributed upward as in the case of the interposer 20A described with reference to FIG. For this reason, it can suppress that electric current CF (refer FIG. 8) flows into the silicon substrate 21. FIG.

  In the case of the interposer 20B, the wiring layer M4 is used as a transmission path for the reference potential. Therefore, as shown in FIG. Can be increased. For example, in the example shown in FIG. 15, in the region 22A (see FIG. 14), the reference potential wiring 22VS is not formed in each of the wiring layer M2 and the wiring layer M3, and only the data signal wiring 22DQ is arranged. . For this reason, the interposer 20B shown in FIG. 15 can increase the number of data signal wirings 22DQ as compared to the interposer 20A shown in FIG.

  However, as a modification of the example shown in FIG. 15, the reference potential wiring 22VS may be arranged in the wiring layer M2 or the wiring layer M3. Even in this case, the number of data signal lines 22DQ provided in each of the wiring layer M2 and the wiring layer M3 can be increased as compared with the interposer 20A shown in FIG. Further, since the control signal wiring 22CMD is mainly provided in the wiring layer M1, the number of the control signal wirings 22CMD can be sufficiently secured. Further, as a modification of the example shown in FIG. 15, the control signal wiring 22CMD may be arranged in the wiring layer M2 or the wiring layer M3.

  When the wiring layer M4 is used as a supply space for the reference potential wiring 22VS as in the interposer 20C included in the semiconductor device PKG3 shown in FIG. 16, a plurality of data signal wirings provided in the wiring layer M2 and the wiring layer M3. The separation distance of 22DQ can be increased.

  In the interposer 20C, the reference potential wiring 22VS is formed in the wiring layer M4, and the wiring for the high-speed signal transmission path has a large distance from other wiring. Specifically, the data signal wiring 22DQ provided in the wiring layer M2 is provided so as not to overlap the control signal wiring 22CMD formed in the wiring layer M1 in the thickness direction. The data signal wiring 22DQ provided in the wiring layer M2 is arranged so as not to overlap with the control signal wiring 22CMD formed in the wiring layer M1 in the thickness direction. Thereby, crosstalk between the transmission path of the data signal and the transmission path of other signals can be reduced. That is, the interposer 20 </ b> C illustrated in FIG. 16 is a configuration example when importance is attached to suppression of crosstalk of a wiring that performs high-speed signal transmission.

  Since the wiring layer M2 is provided between the data signal wiring 22DQ formed in the wiring layer M3 and the control signal wiring 22CMD formed in the wiring layer M1, it is formed in the wiring layer M3. The data signal wiring 22DQ and the control signal wiring 22CMD formed in the wiring layer M1 may overlap. Since the wiring layer M4 is the uppermost wiring layer forming the surface electrode 25 (see FIG. 6), the separation distance B34 between the wiring layer M3 and the wiring layer M4 is the separation distance B12 between the wiring layer M1 and the wiring layer M2. The distance B23 between the wiring layer M2 and the wiring layer M3 is larger. Therefore, the data signal wiring 22DQ formed in the wiring layer M3 and the reference potential wiring 22VS formed in the wiring layer M4 may overlap in the thickness direction.

  Further, as shown in FIGS. 15 and 16, since the wiring layer M4 is the uppermost wiring layer, the reference potential wiring 22VS formed in the wiring layer M4 does not need to be planarized. For this reason, as shown in FIG. 14, it is not necessary to provide an opening other than the opening provided with the surface electrode 25 for a transmission path other than the reference potential, and a sheet-like conductor pattern that spreads uniformly is formed. Can be formed.

  Even when the reference potential wiring 22VS is not formed in the wiring layer M4, for example, the reference potential wiring 22VS having a large area may be formed in the wiring layer M3 like the interposer 20D of the semiconductor device PKG4 shown in FIG. it can. The reference potential wiring of the interposer 20 </ b> D shown in FIG. 23 has a larger area than the other wirings 22. However, the conductor pattern formed on the wiring layer M3 which is not the uppermost layer needs to form a plurality of surface electrodes 25 (see FIG. 10) on the wiring layer M4 which is the uppermost layer (see FIG. 10). Difficult to form. For example, as shown in FIG. 17, the reference potential wiring 22VS of the interposer 20D is a mesh-shaped conductor pattern (mesh pattern) in which a large number of linearly extending conductor patterns intersect each other.

  However, considering the electrical characteristics of the circuit, it is preferable to use a sheet shape rather than a mesh pattern. For example, as shown in FIG. 14, the reference potential wiring 22VS formed in a sheet shape has a lower electrical resistance than the reference potential wiring 22VS formed in a mesh shape as shown in FIG. Therefore, when the reference potential wiring 22VS is used as the reference reference potential line VS2 (see FIG. 4), the sheet-like reference potential wiring 22VS can reduce variations in signal line characteristics.

  Further, when the reference potential wiring 22VS is used as the reference potential line VS1 (see FIG. 4) for supplying a reference potential for driving voltage, the voltage drop is reduced by reducing the electric resistance of the reference potential wiring 22VS. Can be suppressed.

  Further, when considering that the reference potential wiring 22VS functions as an electromagnetic field shield layer, the sheet-like reference potential wiring 22VS is more likely to shield the electromagnetic field than the mesh-shaped reference potential wiring 22VS. Therefore, signal loss can be reduced.

<Modification 2>
Next, as a second modification, an embodiment in which the separation distance between the wiring layers is set to a different value for each layer will be described. FIG. 18 is a modification of FIG. 10 and is a cross-sectional view of the main part showing an example of the distance between each wiring layer of the interposer and the arrangement ratio according to the type of transmission target. FIG. 19 is a cross-sectional view of a principal part showing another modified example with respect to FIG. 18 and 19 illustrate the silicon substrate 21, the wiring 22 constituting each wiring layer, and the surface electrode 25, and the insulating layer 23 covering each wiring layer, as in the enlarged sectional view shown in FIG. Illustration of (see FIG. 6) is omitted.

  A semiconductor device PKG5 shown in FIG. 18 is different from the semiconductor device PKG1 shown in FIG. 10 in the distance between the wiring layers of the interposer 20E. Specifically, the interposer 20E included in the semiconductor device PKG5 is different from the interposer 20A shown in FIG. 10 in that the separation distance B23 between the wiring layer M3 and the wiring layer M2 is larger than the separation distance B12 between the wiring layer M2 and the wiring layer M1. To do. In the example shown in FIG. 18, the separation distance B34 between the wiring layer M4 and the wiring layer M3 is larger than the separation distance B23 between the wiring layer M3 and the wiring layer M2. In other words, the distance between the wiring layers of the interposer 20D increases as the distance from the silicon substrate 21 increases.

  A method of laminating a wiring layer on the silicon substrate 21 is performed by the following method, for example. First, the insulating layer 23 (see FIG. 6) is deposited on the main surface 21t of the silicon substrate 21 (insulating layer deposition step). Next, an opening is formed in the insulating layer 23, and a conductor is embedded in the opening (conductor embedding step). Next, the upper surface side of the insulating layer in which the conductor is embedded (surface away from the main surface 21t of the silicon substrate 21) is polished and planarized by, for example, CMP (polishing step). As a result, a first wiring layer M1 is formed. Next, an insulating layer is deposited on the first wiring layer M1 (insulating layer deposition step). Thereafter, the conductor embedding step, the polishing step, and the insulating layer deposition step are similarly repeated to laminate a plurality of wiring layers.

  When the wiring layers are stacked by the above method, in order to improve the flatness of the upper surface of the wiring layer, it is preferable to reduce the distance between the wiring layers and the thickness of the wiring layer itself. When a plurality of wiring layers are stacked, the lower wiring layer is required to have higher flatness than the upper wiring layer. Therefore, it is preferable to reduce the distance between the wiring layers at a position relatively close to the silicon substrate 21. On the other hand, at a position relatively close to the uppermost wiring layer M4, the separation distance B23 and the separation distance B12 can be set to the same value as in the example shown in FIG. 10, but the modification example shown in FIG. Thus, the separation distance B23 may be larger than the separation distance B12.

  And the following effects are acquired by making the separation distance B23 larger than the separation distance B12.

  Each of the above-described interposers 20A, 20B, 20C, and 20D uses the same process as the process of forming the wiring on the semiconductor wafer, so that the wiring density of the plurality of wirings 22 is, for example, the wiring of the wiring board 10 shown in FIG. The wiring density of 13 can be improved. For example, the thickness of the wiring 22 is about 1 μm to 1.2 μm, and the distance between the stacked wiring layers M 1, M 2, M 3 is about half the thickness of the wiring 22.

  However, when the thickness of each of the plurality of wirings 22 is reduced, the wiring resistance increases. For this reason, the subject that it becomes difficult to make the impedance value of each signal transmission path close to a predetermined value arises.

  For example, when the design value of the characteristic impedance of the data line DQ shown in FIG. 4 is 50Ω [Ohm], in the wiring path using the data signal wiring 22DQ shown in FIGS. 10 and 18, and for the reference reference potential In the wiring path using the wiring 22VS, it is preferable that each approaches 50Ω.

If the time constant consisting of the parasitic capacitance and wiring resistance of the input / output circuit to which the data line DQ is connected is τ,
τ = (signal wiring resistance + reference potential line resistance) × (parasitic capacitance of output circuit + parasitic capacitance of input circuit)
Is defined as

  Here, when the wiring resistances of the data signal wiring 22DQ and the reference potential wiring 22VS are large, the value of τ increases, which causes the signal waveform to become dull.

  On the other hand, the capacitance component of the characteristic impedance defined by √ (inductance / capacitance) is inversely proportional to the separation distance between the wiring layers. Therefore, when the separation distance is small, the capacitance component of the characteristic impedance is a large value. For this reason, if the wiring width is increased in order to reduce the above-described wiring resistance, the capacitance component of the characteristic impedance is further increased and the characteristic impedance becomes too smaller than 50Ω. For this reason, the signal waveform becomes dull.

  Thus, when the wiring layer is thin and the distance between the wiring layers is small, the margin for adjusting the resistance component and the capacitance component of the characteristic impedance is small. The resistance component and the capacitance component of this characteristic impedance are in a trade-off relationship. If the margin for adjusting the resistance component and the capacitance component is reduced, it becomes difficult to adjust the characteristic impedance, and the impedance of the signal transmission path is set to a predetermined value. It becomes difficult to get close to the value.

  Therefore, as shown in FIG. 18, when the separation distance B23 is larger than the separation distance B12, the trade-off relationship described above is improved. That is, by increasing the separation distance B23 between the wiring layer M2 mainly provided with the data signal wiring 22DQ and the wiring layer M3 mainly provided with the reference potential wiring 22VS, the wiring width can be increased. The capacitance component of the characteristic impedance is difficult to decrease. As a result, the characteristic impedance in the wiring path using the data signal wiring 22DQ and in the wiring path using the reference potential wiring 22VS is easily brought close to, for example, 50Ω.

  In the example shown in FIG. 18, the separation distance B34 between the wiring layer M4 and the wiring layer M3 is larger than the separation distance B23 between the wiring layer M3 and the wiring layer M2. Since the wiring layer M4 is the uppermost wiring layer, the flatness of the uppermost surface electrode 25 may be lower than that of the wiring 22 of the other layers. For this reason, the separation distance B34 can be particularly increased. As shown in FIG. 18, when the wiring 22 is not formed in the wiring layer M4 in the region 22A (see FIG. 9), the magnitude of the separation distance B34 shown in FIG. The impact is small. However, when the reference potential wiring 22VS is formed in the wiring layer M4 like the interposer 20F included in the semiconductor device PKG6 of the modification shown in FIG. 19, the following effects are obtained.

  An interposer 20F shown in FIG. 19 has a reference that forms a reference potential line VS in a wiring layer M4 that is a wiring layer that is formed farthest from the main surface 21t of the silicon substrate 21 in the region 22A (see FIG. 9). A potential wiring 22VS is provided. The wiring layer M3 is mainly formed with a data signal wiring 22DQ through which a data signal is transmitted at a high speed (for example, the frequency band F2 shown in FIG. 7). That is, in the interposer 20E, the uppermost wiring layer M4 is mainly provided with the reference potential wiring 22VS, and the wiring layer M3 is provided with the data signal wiring 22DQ mainly transmitted at high speed.

  The above wiring structure can also be expressed as follows. That is, in the region 22A (see FIG. 9), in the wiring 22 arranged in the wiring layer M4 of the interposer 20F, the ratio of the reference potential wiring 22VS constituting a part of the reference potential transmission path is the ratio of the signal transmission path. More than the proportion of signal wiring that constitutes a part. In the plurality of signal wirings arranged in the wiring layer M3, the ratio of the control signal wiring 22CMD that transmits a signal (control signal) in the first frequency band (for example, the frequency band F1) is the second It is less than the ratio of the data signal wiring 22DQ through which a signal (data signal) is transmitted in a frequency band (for example, frequency band F2).

  The expression “the ratio of A is larger than the ratio of B” includes the case where the ratio of B is 0%. The expression “the ratio of A is smaller than the ratio of B” includes the case where the ratio of A is 0%. For example, in the example shown in FIG. 19, like the interposer 20B shown in FIG. 14, only the reference potential wiring 22VS is formed in a sheet shape in the wiring layer M4 (see FIG. 19) in the region 22A (see FIG. 14). Other wirings 22 are not formed. In the example shown in FIG. 19, the control signal wiring 22CMD and the reference potential wiring 22VS are not formed in the wiring layer M3 in the region 22A (see FIG. 9).

  When the wiring layer M4 is provided with the reference potential wiring 22VS and the wiring layer M3 is provided with the data signal wiring 22DQ for transmitting signals at a high frequency like the interposer 20F, the reference potential wiring 22VS and the data signal wiring are provided. The characteristic impedance of the signal transmission path changes depending on the separation distance of 22DQ. The distance between the data signal wiring 22DQ and the reference potential wiring 22VS is defined by the separation distance B34 between the wiring layer M4 and the wiring layer M3.

  Accordingly, as shown in FIG. 19, since the separation distance B34 is further larger than the separation distance B23, the characteristic impedance value of the data signal wiring 22DQ can be easily brought close to a predetermined value (for example, 50Ω).

  Further, the uppermost wiring layer M4 can be thicker than the other wiring layers M1, M2, and M3. For this reason, the interposer 20F is preferable from the viewpoint of reducing the wiring resistance of the reference potential wiring 22VS.

  Further, the structure of the interposer 20C described with reference to FIG. 16 in <Modification 1> described above is preferable in that the characteristic impedance of the signal transmission path at high frequencies can be easily approximated to a predetermined value. That is, in the example illustrated in FIG. 16, in the region 22A (see FIG. 9), each of the plurality of data signal wirings 22DQ provided in the wiring layer M2 includes the plurality of wirings 22 provided in the wiring layer M1, and the wirings. It does not overlap with the plurality of wirings 22 provided in the layer M3 in the thickness direction. In this case, since the distance between the data signal wiring 22DQ and the other wiring 22 can be increased, the characteristic impedance of the signal transmission path can be easily brought close to a predetermined value.

  On the other hand, in the case of the interposer 20F included in the semiconductor device PKG6 shown in FIG. 19, the separation distance B23 between the wiring layer M2 and the wiring layer M3 is larger than the separation distance B12. For this reason, the influence on the characteristic impedance due to the data signal wiring 22DQ of the wiring layer M2 and the data signal wiring 22DQ of the wiring layer M3 overlapping in the thickness direction can be reduced. In the case of the interposer 20F, the data signal wiring 22DQ of the wiring layer M2 and the data signal wiring 22DQ of the wiring layer M3 overlap in the thickness direction, so that the data signal is compared with the interposer 20C shown in FIG. The number of wiring lines 22DQ can be increased.

<Method for Manufacturing Semiconductor Device>
Next, manufacturing processes of the semiconductor devices PKG1, PKG2, PKG3, PKG4, and PKG5 described with reference to FIGS. However, the semiconductor devices PKG1, PKG2, PKG3, PKG4, and PKG5 described above are manufactured by the same manufacturing method except that the steps for stacking the wiring layer on the interposer are different. Therefore, in the following description, a method for manufacturing the semiconductor device PKG1 will be described as a representative example. Moreover, in the following description, it demonstrates, referring the flowchart which shows the flow of a manufacturing process, and FIGS. 1-19 as needed. FIG. 20 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device described with reference to FIGS.

<Interposer preparation>
First, in the interposer preparation step, the interposer 20A shown in FIG. 10, the interposer 20B shown in FIG. 15, the interposer 20C shown in FIG. 16, the interposer 20D shown in FIG. 18, or the interposer 20E shown in FIG. A method for manufacturing the interposers 20A, 20B, 20C, 20D, and 20E (hereinafter, typically described as the interposer 20A in the description of the manufacturing process) is to prepare a silicon substrate 21 that is a semiconductor wafer, A plurality of wiring layers are stacked. For example, as described above, the wiring layer is laminated by repeating the insulating layer deposition step, the conductor embedding step, and the polishing step.

  In this step, a plurality of interposers 20A are collectively formed on a single semiconductor wafer. And after laminating | stacking a wiring layer and performing an electrical test, a semiconductor wafer is cut | disconnected along a dicing line and several interposer 20A is acquired.

<Die bond>
Next, in the die bonding step, a plurality of semiconductor chips 30 are mounted on the interposer 20A as shown in FIG. In this step, the plurality of semiconductor chips 30 are sequentially mounted so that the surfaces 30t of the plurality of semiconductor chips 30 and the upper surface 20t of the interposer 20A face each other. Although the mounting order is not particularly limited, when there is a difference in the thickness of the plurality of semiconductor chips 30, it is preferable to mount the semiconductor chip 30 having a relatively small thickness first.

  For example, in the present embodiment, there is one memory chip 30A, but a stacked body in which a plurality of memory chips 30A are stacked may be used as the memory chip 30A. In this case, the stacked body of the memory chips 30A is likely to be thicker than the logic chip 30B. Therefore, it is preferable to mount the logic chip 30B first.

  In this step, as shown in FIG. 6, the plurality of electrodes 33 of the semiconductor chip 30 and the plurality of surface electrodes 25 of the interposer 20 </ b> A are electrically connected through the plurality of bump electrodes 35.

  3, 5, and 6, the plurality of bump electrodes 35 are exposed, but an underfill resin (illustrated) is provided between the semiconductor chip 30 and the interposer 20 </ b> A so as to cover the periphery of the plurality of bump electrodes 35. May be omitted). The underfill resin is an insulating resin, and can cover the bump electrodes 35 by covering the periphery of the plurality of bump electrodes 35.

<With interposer>
Next, in the interposer mounting step, as shown in FIG. 3, the wiring substrate 10 that is a package substrate is prepared, and the interposer 20 </ b> A on which a plurality of semiconductor chips 30 are mounted is mounted on the wiring substrate 10. In this step, mounting is performed so that the lower surface 20b of the interposer 20A and the upper surface 10t of the wiring board 10 face each other.

  In this step, as shown in FIG. 6, the plurality of backside electrodes of the interposer 20 </ b> A and the plurality of bonding pads 16 of the wiring substrate 10 are electrically connected via the bump electrodes 28.

  3, 5, and 6, the plurality of bump electrodes 28 are exposed, but an underfill resin (illustrated) is provided between the interposer 20 </ b> A and the wiring board 10 so as to cover the periphery of the plurality of bump electrodes 28. May be omitted). The underfill resin is an insulating resin, and can cover the bump electrodes 28 by covering the periphery of the bump electrodes 28.

<Ball mount>
Next, in the ball mounting process, as shown in FIG. 3, a plurality of solder balls 11 serving as external terminals are joined to a plurality of lands 12 formed on the lower surface 10 b of the wiring substrate 10.

  In this step, after the lower surface 10b of the wiring board 10 faces upward, the solder balls 11 are disposed on each of the plurality of lands 12 exposed on the lower surface 10b of the wiring board 10. Then, the plurality of solder balls 11 and the lands 12 are joined by heating the plurality of solder balls 11. Through this step, the plurality of solder balls 11 are electrically connected to the plurality of semiconductor chips 30 (logic chip 30B and memory chip 30A) via the wiring substrate 10. However, the technique described in the present embodiment is not limited to a so-called BGA (Ball Grid Array) type semiconductor device in which solder balls 11 are joined in an array. For example, as a modification to this embodiment, the solder ball 11 is not formed and the land 12 is exposed, or the land 12 is shipped with a solder paste thinner than the solder ball 11 so-called LGA. It can be applied to a (Land Grid Array) type semiconductor device. In the case of an LGA type semiconductor device, the ball mounting process can be omitted.

(Embodiment 2)
In the above embodiment, the embodiment using the silicon interposer in which a plurality of wiring layers are formed on the silicon substrate 21 as the interposer has been described. In the case of a silicon interposer, as described in the first embodiment, since a process similar to the process of forming wiring on a semiconductor wafer can be used, there is an advantage that the wiring density can be easily improved.

  However, in recent years, the technology for thinning a multilayer resin substrate in which a plurality of wiring layers are laminated via an organic insulating layer has advanced, and even with a multilayer resin substrate, the wiring width and wiring layer thickness approaching the silicon interposer, Alternatively, the thickness of the interlayer insulating film has been realized. Therefore, in this embodiment, an embodiment in which the technique described in Embodiment 1 is applied to a multilayer resin substrate will be described.

  FIG. 21 is an enlarged cross-sectional view of a semiconductor device which is a modification to FIG. FIG. 22 is a modification of FIG. 10 and is a cross-sectional view of the main part showing an example of the arrangement ratio for each type of transmission target in each wiring layer of the interposer shown in FIG.

  A semiconductor device PKG7 shown in FIG. 21 is different from the semiconductor device PKG1 shown in FIG. 6 in the structure of the interposer 20G. Specifically, the interposer 20G is different from the interposer 20A shown in FIG. 6 in that the insulating layer covering each of the plurality of wiring layers is the organic insulating layer 29.

  Further, the interposer 20G does not have the silicon substrate 21 shown in FIG. 6, and the lower surface 20b of the interposer 20G is covered with an insulating film 17 that is an organic insulating film called a solder resist film. However, a plurality of openings are formed in the insulating film 17, and a part of the back electrode 27 is exposed in the openings. Similarly, the upper surface 20t of the interposer 20G is covered with the insulating film 17, and some of the plurality of surface electrodes 25 are exposed in the plurality of openings formed in the insulating film 17.

  Further, for example, in the interposer 20G, the lowermost wiring layer M0, the wiring layer M1, the wiring layer M2, the wiring layer M3, and the uppermost wiring layer M4 are laminated in order from the upper surface 10t side of the wiring substrate 10. A plurality of backside electrodes 27 are formed on the lowermost wiring layer M0, and a plurality of front surface electrodes 25 are formed on the uppermost wiring layer M4.

  Except for the above differences, the interposer 20G is the same as the interposer 20A shown in FIG. 6 described in the first embodiment.

  Since the interposer 20G of the present embodiment does not have the silicon substrate 21 shown in FIG. 6, a part of the signal current energy described in the first embodiment is converted into thermal energy by the silicon substrate 21. The problem of consumption and signal loss does not occur.

  However, when signals are transmitted between the plurality of semiconductor chips 30 via the interposer 20G, it is preferable to shorten the return current path formed in the interposer 20G. In other words, the return current path for connecting the semiconductor chips 30 is preferably provided at a position close to the semiconductor chip 30. As described in the first embodiment, the reference potential line VS2 for reference shown in FIG. 4 is supplied with, for example, a ground potential. This is also the return current path of the data signal transmitted through the data line DQ at the same time. But there is.

  When the reference potential wiring 22VS shown in FIG. 22 constitutes a part of the reference potential line VS2 which is a return current path, the reference potential wiring 22VS is provided at a position close to the semiconductor chip 30 shown in FIG. The path length of the return current can be shortened.

  Here, the interposer 20G includes the following wiring structure in a region 22A sandwiched between adjacent semiconductor chips 30. That is, as shown in FIG. 22, in the region 22A (see FIG. 21), the reference potential wiring 22VS constituting the return current path is mainly in the wiring layer M3 close to the wiring layer M4 where the surface electrode 25 is formed. Is formed.

  Specifically, in the region 22A (see FIG. 21), the ratio (occupancy) of the reference potential wiring 22VS constituting a part of the reference potential transmission path among the plurality of wirings 22 is the reference potential wiring in the wiring layer M3. The ratio of 22VS is larger than the ratio (occupancy) of the reference potential wiring 22VS in the wiring layer M1. In the region 22A (see FIG. 9), the ratio (occupancy) of the signal wiring (data signal wiring 22DQ and control signal wiring 22CMD) that constitutes a part of the signal transmission path among the plurality of wirings 22. The ratio of the signal wiring in the wiring layer M1 is larger than the ratio (occupancy) of the signal wiring in the wiring layer M3.

  Further, the example shown in FIG. 22 has the following wiring structure. That is, in the interposer 20G, in the plurality of wirings (conductor patterns) 22 arranged in the wiring layer M1, the ratio of the reference potential wiring (reference potential conductor) 22VS constituting a part of the transmission path of the reference potential is the signal This is less than the ratio of signal wiring (signal conductor) constituting a part of the transmission path. In the plurality of wirings 22 arranged in the wiring layer M3, the ratio of the reference potential wiring 22VS that forms part of the reference potential transmission path is the ratio of the signal wiring that forms part of the signal transmission path. More than

  Since the interposer 20G according to the present embodiment is provided with the return current path in the wiring layer M3 close to the wiring layer M4 in which the surface electrode 25 is formed as described above, for example, the interposer 20G illustrated in FIG. In comparison, the path length of the return current can be shortened.

  In the example shown in FIG. 22, the data signal wiring 22DQ transmitted mainly in the high frequency band F2 (see FIG. 7) is mainly formed in the wiring layer M2 closer to the surface electrode 25 than the wiring layer M1. ing. In other words, in the plurality of signal wirings arranged in the wiring layer M2, the ratio of the control signal wiring 22CMD in which the signal (control signal) is transmitted in the first frequency band (for example, the frequency band F1) is the second Is less than the ratio of the data signal wiring 22DQ in which the signal (data signal) is transmitted in the frequency band (for example, the frequency band F2). In addition, in the plurality of signal wirings (conductor patterns) arranged in the wiring layer M1, the ratio of the control signal wiring 22CMD in which the signal (control signal) is transmitted in the first frequency band (for example, the frequency band F1) is More than the ratio of the data signal wiring 22DQ in which a signal (data signal) is transmitted in a second frequency band (eg, frequency band F2) higher than the first frequency band. For this reason, it becomes possible to shorten the transmission distance of a high frequency signal.

  In the present embodiment, the modification to the interposer 20A described in the first embodiment has been described mainly with respect to differences. However, each of Modification 1 and Modification 2 described in the first embodiment and the structure of the semiconductor device PKG7 of the second embodiment can be applied in combination. Hereinafter, as in the second embodiment, an embodiment in which the relay substrate having the organic insulating layer 29 (see FIG. 21) is combined with the technology described in each modification described in the above embodiment is described. An example will be described. For example, the interposer 20J included in the semiconductor device PKG8 shown in FIG. 23 is a relay board that combines the wiring structure of the interposer 20F described with reference to FIG. 19 and the wiring structure of the interposer 20G described with reference to FIG.

  The interposer 20J is different from the interposer 20G shown in FIG. 22 in that the reference potential wiring 22VS is formed in the wiring layer M4. Therefore, the interposer 20J can increase the number of data signal wirings 22DQ more than the interposer 20G.

  Further, since the interposer 20J has the reference potential wiring 22VS in the wiring layer M4 which is the uppermost layer, as described with reference to FIG. 14, the reference potential wiring 22VS of the wiring layer M4 can be formed in a sheet shape. it can. In this case, the reference potential wiring 22VS can function as an electromagnetic field shield layer.

  Further, the interposer 20J included in the semiconductor device PKG8 is different from the interposer 20G shown in FIG. 22 in that the distance B23 between the wiring layer M3 and the wiring layer M2 is larger than the distance B12 between the wiring layer M2 and the wiring layer M1. . In the example shown in FIG. 23, the separation distance B34 between the wiring layer M4 and the wiring layer M3 is larger than the separation distance B23 between the wiring layer M3 and the wiring layer M2.

  Therefore, compared to the interposer 20G shown in FIG. 22, the interposer 20J has characteristic impedances in the wiring path using the data signal wiring 22DQ and in the wiring path using the reference potential wiring 22VS for reference. It is easy to approach a predetermined value.

  In addition to the above, the relay board described in this embodiment can be combined with each technique described as a modification in the above embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, as shown in FIG. 10, as the relay substrate, the wiring layer M1, the wiring layer M2, the wiring layer M3, and the wiring layer M4 are stacked on the main surface 21t of the silicon substrate 21. The explanation was made by taking up a layered relay board. In the second embodiment, as shown in FIG. 21, the lowermost wiring layer M0, wiring layer M1, wiring layer M2, wiring layer M3, and wiring layer M4 are stacked in this order from the upper surface 10t side of the wiring substrate 10. The five-layer relay board was taken up and explained. However, the reference potential wiring 22VS is mainly provided in the wiring layer relatively close to the semiconductor chip 30 described in the first embodiment and the second embodiment, and the signal wiring is mainly used in the lower wiring layer. The technique of being provided in the relay board can be applied to a relay board having various numbers of wiring layers.

  For example, a relay substrate having two wiring layers between the wiring layer M4 on which the surface electrode 25 is formed and the silicon substrate 21 (or between the wiring layer M0 shown in FIG. 21) may be used. In this case, by providing the reference potential wiring 22VS mainly in the wiring layer M4, three wiring layers can be secured.

  Further, for example, it may be a relay substrate having four or more wiring layers between the wiring layer M4 on which the surface electrode 25 is formed and the silicon substrate 21 (or between the wiring layer M0 shown in FIG. 21). . In this case, since the space in which the data signal wiring 22DQ can be arranged further increases, the number of data lines DQ shown in FIG. 4 can be increased.

  Further, for example, the present invention can be applied to a relay substrate having one wiring layer between the wiring layer M4 on which the surface electrode 25 is formed and the silicon substrate 21 (or between the wiring layer M0 shown in FIG. 21). In this case, a reference potential wiring may be provided in the uppermost wiring layer, and a plurality of signal wirings including the data signal wiring 22DQ may be provided in the lowermost wiring layer. However, when the silicon substrate 21 is used, it is better to increase the separation distance between the main surface 21t of the silicon substrate 21 and the wiring layer closest to the main surface 21t.

  Further, for example, in the above-described embodiment and each modification, the embodiment in which only the interposer is mounted on the wiring board 10 has been described for the sake of simplicity. However, semiconductor components and electronic components other than the interposer may be mounted on the wiring board 10.

  Further, for example, in the above-described embodiment and each modification, an example in which one logic chip 30B and one memory chip 30A are mounted on the interposer has been described. However, three or more semiconductor chips 30 may be mounted on the interposer. For example, in the case of the memory chip 30A, there is a technique for increasing the storage capacity by stacking a plurality of memory chips 30A. Therefore, the memory chip 30A described in the above embodiments and the like may be a stacked body of a plurality of memory chips.

  Further, for example, since the semiconductor chips 30 mounted on the interposer adjacent to each other need only be connected via the wiring layer of the interposer, the plurality of semiconductor chips 30 are not the memory chip 30A and the logic chip 30B. May be. For example, the plurality of semiconductor chips 30 may be a sensor chip in which a sensor circuit is formed and a controller chip in which a control circuit for controlling the sensor circuit is formed.

  Further, for example, the data line DQ (see FIG. 4) described as the data signal transmission path in the above-described embodiment and each modification is a so-called single-ended signal transmission path. However, as a modification, a differential signal transmission path using two paired signal transmission paths may be used.

  Further, for example, the modifications can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.

  In addition, a part of the contents described in the embodiment will be described below.

(1)
A wiring board;
An interposer mounted on the first surface of the wiring board;
A first semiconductor component mounted on the interposer;
A second semiconductor component mounted side by side with the first semiconductor component on the interposer and controlling the first semiconductor component;
A plurality of external terminals formed on a second surface opposite to the first surface of the wiring board;
Including
The interposer has a plurality of wiring layers,
The first semiconductor component and the second semiconductor component are electrically connected to each other through the plurality of wiring layers,
The plurality of wiring layers are separated from the first wiring layer, the second wiring layer farther from the first surface of the wiring board than the first wiring layer, and the first surface from the second wiring layer. A third wiring layer,
In the plurality of wirings arranged in the first wiring layer, the ratio of the reference potential wiring constituting a part of the reference potential transmission path is higher than the ratio of the signal wiring constituting a part of the signal transmission path. Less
In the plurality of wirings arranged in the third wiring layer, the ratio of the reference potential wiring is larger than the ratio of the signal wiring.
Semiconductor device.

(2)
A wiring board;
An interposer mounted on the first surface of the wiring board;
A first semiconductor component mounted on the interposer;
A second semiconductor component mounted side by side with the first semiconductor component on the interposer and controlling the first semiconductor component;
A plurality of external terminals formed on a second surface opposite to the first surface of the wiring board;
Including
The interposer has a base material made of a semiconductor material as a base material, and a plurality of wiring layers arranged on the main surface of the base material,
The first semiconductor component and the second semiconductor component are electrically connected to each other through the plurality of wiring layers,
The plurality of wiring layers include a first wiring layer and a second wiring layer that is farther from the main surface of the base material than the first wiring layer,
In a plan view, in the first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component,
The ratio of the reference potential wiring constituting a part of the reference potential transmission path is such that the ratio of the reference potential wiring in the second wiring layer is larger than the ratio of the reference potential wiring in the first wiring layer,
The ratio of the signal wiring constituting a part of the signal transmission path is such that the ratio of the signal wiring in the first wiring layer is larger than the ratio of the signal wiring in the second wiring layer.
Semiconductor device.

(3)
A wiring board;
An interposer mounted on the first surface of the wiring board;
A first semiconductor component mounted on the interposer;
A second semiconductor component mounted side by side with the first semiconductor component on the interposer and controlling the first semiconductor component;
A plurality of external terminals formed on a second surface opposite to the first surface of the wiring board;
Including
The interposer has a base material made of a semiconductor material as a base material, and a plurality of wiring layers arranged on the main surface of the base material,
The first semiconductor component and the second semiconductor component are electrically connected to each other through the plurality of wiring layers,
The plurality of wiring layers include a first wiring layer and a second wiring layer that is farther from the main surface of the base material than the first wiring layer,
In a plan view, in the first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component,
In the plurality of wirings arranged in the first wiring layer, the ratio of the reference potential wiring constituting a part of the reference potential transmission path is higher than the ratio of the signal wiring constituting a part of the signal transmission path. Less
In the plurality of wirings arranged in the second wiring layer, the ratio of the reference potential wiring is larger than the ratio of the signal wiring.
Semiconductor device.

10 Wiring board (package board)
10b Bottom surface (surface, mounting surface)
10s side surface 10t upper surface (surface, chip mounting surface)
11 Solder balls (external terminals, electrodes, external electrodes)
12 lands (external terminals, electrodes, external electrodes, terminals, solder connection pads)
13 Wiring 14 Insulating layer 15 Via wiring 16 Bonding pad (terminal, chip mounting surface side terminal, electrode)
17 Insulating film 20A, 20B, 20C, 20D, 20E, 20F, 20G, 20H, 20J Interposer (relay substrate)
20b Bottom surface (surface, mounting surface)
20s Side surface 20t Upper surface (surface, chip mounting surface)
21 Silicon substrate (base material)
21t Main surface 22 Wiring (conductor pattern)
22A, 22B Region 22CMD Control signal wiring 22DQ Data signal wiring 22VS Reference potential wiring (reference potential conductor)
23 Insulating layer 24 Through electrode 25, 25A, 25B Surface electrode (electrode pad, terminal)
26 Passivation film 27 Back electrode (electrode, pad, terminal)
28 Bump electrode 29 Organic insulating layer 30 Semiconductor chip (semiconductor component)
30A Memory chip 30b Back surface (main surface, bottom surface)
30B Logic chip 30s Side surface 30t Surface (main surface, upper surface)
31 Silicon substrate (base material)
31t Main surface 32 Wiring layers 33, 33A, 33B Electrode (surface electrode, pad, terminal)
34 Passivation film 35 Bump electrode 40 External device 50 Power supply 60 Mounting substrate B12, B23, B34 Separation distance CF Current CMD Control signal line (signal line)
CORE1, CORE2 Core circuit (main circuit)
D1, D2 Diameter DQ Data line (Signal line)
DRV1, DRV2 Power supply circuit (drive circuit)
F1, F2 Frequency band IF1 External interface circuit (input / output circuit, external input / output circuit)
IF2 internal interface circuit (input / output circuit, internal input / output circuit)
M0, M1, M2, M3, M4 Wiring layer P1, P2 Separation distance PKG1, PKG2, PKG3, PKG4, PKG5, PKG6, PKG7, PKG8 Semiconductor device SIG Signal line VD1, VD2, VD3 Power supply line VS1, VS2 Reference potential line

Claims (10)

A wiring board;
An interposer mounted on the first surface of the wiring board;
A first semiconductor component mounted on the interposer;
A second semiconductor component mounted side by side with the first semiconductor component on the interposer and controlling the first semiconductor component;
A plurality of external terminals formed on a second surface opposite to the first surface of the wiring board;
Including
The interposer has a base material made of a semiconductor material as a base material, and a plurality of wiring layers arranged on the main surface of the base material,
The plurality of wiring layers are separated from the main surface of the base material than the first wiring layer, the second wiring layer farther from the main surface of the base material than the first wiring layer, and the second wiring layer. A third wiring layer, and an uppermost wiring layer on which the plurality of electrode pads and the first wiring are formed, and is separated from the main surface of the base material than the third wiring layer,
In plan view, in the first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component,
The ratio of the reference potential wiring that forms part of the reference potential transmission path included in the third wiring layer and the uppermost wiring layer is greater than the ratio of the reference potential wiring included in the first wiring layer. Many
The second wiring layer includes a plurality of signal lines,
The first semiconductor component and the first semiconductor component are electrically connected via the plurality of signal wirings of the second wiring layer,
The plurality of signal wirings of the second wiring layer overlap with the first wiring in a plan view and in the first region,
The semiconductor device, wherein the first wiring is the reference potential wiring. In claim 1,
The semiconductor device, wherein the base material includes an impurity element constituting a conductive characteristic of a first conductivity type or a second conductivity type opposite to the first conductivity type. In claim 1,
The plurality of electrode pads of the uppermost wiring layer includes a first power supply pad for reference potential and a second power supply pad for reference potential,
The first power supply pad is electrically connected to the first semiconductor component through a first bump electrode,
The second power supply pad is electrically connected to the second semiconductor component through a second bump electrode,
The semiconductor device, wherein the first power supply pad and the second power supply pad are electrically connected via the first wiring of the uppermost wiring layer. In claim 3,
The semiconductor device, wherein a separation distance between the uppermost wiring layer and the third wiring layer is larger than a separation distance between the third wiring layer and the second wiring layer. In claim 1,
The semiconductor device, wherein the first wiring formed in the uppermost wiring layer has a mesh shape in plan view. In claim 1,
The second wiring layer further includes a plurality of the reference potential wirings,
The semiconductor device, wherein the plurality of signal lines in the second wiring layer are arranged between the plurality of reference potential lines in plan view. In claim 1,
The semiconductor device, wherein a distance between the plurality of wiring layers of the interposer and a distance between the first wiring layer and the main surface of the base material are smaller than the thickness of each of the plurality of wiring layers. In claim 1,
The semiconductor device, wherein a separation distance between the third wiring layer and the second wiring layer is larger than a separation distance between the second wiring layer and the first wiring layer. In claim 1,
The first semiconductor component includes a first circuit,
The second semiconductor component includes a second circuit that controls the operation of the first circuit of the first semiconductor component,
The semiconductor device, wherein the first semiconductor component and the second semiconductor component are electrically connected via the plurality of signal wirings and the reference potential wiring. In claim 9,
The semiconductor device, wherein the plurality of signal wirings are electrically separated from the wiring board, and the reference potential wiring is electrically connected to the wiring board.

Images