JPH0636596A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable testing in a test mode even if polarity of each bit data written in a memory section is different. CONSTITUTION:A data polarity control circuit 20 which outputs each read out data from a memory cell being a memory section inverting or not inverting its polarity in accordance with a selecting signal at the time of a test mode is provided between the memory cell and a judging circuit 2. Therefore, even if polarity of each bit data written in the memory cell is different, data of which all polarity are coincident by the data polarity control circuit 20 can be inputted to the judging circuit, the test in the test mode can be performed, and range of a function of the test mode can be expanded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a test mode function.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a part of a conventional semiconductor memory device having a test mode function.

As shown in FIG. 3, for example, 4-bit read data read from a memory cell (not shown) serving as a storage unit is input to a determination circuit 2 formed of an EX-OR circuit via a data bus 1. , Read data RD _i (i =
The determination circuit 2 determines whether or not the polarities of 1, 2, 3, 4) all match, and when they match, a high level (hereinafter, referred to as H), and when they do not match, a low level (hereinafter, referred to as H). 1-bit data TD (referred to as L) is output as a match signal and a mismatch signal, respectively.

The test mode and the normal data read mode are selectively selected by inputting or non-inputting the test mode enable signal TE to the switching circuit 3, and the output data TD of the judging circuit 2 is switched in the test mode. The read data RD ₁ output from the circuit 3 and read from the memory cell in the data read mode is output from the switching circuit 3.

Further, the data TD or RD ₁ from the switching circuit 3 is amplified by the output buffer 4, the read data RD _{2 to} RD ₄ are also amplified by the output buffers 5 to 7, and the amplified data are read. It is output to the data output terminals 8-11.

By the way, the above-mentioned judgment circuit 2 is constructed as shown in FIG. 4, for example, and each 4-bit read data RD is formed.
₁ ~ Rd ₄ is NOR gates 12 and 4, respectively 4 inputs
Input to the input NAND gate 13 and NOR gate 1
Both outputs of 2 and NAND gate 13 are input to a 2-input NOR gate 14, and the result of the exclusive OR processing by these respective gates 12 to 14 is output from the NOR gate 14 as data TD. When the read data RD _{1 to} RD ₄ all have the same H or L polarity, the NOR gate 14 outputs the H data TD, and when the read data RD _{1 to} RD ₄ do not have the same polarity, the NOR gate 14 outputs the H data TD. 14 outputs L data TD.

The switching circuit 3 described above is constructed, for example, as shown in FIG. 5, is provided with two transmission gates 15 and 16, and the output data TD of the decision circuit 2 is provided to the input terminal of one transmission gate 15. The read data RD ₁ is input to the other input terminal of the transmission gate 16, and the test mode enable signal TE is input to the gate of the transmission gate 15 on the N-channel MOS transistor 15b side and the P-channel MOS transistor 1 of the transmission gate 16.
The test mode enable signal TE directly input to the gate on the side of 6a and inverted by the inverter 17 is input to the gate of the transmission gate 15 on the side of the P-channel MOS transistor 15a and the gate of the transmission gate 16 on the side of the P-channel MOS transistor 16b. When the test mode enable signal TE of H is input, the transmission gates 15 and 16 are turned on and off, respectively, and the mode is switched to the test mode.
The data TD from the output terminals of both transmission gates 15 and 16 connected to one transmission gate 15 is output as it is, and the transmission of the transmission gate 1 by inputting the test mode enable signal TE of L.
5, 5 and 16 are turned off and on, respectively, to switch to the normal data read mode, and the read data RD ₁ to the other transmission gate 16 is output as it is.

Therefore, in the normal data read mode,
Each read data RD _{1 to} RD read from the memory cell
₄ is output to the read data output terminals 8 to 11 via the output buffers 4 to 7, respectively, and the polarity of the read data RD ₁ to RD ₄ to the read data output terminals 8 to 11 is determined by the determination circuit 2 in the test mode. It is determined whether or not they all match, and if they match, H data TD, and if they do not match, L data TD is output to the read data output terminal 8 via the switching circuit 3 and the output buffer 4, for example, a memory cell. If the polarities of the read data RD _{1 to} RD ₄ to be read from all of the read data output terminals 8 are the same, the output result of the comparator connected to the read data output terminal 8 indicates that the read data output terminal 8 is H if the polarity is H. It can be seen that the reading is normally performed, and if the polarity of the read data output terminal 8 is L, it can be seen that the reading is abnormal.

[0009]

However, in the conventional configuration, in order to test whether or not the data is normally read, as described above, the read data output terminals 8 to 11 are used.
It is necessary to write data in the memory cell in advance so that all the polarities of the data match. The polarity of each bit data written to the memory cell is different, and one read data output terminal has a different polarity from other read data output terminals. It is not possible to test in the test mode with the
In this way, in order to test each read data output terminal with polarity, it is necessary to connect a comparator to each read data output terminal and read each data from the output result of each comparator in the normal data read mode. Since it is necessary to determine the polarities of the read data output terminals 8 to 11, there is a problem that the configuration becomes complicated.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to perform a test in the test mode even when the polarities of the bit data written in the storage section are different. The purpose is to expand the range of test mode functions.

[0011]

In a semiconductor memory device according to the present invention, a read signal of a plurality of bits from a memory portion is input and it is determined whether or not the polarities of the read data are all the same, and a match signal is output. , A judgment circuit for outputting a non-coincidence signal, and provided between the judgment circuit and the output terminal of the read data, and outputs the output of the judgment circuit to the output terminal instead of the read data from the storage section in the test mode. In a semiconductor memory device including a switching circuit, data to be output to the determination circuit between the storage unit and the determination circuit, the polarity of each read data being inverted or non-inverted according to a select signal in a test mode. The feature is that a polarity control circuit is provided.

[0012]

According to the present invention, the data polarity control circuit for inverting or non-inverting the polarity of each read data from the storage unit according to the select signal in the test mode and outputting the inverted data is provided between the storage unit and the determination circuit. , Even if the polarities of the bit data written in the storage unit are different, the data polarity control circuit allows the data with the same polarity to be input to the judgment circuit, and judgment can be made in the same way as before. It is determined whether the polarities of the data input by the circuit match.

[0013]

1 is a block connection diagram of an embodiment of a semiconductor memory device of the present invention.

In FIG. 1, the same reference numerals as those in FIG. 3 denote the same or corresponding ones. The difference from FIG. 3 is that the select signal is generated between the memory cell and the decision circuit 2 in the test mode. Polarity inversion data R of each read data from the memory cell according to SE _i (i = 1, 2, 3, 4)
The polarity of the D _i ′ bar (i = 1, 2, 3, 4) is appropriately inverted or non-inverted, and data RD _i (i = 1, 2, 3, 4) having the same polarity is output to the determination circuit 2. The data polarity control circuit 20 is provided.

The configuration of each bit of the data polarity control circuit 20 is as shown in FIG. 2. In FIG. 2, 21 to 26 are P channel MOS transistors.
27 to 32 are N-channel MOS transistors, V _s is a power supply, and the MOS transistors 21 and 27 and the MOS transistors 26 and 32 respectively provide inverters I ₁ ,
I ₂ is configured and MOS transistors 22, 23, ₂
8, 29 are provided in series between the power supply V _s and the ground to form one clocked inverter CI ₁ , and similarly the MOS transistors 24, 25, 30, 31 are connected to the power supply V _s.
And the ground, and the other clocked inverter CI ₂ is formed in series to form the MOS transistor 23,
The source of 28 and the sources of the MOS transistors 25 and 30 are OR-connected to form an output terminal of the data polarity control circuit 20, and the input data RD _i ′ bar is input to the gates of the MOS transistors 23 and 28 and the inverter I.
₂ is input to the gates of the MOS transistors 26 and 32, the select signal SE _i is input to the gates of the MOS transistors 21 and 27 of the inverter I ₂ , and MO
Inverted signal SE _i bar 9 of select signal SE _i input to the gates of S transistors 22 and 31 and inverted by inverter I ₁ is input to the gates of MOS transistors 29 and 24 and input data inverted by inverter I _2. The RD _i ′ bar is input to the gates of the MOS transistors 25 and 30.

At this time, if the select signal SE _i is H, the operation of the other clocked inverter CI ₂ causes the input data RD _i ′ bar to be output as the data RD _i without being inverted, and the select signal SE _i is L. Then, the operation of _one clocked inverter CI ₁ inverts the input data RD _i ′ bar and outputs it as data RD _i .

Then, in the test mode, the polarities of the select signals SE _{1 to} SE ₄ are appropriately set so that all the polarities of the data RD ₁ to RD ₄ to the determination circuit 2 match based on the polarities of the data previously written in the memory cells. If the polarity of the read data output terminal 8 according to the output data TD of the determination circuit 2 is H, the polarity of the data RD _i from the data polarity control circuit 20 to the determination circuit 2 is set according to the setting of the select signal SE _i. It can be seen that they all match and that data is being read normally, and conversely, if the polarity of the read data output terminal 8 should be H, then L is abnormal.

On the other hand, in the normal data read mode, the select signal SE _i is set to L and the data RD obtained by inverting all the input data RD _i ′ to the data polarity control circuit 20.
_It suffices to input _i to each of the output buffers 4 to 7, whereby normal data reading is performed.

Therefore, even if the polarities of the respective bit data to be written in the memory cell in advance are different, it is possible to judge whether or not the data is normally read in the test mode, and each bit is tested in the test mode. It is possible to give a polarity to each data, and the range of test mode functions can be expanded.

Further, the data polarity control circuit 20 is CMOS
Since the inverter and the clocked inverter are configured by the transistor, the range of the test mode function can be expanded without significantly increasing the number of elements.

Of course, the configuration of the data polarity control circuit 20 is not limited to the above embodiment.

Further, the configurations of the judging circuit 2 and the switching circuit 3 are not limited to those in the above embodiment.

[0023]

As described above, according to the semiconductor memory device of the present invention, the data polarity control circuit for inverting or non-inverting the polarity of each read data according to the select signal in the test mode and outputting the data polarity control circuit is provided. Because it is provided between the judgment circuit,
By setting the select signal, it is possible to input data with the same polarity to the judgment circuit and judge whether the reading is normal or not, and it is possible to give polarity to each bit data in the test mode. The range of test mode functions can be expanded.

[Brief description of drawings]

FIG. 1 is a partial block connection diagram of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a detailed wiring diagram of the data polarity control circuit of FIG.

FIG. 3 is a block connection diagram of part of a conventional semiconductor memory device.

4 is a connection diagram of the determination circuit of FIG.

5 is a connection diagram of the switching circuit of FIG.

[Explanation of symbols]

 2 Judgment circuit 3 Switching circuit 8-11 Read data output terminal 20 Data polarity control circuit

Front page continuation (72) Inventor Masayuki Kuroiwa 4-61-5 Higashino, Itami City, Hyogo Prefecture Mitsubishi Electric Engineering Co., Ltd.

Claims (2)

[Claims] 1. A determination circuit for inputting a plurality of bits of read data from a storage unit, determining whether or not the polarities of the respective read data are all the same, and outputting a coincidence signal and a non-coincidence signal, and the determination circuit. And a switching circuit that is provided between the read data output terminal and the read data output terminal and outputs the output of the determination circuit to the output terminal instead of the read data from the storage section in the test mode. A semiconductor memory characterized in that a data polarity control circuit for inverting or non-inverting the polarity of each read data in response to a select signal in the test mode and outputting the data to the determination circuit is provided between the section and the determination circuit. apparatus. 2. The semiconductor memory device according to claim 1, wherein the data polarity control circuit is composed of a CMOS transistor.