JP2013182659A - Memory device, test device and operation method of them, and memory system and transmission operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system for memory cell repairs with improved reliability, and a memory device and a test device included in the memory system.SOLUTION: The memory system is a memory system, and includes a memory device including a non-volatile storage device having a matrix array configuration in the form of at least N×M (N and M are an integer of two or more), and a test device for testing the memory device. The fail address detected by the test device is transmitted to the memory device and stored in the non-volatile storage device.

Description

  The present invention relates to a memory system, and more particularly, to a method and apparatus for testing a memory device including a nonvolatile storage device and repairing a memory cell using the test device, and a memory system including the same.

The semiconductor chip is manufactured by a semiconductor manufacturing process and then tested by a test equipment in a wafer or die state or a package state.
A defective portion or a defective chip is selected by the test, and when a part of the memory cells is defective, repair is performed to repair the semiconductor chip.

In recent years, a semiconductor chip such as a DRAM has been miniaturized, so that the possibility of an error occurring in the manufacturing process is increasing.
Even if it is not detected in the initial test stage, an error may occur during chip operation.
In order to solve such a problem, there is a problem that various test methods and apparatuses must be developed.

US Pat. No. 7,768,847

  Accordingly, the present invention has been made in view of the above problems in the conventional memory system, and an object of the present invention is to provide a memory system for memory cell repair with improved reliability, a memory device included therein, and To provide a test device.

  Another object of the present invention is to provide an operation method and a transmission operation method of a memory device and a test device for repairing a memory cell with improved reliability.

  In order to achieve the above object, a memory system according to the present invention includes a non-volatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more). A memory device; and a test device for testing the memory device, wherein a fail address (Fail Address) detected by the test device is transmitted to the memory device and stored in the nonvolatile storage device. And

The test apparatus is preferably composed of a semiconductor chip.
Preferably, the semiconductor chip includes an ECC engine, and the nonvolatile storage device includes an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more).
The semiconductor chip includes a beast-in self test (BIST), and the nonvolatile storage device includes an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more). It is preferable.
The beast is preferably connected to the ECC engine.
The semiconductor chip preferably includes an ECC engine or a beast, and further includes a fail address memory for storing the fail address.
The fail address memory is preferably controlled by a control unit.
Preferably, the semiconductor chip includes an ECC engine or a beast, and further includes a fail address memory, an address output unit, a control output unit, a data buffer, and a control unit.
The control output unit preferably controls operations of the ECC engine or the beast, the fail address memory, the data buffer, and the control unit.
The semiconductor chip is preferably formed in a memory controller and connected to a central processing unit (CPU).
The central processing unit (CPU) preferably applies a test command to the memory device.
Preferably, the test command includes a test start command, a test end command, or a fail address transmission command.

The test apparatus is preferably configured to be included in a test equipment.
Preferably, the test equipment further includes a pattern generator, a probe card, and a socket.
The non-volatile storage device is preferably composed of an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more).
Preferably, the memory system further includes a temporary fail address storage device that stores the fail address.
The fail address is preferably stored in the antifuse array under the control of a control unit.
The control unit is preferably activated by receiving a mode activation signal from the decoding unit.
Preferably, the control unit controls writing or reading of the fail address in the antifuse array and controlling transmission of a verification result value to the outside of the memory device.
The anti-fuse array is connected to a repair address storage unit that stores the fail address, the repair address storage unit is connected to a comparison unit that compares an external address and the fail address, and the comparison unit has two addresses. Is preferably connected to a multiplexer (Mux) that selects one of

  The memory device according to the present invention made to achieve the above object includes a temporary fail address storage device for temporarily storing a fail address, and at least N × M form (N and M are used for storing the fail address). A non-volatile storage device having a matrix array structure of an integer of 2 or more, and a control unit that controls an operation for transmitting the fail address stored in the temporary fail address storage device to the non-volatile storage device It is characterized by that.

The non-volatile storage device is preferably composed of an antifuse array.
The control unit reads the fail address stored in the anti-fuse array and transmits a verification result value to the outside of the memory device in order to check whether the fail address is correctly written or not. It is preferable to control as described above.
It is preferable that the control unit controls execution of a reading or writing operation for the antifuse array.
The antifuse array is connected to a repair address storage unit that stores the fail address, and the repair address storage unit is connected to a comparison unit that compares an external address with the fail address. It is preferably connected to a multiplexer (Mux) that selects one from the addresses.
The temporary fail address storage device is preferably connected to an address buffer that receives an external address.
The control unit is preferably activated by a mode activation signal generated by the decoding unit.
The decoding unit is preferably connected to the address buffer and a control buffer that receives a control signal.

  A test apparatus according to the present invention made to achieve the above object is a test apparatus, an error correction circuit for detecting and correcting error data, a fail address memory for storing a fail address of the error data, And a control unit that controls an operation of storing a fail address in the fail address memory and transmitting the fail address to the outside in accordance with a test command.

The error correction circuit is preferably connected to a data buffer that receives the error data.
Preferably, the test command includes a test start command, a test end command, or a fail address transmission command.
The error correction circuit is preferably composed of a beast.
The test apparatus is preferably built in a memory controller and connected to a central processing unit (CPU).
The test apparatus is preferably configured to be included in a test equipment.
Preferably, the test equipment further includes a pattern generator, a probe card, and a socket.

  The test apparatus operating method according to the present invention made to achieve the above object includes a step of detecting the fail address by an error correction circuit in an operation method for fail address transmission from the test apparatus, and the fail address is converted to a fail address. Storing in a memory, entering a fail address transmission mode according to a test command, transmitting a transmission signal including a mode register set command, and transmitting the fail address.

The fail address is preferably detected by an ECC engine or a beast.
Preferably, the transmission signal further includes a write command and a chip selection signal.
Preferably, the test command includes a fail address transmission start command or a fail address transmission end command, and the test command is applied from a central processing unit (CPU).

  In order to achieve the above object, a memory device operating method according to the present invention includes a step of receiving a fail address in accordance with a mode register set command in an operating method for writing a fail address to a memory device, and the fail address is temporarily received. Storing the fail address in a nonvolatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more). To do.

Preferably, the method further includes a step of confirming a storage space of the nonvolatile storage device before storing the fail address in the nonvolatile storage device.
Preferably, the method further comprises a step of reading the stored fail address again after storing the fail address in the nonvolatile storage device.
Preferably, the method further includes a step of transmitting the verification result value according to the read state to the outside serially or in parallel after reading the fail address again.

  In order to achieve the above object, a transmission operation method according to the present invention is an operation method for transmitting a fail address from a test device to a memory device, wherein the test device detects the fail address from an error correction circuit. Storing the fail address in a fail address memory; entering a fail address transmission mode according to a test command; transmitting a transmission signal including a mode register set command; and transmitting the fail address. Receiving at the memory device the fail address in accordance with the mode register set command; storing the fail address in a temporary fail address storage device; and at least N × M form (N and M are 2 Matrix array structure That is characterized by having a step of storing the fail address in the nonvolatile storage device.

  Preferably, the method further includes a step of confirming a storage space of the nonvolatile storage device before storing the fail address in the nonvolatile storage device.

  In addition, a memory system according to the present invention made to achieve the above object includes a test device that provides test data to a memory device, a beast (BIST) for testing the memory device, and at least an N × M configuration. A non-volatile storage device having a matrix array structure (N and M are integers of 2 or more), and storing the fail address generated by the beast test in the non-volatile storage device. It is characterized by.

The non-volatile storage device is preferably composed of an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more).
Preferably, the memory device further includes at least two fail address storage register arrays for temporarily storing fail addresses.
The beast (BIST) preferably transmits the fail address to the fail address storage register array by a fail flag.
The fail generation flag is preferably replaced according to a precharge command.
It is preferable that the test device and the memory device are connected via a TSV (Through Silicon Via) or a bump.
The test device and the memory device are preferably connected via an optical link.

According to the memory device, the test device, the operation method thereof, the memory system, and the transmission operation method according to the present invention, a defective chip can be relieved by detecting and repairing a fail address of a defective memory cell in the memory device. There is an effect.
Further, there is an effect that the memory device can be tested and repaired by the test device during the chip operation or after the package. Therefore, there is an effect that the malfunction of the memory device due to the defective cell is reduced and the operation reliability of the memory device is improved.

1 is a block diagram conceptually illustrating a memory system according to an embodiment of the present invention. 1 is a block diagram conceptually illustrating a memory system according to an embodiment of the present invention. 1 is a block diagram conceptually illustrating a memory system according to an embodiment of the present invention. 1 is a block diagram conceptually illustrating a memory system according to an embodiment of the present invention. It is a block diagram which shows the circuit of the test apparatus by one Embodiment of this invention. 1 is a block diagram showing a system on chip (SOC) with a built-in test device according to an embodiment of the present invention. 1 is a block diagram showing test equipment in which a test apparatus according to an embodiment of the present invention is used. 1 is a block diagram illustrating a circuit of a memory device according to an embodiment of the present invention. 1 is a diagram illustrating a non-volatile storage device according to an embodiment of the present invention. 1 is a diagram illustrating a memory module according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating fail address transmission timing according to an exemplary embodiment of the present invention. FIG. 6 is a timing diagram illustrating fail address transmission timing according to an exemplary embodiment of the present invention. It is a timing diagram which shows the timing which transmits the verification result value by one Embodiment of this invention in parallel. 7 is a table showing verification result values for parallel transmission according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating timings for transmitting verification result values according to an exemplary embodiment of the present invention. 6 is a table showing verification result values for serial transmission according to an embodiment of the present invention. 3 is a flowchart for explaining a method of operating a test apparatus according to an embodiment of the present invention. 3 is a flowchart for explaining a method of operating a test apparatus according to an embodiment of the present invention. 1 is a block diagram schematically illustrating a memory system according to an embodiment of the present invention. 1 is a block diagram illustrating a circuit of a memory device according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating operation timing of the memory device according to the embodiment of the present invention. FIG. 6 is a timing diagram illustrating operation timing of the memory device according to the embodiment of the present invention. 5 is a flowchart illustrating an operation method of a memory device according to an exemplary embodiment of the present invention. 1 is a block diagram showing an optical link of a memory system according to an embodiment of the present invention. 1 is a perspective view schematically showing a TSV multilayer chip to which a memory system according to an embodiment of the present invention is applied. FIG. 3 is a block diagram schematically illustrating various interfaces of a memory system according to an embodiment of the present invention. FIG. 3 is a block diagram showing system connections of a memory system according to an embodiment of the present invention. FIG. 3 is a block diagram showing system connections of a memory system according to an embodiment of the present invention.

  Next, specific examples of a mode for carrying out a memory device, a test device, an operation method thereof, a memory system, and a transmission operation method according to the present invention will be described with reference to the drawings.

The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art.
The present invention can be variously modified and can have various forms, and specific embodiments have been described in detail with reference to the drawings. However, this should not be construed as limiting the invention to the particular forms disclosed, but should be understood to include all modifications, equivalents or alternatives that fall within the spirit and scope of the invention.
Like reference numerals are used for like components while describing the drawings. In the attached drawings, the dimensions of the structures are shown enlarged or reduced from the actual size for the sake of clarity of the present invention.

  The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expression also includes the plural expression unless the context clearly dictates otherwise. In this application, terms such as “including” or “having” designate the presence of features, numbers, steps, actions, components, parts or combinations thereof as described in the specification. Thus, it should be understood that the existence or additional possibilities of one or more other features or numbers, steps, operations, components, components or combinations thereof are not excluded in advance.

  Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. . Terms such as those defined in a general dictionary should be interpreted as meanings consistent with those in the context of the related art, and are ideal or less formal unless explicitly defined in this application. Don't interpret it in a meaningful way.

  1 to 4 are block diagrams conceptually showing a memory system according to an embodiment of the present invention.

Referring to FIG. 1, the memory system includes a test apparatus 100 and a memory apparatus 200.
The test apparatus 100 transmits a fail signal (Fail Addr), a control signal (Control) including an operation command of the memory device 200, and data (DQ). The test apparatus 100 can be included in a memory controller and test equipment.
The memory device 200 is constituted by a DRAM which is a volatile memory. On the other hand, a memory device can be configured by a non-volatile memory such as MRAM, RRAM (registered trademark), PRAM, or NAND Flash.
The memory device 200 includes a non-volatile storage device configured with an anti-fuse array. Nonvolatile storage devices are used to store fail addresses. The non-volatile storage device can be configured with MRAM, RRAM (registered trademark), PRAM, NAND Flash, or the like. The memory device 200 operates according to a control signal (Control), and transmits data to the test device 100.

Referring to FIG. 2, the test apparatus 100 includes an ECC engine (ECC (Error Correcting Code) Engine).
The ECC engine detects the fail data and the fail address via the date received from the memory device and corrects the fail data.
The memory device 200 includes an antifuse array and stores a fail address (Fail Addr) transmitted from the test device 100. The defective memory cell is repaired by the stored fail address.

Referring to FIG. 3, the test apparatus 100 includes a beast (built-in self test: BIST).
The beast tests the test apparatus 100 or the memory device 200. A test date is generated and transmitted to the memory device 200 to test the memory device.
The test data is written into the memory cell, and further read to detect the fail memory cell.
The fail address, which is the address of the fail memory cell, is temporarily stored in the test apparatus 100 and then transmitted to the memory apparatus 200. The transmitted fail address is stored in the antifuse array to repair the fail memory cell.

Referring to FIG. 4, the test apparatus 100 includes a beast and an ECC engine.
The memory device 200 is tested through the beast to store the fail address in the antifuse array.
On the other hand, the fail address of the fail data generated during the operation of the memory device is detected via the ECC engine and stored in the antifuse array of the memory device. When the memory device is not operating, it can be tested using a beast according to a test command from a central processing unit (CPU), and when it is operating, a fail address can be detected using an ECC engine.

FIG. 5 is a block diagram showing a circuit of a test apparatus according to an embodiment of the present invention.
Referring to FIG. 5, a test apparatus 100 includes a fail address memory 100, an ECC engine or BIST 120, a control unit 130, an address output unit 140, and a control. An output unit (Control Output Unit) 150 and an input / output data buffer (Data Buffer In / Out) 160 are included.

The fail address memory 110 stores a fail address detected by the ECC engine 120 or the beast 120. The fail address memory 110 can be composed of a register, an SRAM, or a nonvolatile memory.
An address output unit (Address Output Unit) 140 is connected to the fail address memory 110 and transmits a fail address 141 (ADD) to the memory device 200.
The control output unit 150 transmits a signal 151 including a read command, a write command, a pre-charge command, a mode register set command, and the like to the memory device 200. To do. The control output unit 150 is connected to the control unit 130 and controlled.

The input / output data buffer 160 is controlled by the control unit 130 to receive or transmit input / output data. Input / output data may include only test data for memory device testing. Data received from the memory device is transmitted to the ECC engine or beast 120 via the data buffer.
The control unit 130 is connected to the ECC engine or beast 120, the fail address memory 110, the address output unit 140, the control output unit 150, and the data buffer 160. The control unit 130 receives a test command from a central processing unit (CPU). The test command may include a test start command, a test end command, a fail address transmission start command, and a fail address transmission end command. The operation of storing the fail address detected by the ECC engine 120 or the beast 120 in the fail address memory 110 according to the applied test command is controlled. Further, the transmission of the fail address 141 and the control signal 151 is controlled via the address output unit 140 and the control output unit 150.

  FIG. 6A is a block diagram illustrating a system-on-chip (SOC) incorporating a test apparatus according to an embodiment of the present invention.

Referring to FIG. 6A, a system-on-chip 1100 includes a central processing unit (CPU) 1120, a memory controller 1110, and an interface 1130.
The memory controller 1110 includes the test apparatus 100. The test apparatus includes an ECC engine or beast (BIST) 120, a fail address memory (FAM) 110, a control unit and the like which are components of the circuit block of FIG. The memory controller 1110 is connected to a central processing unit (CPU), and a test command (Com) is applied. The test instructions include a test start instruction, a test end instruction, a fail address transmission start instruction, and a fail address transmission end instruction. The fail address, control signal, and data are transmitted to the memory device 200 via the data interface 1130.

  FIG. 6B is a block diagram illustrating test equipment in which a test apparatus according to an embodiment of the present invention is used.

Referring to FIG. 6B, a test equipment 1200 includes a test apparatus 100, a pattern generator 1210, a probe card 1220, and a socket 1230 according to an embodiment of the present invention. .
The pattern generator 1200 generates various test data for testing the memory device 200. The probe card 1220 directly contacts the test pad (Pad) of the memory device through the probe needle (Probe Needle) and transmits test data. The socket 1230 allows the memory device to be fixed during the memory device test.

  FIG. 7 is a block diagram illustrating a circuit of a memory device according to an embodiment of the present invention.

  Referring to FIG. 7, the memory device 200 includes an address buffer 210, a control buffer 220, a data buffer 230, a decoding unit 240, and a repair address storage. Part (Repair Address Register) 250, comparison unit (Comparing Unit) 251, multiplexer (Mux) 252, temporary fail address storage device (Temporary Fail Address Storage) 260, control unit (Control Unit) 270 and non-volatile storage device 270 A fuse array 280 and a memory cell array 290 are included.

The fail address is received via the address buffer 210 and temporarily stored in the temporary fail address storage device 260.
The temporary fail address storage device 260 includes a register array, an SRAM, and a nonvolatile memory.
The decoding unit 240 receives a control signal through the control buffer 220 and performs decoding to generate a mode enable signal. The control signal includes a read command, a write command, a precharge command, a mode register set signal, and the like.
The control unit 270 is activated by the mode enable signal to store the fail address in the antifuse array 280 of the nonvolatile memory storage device.

The control unit 270 reads and senses the stored fail address in order to verify whether the fail address is correctly programmed.
The program result value (Verify Result) is transmitted to the test apparatus via the data output pin.
The antifuse array 280 of the nonvolatile storage device is connected to a repair address storage unit 250 that stores a fail address, and the repair address storage unit 250 is connected to a comparison unit 251 that compares an external address and a fail address. Are connected to a multiplexer (Mux) 252 which selects one of the two addresses.
Data transmitted from the data buffer 230 is used as a chip selection signal (Component Designation) for selecting a chip on the memory module.

  FIG. 8 is a diagram illustrating a non-volatile storage device according to an embodiment of the present invention.

Referring to FIG. 8, the nonvolatile storage device 1000 includes a fuse array 1100a having a plurality of fuses 1110a, a level shifter (1200_1 to 1200_m) that generates a high voltage for changing the resistance state of the fuses 1110a, and a fuse array 1100a. Sense amplifier unit 1300 for sensing / amplifying information stored in the memory.
The nonvolatile storage device 1000 includes a first register unit 1400 and a second register unit 1500 for storing fuse data generated by reading information stored in the anti-fuse array 1100a. Each of the first register unit 1400 and the second register unit 1500 can be realized as a shift register including a plurality of registers.

The fuse array 1100a includes a plurality of fuses 1110a, and information is stored in each fuse. The fuse array 1100a can include a laser fuse whose connection is controlled by laser irradiation, or can include an electrical fuse whose connection is controlled by an electrical signal. Further, the fuse array 1100a can include an anti-fuse, and the anti-fuse has a characteristic that its state is converted from a high resistance state to a low resistance state by an electrical signal (for example, a high voltage signal).
As the fuse array 1100a, any one of the above-described plural types may be applied. However, in the following embodiment, it is assumed that the fuse array 1100a is an antifuse array including an antifuse. To explain.
Information stored in the antifuse and data read from the antifuse are referred to as fuse data.

The antifuse array 1100a has an array structure in which the antifuses 1110a are arranged at positions where a plurality of rows and columns intersect.
For example, if the antifuse array 1100a has m rows and n columns, the antifuse array 1100a has m × n antifuses 1110a. m word lines (WL1 to WLm) for accessing antifuses 1110a arranged in m rows and n columns for transmitting information read from antifuses 1110a. N bit lines (BL1 to BLn) to be arranged are connected to the fuse 1110a.

The antifuse array 1100a stores various information related to the operation of the nonvolatile storage device 1000.
For example, the antifuse array 1100a can store setting information for setting the operating environment of the nonvolatile storage device 1000, and the setting information is voltage signals (WLP1 to WLPm) provided from level shifters (1200_1 to 1200_m). Is applied to the antifuse array 1100a to change the state of the antifuse 1110a.
Unlike a general fuse circuit such as a laser fuse circuit or an electrical fuse circuit, the antifuse 1110a starts with a high resistance state and changes to a low resistance state by a programming operation to store information. The antifuse 1110a may have a structure having two conductive layers and a dielectric layer therebetween, that is, a capacitor structure, and a high voltage is applied between the two conductive layers to cause the dielectric layer to break down. To program.

After the antifuse array 1100a is programmed, a read operation for the antifuse array 1100a is performed when the nonvolatile storage device 1000 starts to be driven. The read operation with respect to the antifuse array 1100a can be performed simultaneously with the driving of the nonvolatile storage device 1000, or can be performed after a predetermined set time from the driving of the nonvolatile storage device 1000.
A word line selection signal is provided through the word lines (WL1 to WLm) of the antifuse array 1100a, and information stored in the selected antifuse 1110a is transmitted to the sense amplifier unit 1300 through the bitlines (BL1 to BLn). Provided. Due to the characteristics of the array structure, the information of the antifuse array 1100a can be accessed randomly through the driving of the word lines (WL1 to WLm) and the bit lines (BL1 to BLn).

  For example, the word lines (WL1 to WLm) are sequentially driven, so that the antifuses 1110a from the first row to the mth row of the antifuse array 1100a are sequentially accessed. Information of the antifuse 1110a accessed in order is provided to the sense amplifier unit 1300. The sense amplifier unit 1300 includes one or more sense amplifier circuits. For example, when the antifuse array 1100a includes n columns, the sense amplifier unit 1300 includes n sense amplifier circuits corresponding to the n columns. The n sense amplifier circuits are connected to n bit lines (BL1 to BLn), respectively.

For example, an odd (ODD) sense amplifier circuit and an even (EVEN) sense amplifier circuit are arranged corresponding to the first bit line BL1, and the odd sense amplifier circuit is connected to the odd-numbered word lines WL1, WL3, WL5,. Information of the antifuse 1110a is sensed / amplified and output, and the even sense amplifier circuit senses / amplifies information of the antifuse 1110a connected to the even-numbered word lines WL2, WL4, WL6,.
However, the embodiment of the present invention is not limited to this, and various modifications of the arrangement of the sense amplifier circuits are possible. For example, only one sense amplifier circuit can be arranged corresponding to one bit line, or three or more sense amplifier circuits can be arranged corresponding to one bit line.

  The sense amplifier unit 1300 senses / amplifies information accessed to the antifuse array 1100a and outputs the sensed / amplified information. The sensed / amplified information is fuse data (OUT1 to OUTn) used for setting an actual operating environment of the nonvolatile storage device 1000. As described above, in the example in which two sense amplifier circuits are arranged corresponding to one bit line, any one fuse data (for example, the first fuse data OUT1) is actually odd fuse data and even fuse data. Can be included.

The fuse data (OUT1 to OUTn) output from the sense amplifier unit 1300 is provided to the first register unit 1400.
The first register unit 1400 can be realized by a shift register in which a plurality of registers are connected in series to sequentially transmit signals. The first register unit 1400 includes a smaller number of registers than the number of antifuses 1110a provided in the antifuse array 1100a. In addition, the number of registers provided in the first register unit 1400 can be related to the number of columns in the antifuse array 1100a. For example, when the antifuse array 1100a has n columns, the first register unit 1400 may include n registers. Alternatively, as described above, when two sense amplifier circuits are arranged corresponding to one bit line, the first register unit 1400 may include 2 × n registers.

The first register unit 1400 receives fuse data (OUT1 to OUTn) in units of rows of the antifuse array 1100a.
For example, when any one row of the antifuse array 1100a is selected, the first register unit so that the fuse data (OUT1 to OUTn) from the antifuse 1110a connected to the word line of the selected row are in parallel. 1400. The first register unit 1400 provides the fuse data (OUT1 to OUTn) to the second register unit 1500 by shifting the received fuse data (OUT1 to OUTn) in bit units.

The second register unit 1500 can be realized by a shift register in which a plurality of registers are connected in series to sequentially transmit signals. In addition, the same number of registers as the number of antifuses 1110a included in the antifuse array 1100a can be included.
The fuse data (OUT1 to OUTn) stored in the second register unit 1500 can be used as information for setting the operating environment of the nonvolatile storage device 1000. For example, a part of the fuse data (OUT1 to OUTn) stored in the second register unit 1500 is information for replacing a memory cell (not shown) provided in the nonvolatile storage device 1000 with a redundant memory cell ( Info_FA), and the other part is used as trimming information (Info_DC) for adjusting the level of the voltage generated from the nonvolatile storage device 1000.

  In order to store the fuse data (OUT1 to OUTn) from the antifuse array 1100a, a register connected to the sense amplifier unit 1300 for temporarily storing the fuse data (OUT1 to OUTn) and the fuse data (OUT1 to OUTn) A register that is arranged adjacent to various circuit blocks (for example, row and column decoders and DC voltage generators) of the nonvolatile storage device 1000 that uses fuses and provides fuse data (OUT1 to OUTn) to the circuit blocks is required. .

According to the embodiment of the present invention, the first register unit 1400 receives the fuse data (OUT1 to OUTn) output from the sense amplifier unit 1300, and the second register unit 1500 disposed adjacent to the circuit block. Fuse data (OUT1-OUTn) is transmitted.
In particular, the antifuse array 1100a has an array structure, and the first register unit 1400 includes a number of registers corresponding to the number of columns of the antifuse array 1100a. Therefore, the first register unit 1400 includes the entire antifuse array 1100a. The number of registers is smaller than the number of fuses 1110a.

  For example, when one sense amplifier circuit is arranged corresponding to one bit line, the first register unit 1400 includes n sense amplifier circuits. Thus, the number of registers in the first register unit 1400 related to the fuse data (OUT1 to OUTn) does not need to be maintained at m × n, and only n is sufficient. In particular, even if a large number of antifuses 1110a are provided in the antifuse array 1100a, the number of registers in the first register unit 1400 can be limited to n by the structure of the antifuse array 1100a. It is possible to prevent the number of registers from increasing proportionally due to the increase in.

  FIG. 9 is a diagram illustrating a memory module according to an embodiment of the present invention.

Referring to FIG. 9, a module including a memory including the memory device of the present invention.
For example, one module is composed of 8 DRAMs. The DRAM includes an antifuse array that is a nonvolatile storage device. When the fail address is stored in the DRAM 5, the memory controller can select the memory device of the DRAM 5 by transmitting data “0” only to the DRAM 5 chip. The antifuse array is used to store a fail address generated in each DRAM chip.
A command (Command) and an address (Address) are shared by the eight DRAM chips.

  FIG. 10 is a timing diagram illustrating fail address transmission timing according to an embodiment of the present invention.

Referring to FIG. 10, a mode register set ((Mode Register Set) instruction, an active (ACT) instruction, a read (Read) instruction, and a write (Write) instruction are received through a command line.
A row address (F-RA) and a column address (F-CA) are received through an address line.
Referring to the module of FIG. 10, when the DRAM 5 is selected from the eight DRAMs, it is selected by receiving only “0” (“low”) data through the data line (DQ). When DQ 0 to DQ 7 are set to “low” in the DRAM 5, the fail address is stored in the antifuse array which is a nonvolatile storage device of the DRAM 5.

A mode register set command (MRS), an active command (ACT), and a write command (WR) are sequentially applied, and after a row address (F-RA) and a column address (F-CA) are input, as final chip selection data “0” is applied through the DQ pin, and the fail address is stored in the nonvolatile storage device.
This section corresponds to a fail address transmission (Fail Address Transfer) section. The fail address programmed according to the read command (RD) is read again, and this corresponds to the interval for verifying the interval until a new mode register set command is received. Verification is completed by another mode register set (MRS) instruction after the read instruction.

  Referring to FIG. 11, although similar to the description of the timing of FIG. 10, the difference is that only the fail-fail address (F-RA) is received through the address line (ADD) and fail address repair is performed. When reading and verifying the fail address again, the verification is completed according to the pre-charge instruction and the mode is left.

  FIG. 12 is a timing diagram illustrating the timing for transmitting the verification result value in parallel according to an embodiment of the present invention.

  Referring to FIG. 12, a mode register set command (MRS), an active command (ACT), and a write command (WR) are applied through a command line, and row and column fail addresses are applied to an antifuse array as a nonvolatile memory device. Save (F-RA, F-CA). Thereafter, the data is read again for verification of the stored data, the state of the data is confirmed, and the verification result value is transmitted to the external test apparatus 100 via the data lines DQ1, DQ1, and DQ3. For example, a “low” value is transmitted in parallel via DQ0, DQ1, and DQ2. The values transmitted to the remaining data lines including DQ3 (DQ3,..., DQ7) are not recognized by the memory controller.

  FIG. 13 is a table showing verification result values for parallel transmission according to an embodiment of the present invention.

Referring to FIG. 13, the verification result values are DQ0, DQ1, and DQ2 verification result values in case 1 in which the state of the storage value can be known by reading the storage value again into the anti-fuse array that is a nonvolatile memory. “Low / Low / Low” is when the program is completed normally. It means that fail data (Fail Bit) is replaced by Row Redundant Cells (Row Redundant Cells).
When the verification result value of Case 2 is “low / low / high”, it means that the program is normally completed and is replaced by column redundant cells (Column Redundant Cells).
In case 3, “low / high / low” means that the program is completed normally and the fail data (Fail Bit) is replaced by a single redundant cell.
In case 4, “low / high / high” means that no specific meaning is given for future use.

Cases 5 to 8 mean that the program is not complete.
In case 5, “high / low / low” means that there is a problem with the rupture for the memory cell, and in case 6, “high / low / high” means that the rupture is in progress. . In this case, after waiting for a while, verification can be requested again by a read command (RD).
In case 7, “high / high / low” is a case where there is no redundant cell, and repair is impossible, so the fail memory needs to be replaced.
In case 8, “high / high / high” means that the current chip is not selected.
The verification result value is transmitted to the test apparatus in parallel by the DQ0, DQ1, and DQ2 pins.

  FIG. 14 is a timing diagram illustrating timings for transmitting verification result values according to an embodiment of the present invention.

Referring to FIG. 14, the verification result value according to FIG. 13 is transmitted serially.
For example, 3-bit verification result values are serially transmitted to DQ0. The same verification result value is transmitted to the test apparatus in DQ7.

  FIG. 15 is a table showing verification result values for serial transmission according to an embodiment of the present invention.

Referring to FIG. 15, in case 1 (LLL), it means that fail data (Fail Bit) is replaced by a low redundant cell.
For example, as the verification result value, 3-bit data is serially transmitted to the test apparatus via one DQ pin.
Case 6 (HLH) means that the rupture is still in progress and is transmitted serially via each DQ pin (DQ0, DQ1, DQ2, DQ3).

  16 and 17 are flowcharts for explaining an operation method of the test apparatus according to the embodiment of the present invention.

Referring to FIG. 16, the test apparatus performs the following operation for fail address detection and transmission.
First, a step of detecting a fail address by the ECC engine or the beast is performed (step S100).
Next, the detected fail address is stored in a fail address memory (FAM) (step S105).
Next, a step of entering a fail address transmission mode is performed in accordance with a test command from the central processing unit (CPU) (step S110). The test instructions include a test start instruction, a test end instruction, a fail address transmission start instruction, and a fail address transmission end instruction.
Next, a mode register set (Mode Register Set) command, a chip selection signal, and a fail address are transmitted (step S120).

Referring to FIG. 17, the memory device receives a mode register set command, a chip selection signal, and a fail address (step S130).
Next, a step of storing the fail address in the temporary fail address storage device is performed (step S140).
Next, a step of entering a mode for programming the nonvolatile storage device is performed (step S150).
Next, the storage space of the antifuse array that is a nonvolatile storage device is detected (step S160).
Next, a step of programming the antifuse array, which is a nonvolatile storage device, is performed (step S170).
Next, a step of reading again the programmed data for verification of the stored data is performed (step S180).
Next, after confirming the state of the stored data, the verification result value is transmitted to the outside (step S190).
Finally, a step of replacing fail bits is performed (step S200).

  FIG. 18 is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

Referring to FIG. 18, the memory system includes a test apparatus 100 and a memory apparatus 200.
The test apparatus transmits a fail address (Addr), a control signal (Control), and data.
The memory device 200 includes a beast and an antifuse array that is a non-volatile memory device. The beast tests the memory device 200 according to a test command from the test device applied by the CPU, and stores the fail address in an antifuse array that is a nonvolatile memory device.

  FIG. 19 is a block diagram illustrating a circuit of a memory device according to an embodiment of the present invention.

  Referring to FIG. 19, the memory device 300 includes a fuse array 340 that is a nonvolatile memory that stores fail addresses as program data, a temporary fail address storage device (FAM) 330, and a fuse array information storage device 350 that stores information about fuses. , A control unit 360 for controlling the fuse array 340 and the fuse array information storage device 350, a beast 310 for detecting a fail address, and a memory cell array.

The beast 310 detects a fail address by receiving a test command (Control) and a test date (DQ) from the test apparatus and writing (Read) and reading (Read) the memory cell array 320.
When fail data is generated, a fail flag (Fail Flag) is transmitted to the temporary fail address storage device (FAM) 330 as a fail address corresponding to the fail data. The FAM is composed of a register, and is composed of a plurality of fail address arrays (FAM1,..., FAMn).
The control unit 360 can check the space of the fuse array via the fuse array information storage device 350. Further, it is possible to program-control program instructions and program addresses in the fuse array 340 which is a nonvolatile storage device.
On the other hand, a test command is applied from the test apparatus to the control signal (Control), and thereby the beast 310 is activated. Further, the fail address stored in the FAM 330 is transmitted to the fuse array 340 by the control signal.

  20 and 21 are timing diagrams illustrating operation timings of the memory device according to the embodiment of the present invention.

Referring to FIG. 20, an active (ACT) command and a read (Read) command are input through a command (CMD) line.
Also, test data (EDQ) is input through the DQ line. The test data (EDQ) is written into the memory cell array, and the test data stored in the memory cell is read again according to the read command to generate read data.
When the fail flag signal changes from high to low, the N row address is written to FAM # 1, and when the fail flag is generated (N + 1), the row address is written to FAM # 2. The command (CMD) and data input are input in synchronization with the clock (CLK), and the clock activation (CKE) and chip selection signal are also applied in synchronization with the clock.

Referring to FIG. 21, an active (ACT) instruction, a read (RD) instruction, and a precharge (Pre) instruction are input through a command (CMD) line.
Although almost similar to the timing of FIG. 20, the N row address is transmitted to FAM # 1 according to the precharge (Pre) command, and the (N + 1) row address is transmitted to FAM # 2 again according to the precharge (Pre) command.
FAM330 (refer FIG. 19) is comprised from a register or SRAM.

  FIG. 22 is a flowchart illustrating a method for operating a memory device according to an embodiment of the present invention.

Referring to FIG. 22, the memory device receives an active command and a command (CMD) including a write / read command from the test device (step S300).
Next, a step of activating the memory device beast according to the command (CMD) is performed (step S310).
Next, a step of detecting a fail address, generating a fail flag, or receiving a precharge command is performed (step S320).
Next, a step of saving the fail address by FAM according to the fail flag or the precharge command is performed (step S330).
A step of entering a program mode for programming a fail address in the fuse array is performed (step S340).
A step of confirming the capacity (Capacity) of the fuse memory is performed (step S350).
Next, the fuse array is programmed (step S360).
Finally, a step of repairing the fail data (Fail Bit) is performed (step S370).

  FIG. 23 is a block diagram illustrating an optical link of the memory system according to an embodiment of the present invention.

Referring to FIG. 23, the memory system includes a controller 8100 and a memory device 8200.
The controller 8100 includes a control unit 8110 including an ECC engine or a beast, a controller transmitter (CTx) 8121 including a device (E / O) that converts an electrical signal into an optical signal, and a device that converts an optical signal into an electrical signal ( Controller receiver (CRx) 8122 including O / E).
The memory device 8200 includes an anti-fuse array 8221, a beast 8222, a DRAM core 8223, which are nonvolatile storage devices, and a transmitter (MTx) 8212 including a device (E / O) that changes an electrical signal to an optical signal. It comprises a receiver (MRx) 8211 including a device (O / E) for changing to an electrical signal.
The controller 8100 and the memory device 8200 are connected to the optical link 0 (8500) and the optical link 1 (8501) for transmission and reception. In other embodiments, transmission and reception may be performed over a single optical link.
The input / output circuit 8120 of the controller 8100 and the input / output circuit 8210 of the memory device 8200 are connected to each other via an optical link.

  FIG. 24 is a perspective view schematically showing a TSV multilayer chip to which the memory system according to the embodiment of the present invention is applied.

Referring to FIG. 24, the interface chip 3100 is positioned at the lowest layer, and the memory devices 0 to 3 (3200, 3300, 3400, 3500) are positioned thereon.
The interface chip 3100 may include an ECC engine or beast, a memory controller, and a central processing unit (CPU).
The memory device (memory chip) includes antifuse arrays 0 to 3 (3601, 3602, 3603, 3604) and beasts 0 to 3 (3801, 3802, 3803, 3804) which are nonvolatile storage devices.
The fail address of the memory device is detected through the test device of the interface chip 3100, and the fail address is stored in the antifuse array. The memory device (memory chip) and the memory device (memory chip) are connected via micro bumps (μBump), and the memory device (memory chip) itself is connected via TSV (Through Silicon Via) (reference numeral 3701, 3702, 3703, 3704). For example, the number of stacked memory devices (memory chips) can be one or more.

  FIG. 25 is a block diagram schematically illustrating various interfaces of a memory system according to an embodiment of the present invention.

Referring to FIG. 25A, the memory system includes a controller 4000 and a memory device 5000.
The controller 4000 includes a control unit 4100 and an input / output circuit 4200.
The control unit 4100 can include an ECC engine or a beast.
The memory device 5000 includes a DRAM core 5300, an antifuse array 5100 that is a nonvolatile storage device, a beast 5400, and an input / output circuit 5300.
The input / output circuit 4200 of the controller 4000 includes an interface that transmits a command, a control signal, an address, and a data strobe (DQS) to the memory device 5000 and transmits and receives data (DQ). A fail address is transmitted through the interface.

  Referring to (b) of FIG. 25, the input / output circuit of the controller 4000 transmits the chip selection signal (CS) and the address (Addr) in one package (Packet), and transmits and receives data (DQ). Interface. A fail address is transmitted through the interface.

  Referring to (c) of FIG. 25, the input / output circuit of the controller 4000 transmits the chip selection signal (CS), the address (Addr), and the write data (wData) as one package (Packet), and transmits the read data (Packet). It includes an interface that receives rData). A fail address is transmitted through the interface.

  Referring to (d) of FIG. 25, the input / output circuit of the controller 4000 has an interface for transmitting and receiving a command (Com.), An address (Addr), and data (DQ), and receiving a chip selection signal (CS). Including. A fail address is transmitted through the interface.

  26 and 27 are block diagrams showing system connections of the memory system according to the embodiment of the present invention.

  Referring to FIG. 26, a memory including an antifuse array 7301 and a beast 7302 which are nonvolatile memories, a central processing unit (CPU) including a beast or ECC engine 7101, and a user interface 7200 are connected via a system bus 7110. .

  Referring to FIG. 27, a memory including an antifuse array and a beast via a system bus 6110, a memory system 6500 including a memo controller 6510 including a beast or ECC engine 7101, a central processing unit (CPU) 6100, a ram ( RAM) 6200, user interface 6300, and modem 6400 are connected.

  The present invention is not limited to the above-described embodiment. Various modifications can be made without departing from the technical scope of the present invention.

  The present invention is preferably used for a semiconductor memory device and a memory system including the same.

100 test equipment 110 fail address memory (FAM)
120 ECC engine (or Beast)
DESCRIPTION OF SYMBOLS 130 Control unit 140 Address output unit 150 Control output unit 160 Input / output data buffer 200 Memory device 210 Address buffer 220 Control buffer 230 Data buffer 240 Decoding unit 250 Repair address storage unit 251 Comparison unit 252 Multiplexer 260 Temporary fail address storage device 270 Control unit 280 Antifuse array 290 Memory cell array 1100 System on chip 1000 Non-volatile storage device 1110 Memory controller 1120 Central processing unit (CPU)
1130 Interface 1200 Test equipment 1210 Pattern generator 1220 Probe card 1230 Socket

Claims (52)

A memory system,
A memory device including a nonvolatile storage device having a matrix array structure of at least N × M form (N and M are integers of 2 or more);
A test device for testing the memory device;
A memory system, wherein a fail address (Fail Address) detected by the test device is transmitted to the memory device and stored in the nonvolatile storage device.   The memory system according to claim 1, wherein the test apparatus includes a semiconductor chip.   The semiconductor chip includes an ECC engine, and the nonvolatile storage device includes an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more). The memory system described in.   The semiconductor chip includes a beast-in self test (BIST), and the nonvolatile storage device includes an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more). The memory system according to claim 2.   The memory system according to claim 4, wherein the beast is connected to the ECC engine.   The memory system according to claim 2, wherein the semiconductor chip includes an ECC engine or a beast, and further includes a fail address memory for storing the fail address.   The memory system according to claim 6, wherein the fail address memory is controlled by a control unit.   3. The memory system according to claim 2, wherein the semiconductor chip includes an ECC engine or a beast, and further includes a fail address memory, an address output unit, a control output unit, a data buffer, and a control unit.   9. The memory system according to claim 8, wherein the control output unit controls operations of the ECC engine or the beast, the fail address memory, the data buffer, and the control unit.   The memory system according to claim 2, wherein the semiconductor chip is formed in a memory controller and connected to a central processing unit (CPU).   The memory system according to claim 10, wherein the central processing unit (CPU) applies a test command to the memory device.   12. The memory system of claim 11, wherein the test instruction includes a test start instruction, a test end instruction, or a fail address transmission instruction.   The memory system according to claim 1, wherein the test apparatus is included in a test equipment.   The memory system of claim 13, wherein the test equipment further includes a pattern generator, a probe card, and a socket.   The memory system according to claim 1, wherein the nonvolatile storage device includes an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more).   The memory system of claim 15, further comprising a temporary fail address storage device that stores the fail address.   The memory system of claim 16, wherein the fail address is stored in the antifuse array under control of a control unit.   The memory system of claim 17, wherein the control unit is activated in response to a mode activation signal from a decoding unit.   The control unit according to claim 17, wherein the control unit controls writing or reading of the fail address to the anti-fuse array, and controls transmission of a verification result value to the outside of the memory device. Memory system. The antifuse array is connected to a repair address storage unit that stores the fail address,
The repair address storage unit is connected to a comparison unit that compares an external address with the fail address, and the comparison unit is connected to a multiplexer (Mux) that selects one from two addresses. Item 17. The memory system according to Item 16. A temporary fail address storage device for temporarily storing the fail address;
A non-volatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more) for storing the fail address;
A memory device comprising: a control unit for controlling an operation for transmitting the fail address stored in the temporary fail address storage device to the nonvolatile storage device.   The memory device of claim 21, wherein the nonvolatile storage device comprises an antifuse array.   The control unit reads the fail address stored in the anti-fuse array and transmits a verification result value to the outside of the memory device in order to check whether the fail address is correctly written or not. The memory device according to claim 22, wherein the memory device is controlled as follows.   The memory device of claim 22, wherein the control unit controls execution of a reading or writing operation to the antifuse array. The antifuse array is connected to a repair address storage unit that stores the fail address,
The repair address storage unit is connected to a comparison unit that compares the external address with the fail address;
23. The memory device according to claim 22, wherein the comparison unit is connected to a multiplexer (Mux) that selects one of the two addresses.   The memory device of claim 21, wherein the temporary fail address storage device is connected to an address buffer that receives an external address.   The memory device of claim 21, wherein the control unit is activated by a mode activation signal generated by a decoding unit.   25. The memory device of claim 24, wherein the decoding unit is connected to the address buffer and a control buffer that receives a control signal. A test device,
An error correction circuit that detects and corrects error data;
A fail address memory for storing a fail address of the error data;
And a control unit for controlling the operation of storing the fail address in the fail address memory and transmitting the fail address to the outside in accordance with a test command.   30. The test apparatus according to claim 29, wherein the error correction circuit is connected to a data buffer that receives the error data.   30. The test apparatus of claim 29, wherein the test command includes a test start command, a test end command, or a fail address transmission command.   30. The test apparatus according to claim 29, wherein the error correction circuit comprises a beast.   30. The test apparatus according to claim 29, wherein the test apparatus is built in a memory controller and connected to a central processing unit (CPU).   30. The test apparatus according to claim 29, wherein the test apparatus is included in a test equipment.   The test apparatus of claim 34, wherein the test equipment further includes a pattern generator, a probe card, and a socket. In an operation method for fail address transmission from a test device,
Detecting the fail address with an error correction circuit;
Storing the fail address in a fail address memory;
Entering a fail address transmission mode according to a test instruction;
Transmitting a transmission signal including a mode register set command;
A test apparatus operating method comprising: transmitting the fail address.   The test apparatus operating method according to claim 36, wherein the fail address is detected by an ECC engine or a beast.   The method of claim 36, wherein the transmission signal further includes a write command and a chip selection signal.   The test apparatus operating method according to claim 36, wherein the test command includes a fail address transmission start command or a fail address transmission end command, and the test command is applied from a central processing unit (CPU). In an operating method for writing a fail address to a memory device,
Receiving a fail address according to a mode register set instruction;
Storing the fail address in a temporary fail address storage device;
And storing the fail address in a non-volatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more).   41. The method of claim 40, further comprising: confirming a storage space of the nonvolatile storage device before storing the fail address in the nonvolatile storage device.   41. The method of claim 40, further comprising reading the stored fail address again after storing the fail address in the nonvolatile storage device.   43. The method of claim 42, further comprising transmitting a verification result value according to a read state to the outside serially or in parallel after reading the fail address again. In an operation method for transmitting a fail address from a test device to a memory device,
In the test device,
Detecting the fail address from an error correction circuit;
Storing the fail address in a fail address memory;
Entering a fail address transmission mode according to a test instruction;
Transmitting a transmission signal including a mode register set command;
Transmitting the fail address;
In the memory device,
Receiving the fail address in accordance with the mode register set instruction;
Storing the fail address in a temporary fail address storage device;
And storing the fail address in a non-volatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more).   45. The transmission operation method of claim 44, further comprising the step of confirming a storage space of the nonvolatile storage device before storing the fail address in the nonvolatile storage device. A test device for providing test data to the memory device;
A memory device comprising: a beast (BIST) for testing the memory device; and a nonvolatile storage device having a matrix array structure of at least N × M (N and M are integers of 2 or more). ,
A memory system, wherein a fail address generated by the Beast test is stored in the nonvolatile storage device.   47. The memory system according to claim 46, wherein the nonvolatile storage device comprises an antifuse array having a matrix structure of at least N × M (N and M are integers of 2 or more).   The memory system of claim 46, wherein the memory device further includes at least two fail address storage register arrays for temporarily storing fail addresses.   49. The memory system according to claim 48, wherein the beast (BIST) transmits the fail address to the fail address storage register array by a fail flag.   50. The memory system of claim 49, wherein the fail flag is substituted according to a precharge command.   The memory system according to claim 1, wherein the test device and the memory device are connected to each other via a TSV (Through Silicon Via) or a bump. The memory system according to claim 1, wherein the test device and the memory device are connected via an optical link.

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