KR101519615B1 - Method and apparatus for controlling data input of semiconductor memory device - Google Patents

Abstract

The present invention relates to a data input control method and apparatus for a semiconductor memory device. The disclosed data input control method reads data constituting n chunks each consisting of y bits extracted from x ECC words (n and x and y are integers of 2 or more and y is a multiple of x) Forming n chunks of data so that bits belonging to different ECC words are transmitted to channels formed respectively in the layers of the semiconductor memory device having n layer stacked structures when compared with other channels adjacent to each other in the layer stacking direction; Lt; / RTI > Therefore, even when a continuous channel error occurs in the layer stacking direction when data is transmitted in each layer channel, it can be corrected by an ECC error correction method, and three or more consecutive channel errors It is possible to detect the error through the ECC error correction method. Therefore, there is an advantage that reliability of data transmitted through a channel is increased.

Description

TECHNICAL FIELD [0001] The present invention relates to a data input control method and apparatus for a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a data input control method and apparatus for a semiconductor memory device, and more particularly, To a channel of each layer so as to be transmitted, and to a method and an apparatus for controlling data input of a semiconductor memory device.

The semiconductor memory is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) Semiconductor memory is divided into volatile memory and nonvolatile memory.

The volatile memory is a memory device in which the stored data is lost when the power supply is interrupted. Volatile memories include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). A nonvolatile memory is a memory device that retains data that has been stored even when the power supply is turned off. The non-volatile memory includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

In such a semiconductor memory, an ECC (Error Correction Code) word is used for error correction. According to an error correction method using the ECC word, a bit error in the ECC word can be corrected and a two-bit error can be detected. This is called SEC / DED (Single Error Correction / Double Error Detection).

Further, according to the error correction method using the more advanced ECC word dispersion, an ECC word is distributed and stored in a plurality of memory devices, thereby correcting or detecting a continuous multi-bit error occurring in one memory device .

On the other hand, a channel is formed in the semiconductor memory. Channel means an individual channel through which data flows in the system. In a three-dimensional memory device in which a plurality of layers are stacked, channels located in each layer are also stacked in the stacking direction of the layers.

Data errors occurring in these channels are characterized by large spatial correlation of error locations mainly due to heat, noise or impact.

However, since a structure in which a plurality of layers are stacked has a structure in which channels through which data is transferred are stacked in a three-dimensional memory device, a spatial correlation is generated between the channels in the vertical direction, that is, in the stacking direction of layers .

In the case of storing or reading data in a three-dimensional memory device using an error correction method using ECC word dispersion, data belonging to the same ECC word are transmitted to the channels of adjacent layers in the stacking direction when viewing the vertical cross- do.

Therefore, when a continuous channel error occurs in the stacking direction when data is transmitted in each layer channel, it can not be corrected through the ECC error correction method. If three or more consecutive channel errors occur, an ECC error There is a problem that it can not be detected through the correction method. Here, a channel error means a data error caused by a flip phenomenon occurring in a channel during data transmission, a data error caused by a failure of an input / output terminal, or a data error caused by a failure of a through silicon via (TSV).

Korean Patent Publication No. 10-2008-0086152, published on September 25, 2008.

According to the embodiment of the present invention, in a semiconductor memory device having a structure in which a plurality of layers are laminated, when inputting that an ECC word is transmitted in a channel of each layer, data belonging to different ECC words The data input control method and apparatus of the semiconductor memory device.

The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of controlling data input of a semiconductor memory device, comprising: n chunks each consisting of y bits extracted from x ECC words, wherein n and x and y are integers of 2 or more, A step of reading data constituting each of the layers formed in the layer of the semiconductor memory device having a structure in which n layers are stacked, And routing the n chunks of data so that the bits belonging to the ECC word are transmitted.

According to another aspect of the present invention, there is provided a data input control device for a semiconductor memory device, comprising: n chunks each consisting of y bits extracted from x ECC words, wherein n, x and y are integers of 2 or more, A plurality of channels formed in the layer of the semiconductor memory device having a structure in which n layers are stacked are compared with each other in the stacking direction of the layers, And a data processor for routing the n chunks of data so that bits belonging to the other ECC words are transmitted.

According to the embodiment of the present invention, in a semiconductor memory device having a structure in which a plurality of layers are laminated, when inputting that an ECC word is transmitted in a channel of each layer, data belonging to different ECC words Lt; / RTI >

Therefore, even when a continuous channel error occurs in the layer stacking direction when data is transmitted in each layer channel, it can be corrected by an ECC error correction method, and three or more consecutive channel errors It is possible to detect the error through the ECC error correction method. Therefore, the reliability of data transmitted through the channel is increased.

Also, when compared with the conventional art, there is an effect of correcting or detecting a wider range of channel errors, thereby reducing the malfunction due to erroneous data use and the overhead required to recover the erroneous data.

1 is an exemplary diagram of a memory control interface of a semiconductor memory device including a data input control device according to an embodiment of the present invention.
2 is a flowchart illustrating a data input control method of a semiconductor memory device according to an embodiment of the present invention.
3 is an exemplary diagram of a semiconductor memory device to which a data input control method according to an embodiment of the present invention can be applied.
4 is a diagram illustrating a state in which ECC words are dispersed in a plurality of layers in a semiconductor memory device to which a data input control method according to an embodiment of the present invention can be applied.
FIG. 5A is a diagram illustrating a bit position adjustment state of an ECC word according to a data input control method of a semiconductor memory device according to an embodiment of the present invention, and FIG. 5B is an example of an arrangement state of ECC words according to the related art .
FIG. 6 is an exemplary diagram showing data arrangement states of chunks input to four stacked layers according to a data input control method of a semiconductor memory device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions in the embodiments of the present invention, which may vary depending on the intention of the user, the intention or the custom of the operator. Therefore, the definition should be based on the contents throughout this specification.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is an exemplary diagram of a memory control interface of a semiconductor memory device including a data input control device according to an embodiment of the present invention.

The data input control apparatus 100 includes a data read unit 110 and a data processing unit 120. The data input control apparatus 100 receives a plurality of data from the ECC word memory 10, The ECC word is read and then subjected to routing processing so as to be input to each of the channels 21, 22, 23, and 24 of the stacked layers of the semiconductor memory device. For example, the data input control apparatus 100 may be implemented as a memory controller that controls data input and output to and from a memory in a semiconductor memory device.

The data lead unit 110 constitutes n chunks (where n and x and y are integers of 2 or more and y is a multiple of a positive number) each composed of y bits extracted from x ECC words From the ECC word memory 10, as shown in Fig.

The data processing unit 120 may compare the n channels of the ECC words with the n chunks so that the channels formed in the layers of the semiconductor memory device having the n layered structure are compared with other channels adjacent to each other in the layer stacking direction, Lt; / RTI > Here, when the nxy matrix means a logical arrangement of data to be transmitted to the channels, the data processing unit 120 sets data chunks in the data matrix corresponding to the nxy matrix according to the order of the rows (Column) as many as the number of bit-shifted columns.

2 is a flowchart illustrating a data input control method of a semiconductor memory device according to an embodiment of the present invention.

As shown therein, the data input control method includes: n chunks (n, x and y are integers greater than or equal to 2, where x is y or a multiple of y), each of y bits extracted from x ECC words, (Step S201).

In order to transmit data belonging to different ECC words when data transmitted to the channels of the semiconductor memory device are compared with other channels adjacent to each other in the stacking direction of the layers, (Step S203) of positioning data so that chunks of data in the data matrix corresponding to the nxy matrix are arranged in a bit-shifted column by a predetermined number according to the order of the rows .

The data chunks in the data matrix corresponding to the n x y matrix are arranged so as to be located in a column (bit) shifted by a predetermined number according to the order of the rows, (Step S205) of inputting to the channels of the layer.

Hereinafter, a process of inputting an ECC word into a semiconductor memory device according to a data input process by the data input control device according to an embodiment of the present invention will be described in detail with reference to FIG. 1 to FIG.

A semiconductor memory device to which a data input control method according to an embodiment of the present invention can be applied has a structure in which a plurality of layers L1, L2, L3, and L4 are stacked in a vertical direction as in the example of FIG. 3, The layers L1, L2, L3, and L4 have channels through which data is transmitted.

First, the data lead unit 110 of the data input control apparatus 100 transmits a plurality of ECC words stored in the ECC word memory 10 to each of the channels 21, 22, 23, and 24 of the stacked layer of the semiconductor memory device, (S201).

Here, the semiconductor memory device has a structure in which n (n is an integer of 2 or more) layers are laminated, and the data lead section 110 reads out n chunks each consisting of y bits extracted from x ECC words Note that x and y are integers greater than or equal to 2, and y is a multiple of the amount of x).

The data processing unit 120 then causes the channels formed in the layers of the semiconductor memory device having the n-layer stacked structure to transmit bits belonging to different ECC words when compared with other channels adjacent to each other in the layer stacking direction And performs position adjustment on the data constituting the n chunks read out. For example, when an n x y matrix means a logical arrangement of data to be transmitted to channels, data chunks in the data matrix corresponding to the n x y matrix are sequentially shifted by a predetermined number of bits (Step S203).

For example, as shown in FIG. 4, the ECC word is distributed over a plurality of layers, and bits belonging to a plurality of ECC words are gathered in each of the layers L1, L2, L3, and L4 to form one chunk.

FIG. 5A is a diagram illustrating a bit position adjustment state of an ECC word according to a data input control method of a semiconductor memory device according to an embodiment of the present invention. FIG. As shown in the figure, the data processing unit 120 shifts the bits of the ECC word in the nxy data matrix by the different bit positions of the columns according to the order of the rows, So that data belonging to different ECC words are located when compared with adjacent adjacent channels. FIG. 5B is a diagram illustrating an arrangement of ECC words according to the related art. Comparing FIG. 5A with FIG. 5B, the bit shift state by the data processing unit 120 can be more easily confirmed. 5A, 5B and 6, 'O' means 1 bit data, and 1, 2, 3,... , x-3, x-2, x-1, x are the identification numbers of ECC words. That is, the data indicated by x indicates that the data is extracted from the x-th ECC word. Here, y is defined as a multiple of a positive number of x because x and y may be the same number, but one chunk may be composed of x bits, 2x bits, 3x bits, etc. depending on the channel width to be.

Next, the data processing unit 120 obtains n chunks, which are positioned so that the chunks of data in the data matrix corresponding to the n x y matrix are located in a column shifted by a predetermined number according to the order of the rows, And inputs the processed data to the channels 21, 22, 23, and 24 of the stacked layer of the semiconductor memory device (S205).

FIG. 6 is an exemplary diagram showing a data arrangement state of chunks input to four stacking layers L1, L2, L3, and L4 according to a data input control method of a semiconductor memory device according to an embodiment of the present invention. As a result, it can be seen that the chunks input to adjacent layers are compared with each other, and the identification numbers of the ECC words are arranged differently from each other. Unlike the input array of data, the arrangement of data actually stored in each memory of the stacked layers may be the same as in the example of FIG.

As described above, according to the embodiment of the present invention, in the semiconductor memory device having a structure in which a plurality of layers are stacked, when inputting such that the ECC word is transferred in the channel of each layer, Data belonging to the ECC word is routed to be transmitted.

Then, when a channel error occurs in the layer stacking direction when data is transmitted in the channel of each layer, each channel error is distributed to different ECC words.

Therefore, according to the embodiment of the present invention, even if a continuous channel error occurs in the layer stacking direction, that is, in the vertical direction, it can be corrected or detected by an ECC error correction method.

Each block of the block diagrams attached hereto and combinations of steps of the flowchart diagrams may be performed by computer program instructions. These computer program instructions may be loaded into a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus so that the instructions, which may be executed by a processor of a computer or other programmable data processing apparatus, And means for performing the functions described in each step are created. These computer program instructions may also be stored in a computer usable or computer readable memory capable of directing a computer or other programmable data processing apparatus to implement the functionality in a particular manner so that the computer usable or computer readable memory It is also possible for the instructions stored in the block diagram to produce a manufacturing item containing instruction means for performing the functions described in each block or flowchart of the block diagram. Computer program instructions may also be stored on a computer or other programmable data processing equipment so that a series of operating steps may be performed on a computer or other programmable data processing equipment to create a computer- It is also possible that the instructions that perform the processing equipment provide the steps for executing the functions described in each block of the block diagram and at each step of the flowchart.

Also, each block or each step may represent a module, segment, or portion of code that includes one or more executable instructions for executing the specified logical function (s). It should also be noted that in some alternative embodiments, the functions mentioned in the blocks or steps may occur out of order. For example, two blocks or steps shown in succession may in fact be performed substantially concurrently, or the blocks or steps may sometimes be performed in reverse order according to the corresponding function.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

According to the embodiment of the present invention, in a semiconductor memory device having a structure in which a plurality of layers are stacked, when inputting that an ECC word is to be transmitted in a channel of each layer, data belonging to different ECC words Even when a continuous channel error occurs in the layer stacking direction when data is transmitted in a channel of each layer, it can be corrected by an ECC error correcting method, and more than three If a continuous channel error occurs, it can be detected by an ECC error correction method.

The present invention can be used in designing and manufacturing a three-dimensional semiconductor memory device having a structure in which a plurality of layers are stacked.

100: Data input control device
110: Data lead portion
120:

Claims (4)

A data input control method for a semiconductor memory device performed by a data input control device,
(n, x and y are integers greater than or equal to 2, y is a multiple of a positive number) each composed of y bits extracted from x ECC (Error Correction Code) words, Wow,
the n chunks are formed so that bits belonging to different ECC words are transmitted to channels formed respectively in the layers of the semiconductor memory device having the n layer stacked structure when compared with other channels adjacent in the stacking direction of the layer And routing the data to the semiconductor memory device. The method according to claim 1,
when an nxy matrix means a logical arrangement of data to be transmitted to the channels, the data constituting the chunk in the data matrix corresponding to the nxy matrix is bit-shifted by a predetermined number according to the order of the rows Wherein the data is routed so as to be located in a column. (n and x and y are integers of 2 or more, y is a multiple of a positive number), each of which is composed of y bits extracted from x ECC (Error Correction Code) words, A lead portion,
the n chunks are formed so that bits belonging to different ECC words are transmitted to channels formed respectively in the layers of the semiconductor memory device having the n layer stacked structure when compared with other channels adjacent in the stacking direction of the layer And a data processing section for routing the data. The method of claim 3,
when an nxy matrix means a logical arrangement of data to be transmitted to the channels, the data constituting the chunk in the data matrix corresponding to the nxy matrix is bit-shifted by a predetermined number according to the order of the rows Wherein the data input control unit is arranged to be located in a column.

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