JP2002150793A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which influence of a noise caused by simultaneous operation of plural output buffers can be confirmed in a test mode and reliability can be improved. SOLUTION: This semiconductor memory is provided with a normal operation mode and a test mode, and has an output terminal 6, an output buffer 10 corresponding to each output terminal, an output control circuit 1 outputting data to each output buffer, an input terminal 5 for a test mode for inputting a test mode selecting signal, a test mode entry circuit 4 shifting to a test mode, an output terminal 7 for a test mode, and a data compressing circuit 3 reading out data from the output control circuit at the time of test mode and outputting this data from an output terminal for a test mode. In bothe modes of the normal operation mode and the test mode, the output buffer 10 is operated and data from the output control circuit 1 is outputted from the output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a large-capacity random access memory with improved inspection reliability.

[0002]

2. Description of the Related Art In recent years, the progress of high integration of semiconductor integrated circuits has been remarkable, and semiconductor storage devices, especially random access memories (hereinafter, referred to as "RAMs") have been increasing in capacity and increasing in number of bits. . Therefore, when a test is performed by measuring all input / output data in a large-capacity RAM having a multi-bit configuration, the test time increases due to the limitations of the tester. Therefore, in a large-capacity RAM having a multi-bit configuration, the number of I / Os normally used in the test mode (the number of input / output data terminals measured by a tester) is reduced, and the number of I / Os measured (a test per unit time is possible) is reduced. An I / O compression configuration that can shorten the inspection time by increasing the number of semiconductor memory devices) is adopted. Specifically, this is realized by expanding the address space using a test address input pad prepared in the chip in advance and reducing the number of input / output data terminals to perform a test.

FIG. 5 is a block diagram showing a part of a conventional semiconductor memory device. The semiconductor memory device shown in FIG. 5 is a dynamic RAM having a normal operation mode and a test (bit compression test) mode. 13 is an output control circuit. The output control circuit 13 is connected to a sense-up (not shown) constituting the RAM. A circuit 14 is selected during normal operation to output data. Reference numeral 18 denotes a plurality of output terminals for outputting data during normal operation. 21
Are a plurality of output buffers provided corresponding to the plurality of output terminals 18. The plurality of output buffers 21 are shown by one block, and constitute a part of the circuit 14.

Reference numeral 15 denotes a data compression circuit which is selected and operated in the bit compression test mode, 16 denotes a test mode entry circuit which receives a test mode selection signal and performs a test mode entry, and 17 denotes a test mode for inputting a test mode selection signal. Reference numeral 20 denotes a test address input pad.

A test of a semiconductor memory device is performed as follows. First, writing is performed on a plurality of memory cells (not shown) in accordance with a test pattern. Next, when a test mode selection signal is input from the test mode input terminal 17, the test mode entry circuit 16 is operated by this to shift to the test mode.

The test address input pad 20
For example, when “0000 (binary number)” is input to the data compression circuit 15 from (PA0 to PA3), the data compression circuit 15 selects the output terminal DOS0 of the output control circuit 13 assigned to “0000”, and The data from DOS0 is read, and the data is output from the test mode output terminal 19.

At this time, if all the data read from the output terminal DOS0 have the same value, for example, if the data read out from the output terminal
If all signals are at the L level, an output signal at the L level is output from the test mode output terminal 19. On the other hand, if at least one data read from the output terminal DOS0 is different from the other, the data compression circuit 15 outputs the test mode output terminal 19.
In a high impedance state. As a result, the number of I / Os can be reduced, and the test can be facilitated.

[0008]

By the way, especially in a dynamic RAM having a large capacity, the number of output buffers required increases with the increase in the number of bits, so that a large number of output buffers operate simultaneously. Noise is a problem. Therefore, it is also desired to confirm the influence of this noise in the test mode.

However, in the conventional semiconductor memory device shown in FIG. 5, when a test mode selection signal is input, a signal is sent from the test mode entry circuit 16 to the circuit 14, and
The output terminal 18 is opened, and the output buffer 21 is not operating. Therefore, the output terminal (DOS0
.. DOSn), only the signal fixed to L (or H) is output from the output terminal 18 irrespective of the type of signal output from the output terminal 18, resulting in a situation different from the actual operation. For this reason,
The effect of noise due to the simultaneous operation of the plurality of output buffers 21 cannot be confirmed, and there is a problem in that a characteristic difference occurs between the actual operation and the test mode.

An object of the present invention is to provide a semiconductor memory device in which the influence of noise caused by the simultaneous operation of a plurality of output buffers can be confirmed in a test mode and reliability can be improved.

[0011]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device having a normal operation mode and a test mode. A plurality of output terminals for outputting data to the outside of the device, a plurality of output buffers provided corresponding to each output terminal, and at least an output control circuit that outputs data to each output buffer, Each output buffer operates in both the normal operation mode and the test mode to output data from the output control circuit from an output terminal.

A semiconductor memory device according to a second aspect of the present invention is a semiconductor memory device having a normal operation mode and a test mode, and is for outputting data to the outside of the semiconductor memory device. At least a plurality of output terminals, a plurality of output buffers provided corresponding to each output terminal, an output control circuit for outputting data to each output buffer, and a signal generation circuit connected to each output buffer ,
The signal generation circuit outputs an H or L signal from an output terminal via all or some output buffers in a test mode.

Further, in the first and second aspects, a test mode input terminal for inputting a test mode selection signal, and a test for shifting to a test mode in accordance with the input test mode selection signal. It has a mode entry circuit, a test mode output terminal that outputs data in the test mode, and a data compression circuit that reads data from the output control circuit in the test mode and outputs the data from the test mode output terminal. preferable.

As described above, in the semiconductor memory device according to the first and second aspects of the present invention, the output buffer is set to the operating state in a state close to the actual use state even in the test mode, and the output terminal Output data. Therefore, the influence of noise can be confirmed in the test mode, especially in the bit compression test mode, so that the characteristic difference between the actual operation and the test mode can be extremely reduced, and the reliability of the RAM equipped with the bit compression test mode can be particularly improved. it can.

[0015]

(First Embodiment) A semiconductor memory device according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the semiconductor memory device according to the first embodiment of the present invention. In addition,
1, the circuits and terminals shown in FIG. 3 are omitted. FIG. 2 is a diagram showing a unit circuit (memory cell) for storing 1-bit information in the semiconductor memory device of the present invention. FIG. 3 is a block diagram showing a part of the semiconductor memory device according to the first embodiment of the present invention shown in FIG. Figure 1
The semiconductor memory device according to the first embodiment of the present invention shown in FIG. 3 has a normal operation mode and a test mode.

First, a write operation and a read operation in the semiconductor memory device of the present invention will be described with reference to FIGS. In FIG. 1, BL is a bit line for transmitting storage information, and WL is a word line for selecting a cell. Reference numeral 22 denotes an address signal input from the test mode input terminal, and reference numeral 23 denotes an address buffer to which an address is input. Reference numeral 24 denotes a row decoder for selecting a word line specified by a row (X) address, and reference numeral 25 denotes a column decoder for selecting a bit line specified by a column (Y) address. Reference numeral 26 denotes a sense amplifier that detects and amplifies a small signal voltage, and 27 denotes a memory cell array in which memory cells located at a portion where BL and WL intersect are arranged on a matrix. 28 is an output control circuit, 29
Is an input control circuit. In FIG. 2, reference numeral 30 denotes a capacitor element (capacity for storing information: C
s) and 31 are MOS transistors constituting a memory cell.

The semiconductor memory device of the present invention shown in FIGS. 1 to 3 is a dynamic RAM. Therefore, the operation cycle is roughly divided into a precharge period and an active period. A precharge operation is performed before the operation of the memory cell. In the precharge period in which the precharge operation is performed, the bit line BL is initially set (equalized) to a predetermined voltage.

As shown in FIG. 1, when a transition is made from the precharge period to the active period, the address buffer 23 takes in and holds the address signals 22 inputted from the outside and forms an internal address based on these address signals 22. I do. The address signal 22 is further sent to a row decoder 24 and a column decoder 25.

The row decoder 24 decodes the internal X address signal and sets a corresponding word line WL of the memory cell array 27 to a selected state. The column decoder 25 decodes the internal Y address signal supplied from the address buffer 23, and sets the corresponding bit of the bit line BL selection signal to an H level selection state. In the read operation, by selecting the word line WL, a signal voltage corresponding to the information storage capacitance Cs of the capacitor element connected to the memory cell is output to the sense-up 26 via the precharged bit line BL. It is done by being done.

The capacitance Cs of the capacitor element in the memory cell is much smaller than the capacitance of the bit line, and the value of the signal voltage output to the sense-up 26 is small. Therefore, this signal voltage is detected and amplified by the sense amplifier 26 and then output as data via the output control circuit 28.

The write operation is performed by selecting the word line WL of the cell intended to be written in the same manner as the read operation, but the read operation is performed before the write operation because the information of the non-selected cells is destroyed. There is a need.

That is, first, a read operation is performed on all the memory cells on the word line WL, and the cell amplification voltage is temporarily held on each bit line BL. Thereafter, the cell selection switch is turned on, and the information voltage to be written is input to the capacitor element of the selected cell. At this time, the amplified voltage of the non-selected bit line BL is simultaneously rewritten into each cell.

Next, Embodiment 1 of the present invention will be described with reference to FIG.
The normal operation mode and the test mode included in the semiconductor memory device according to the first embodiment will be described. As shown in the example of FIG. 3, the semiconductor memory device according to the first embodiment of the present invention performs a normal operation, and thus requires a plurality of output terminals (DOUT0 to n) 6.
And a plurality of output buffers 10 provided corresponding to the respective output terminals 6, and an output control circuit 1 for outputting data to the respective output buffers 10. The output control circuit 1
Is the output control circuit 28 shown in FIG. 1 and is connected to the sense up. In FIG. 3, the plurality of output buffers 10 are shown as one block, and constitute a part of the circuit 2 for outputting data in the normal operation mode.

In the normal operation mode, when the signal detected and amplified by the sense-up is input to the output control circuit 1, the output control circuit 1 outputs its output terminals (DOS0 to DO).
Sn), the input signal is output as data to each output buffer 10, and each output buffer 10 outputs the corresponding signal to each output terminal 6.

In the semiconductor memory device shown in FIG. 3, a test mode input terminal 5 for inputting a test mode selection signal for performing a bit compression test in the test mode.
A test mode entry circuit 4 for shifting to a test mode according to the input test mode selection signal;
A test mode output terminal 7 for outputting data in the test mode, a data compression circuit 3 which operates in the test mode to read data from the output control circuit 1, and outputs this data from the test mode output terminal 7; Address input pad 8.

The transition to the test mode is performed by first inputting a test mode selection signal for selecting the test mode from the test mode input terminal 5 and operating the test mode entry circuit 4. Here, for example, “00” is input by a test address input pad (PA0 to PA3).
01 (binary number) ", the data compression circuit 3 selects the output terminal DOS1 of the output control circuit 1 assigned to" 0001 ", reads data from the output terminal DOS1, and outputs the test mode output terminal. 7 outputs data.

At this time, in the case of the conventional semiconductor memory device, as shown in FIG.
To the circuit 2 and the data output from all the output terminals 6 is fixed at L (or H), which is different from the actual operation. However, Embodiment 1 shown in FIG.
In the semiconductor memory device according to (1), no signal is sent from the test mode entry circuit 4 to the circuit 2, so that the output buffer 10 operates also in the test mode, and the output terminal of the output control circuit 1 as in the normal operation mode. (DO
S0 to DOSn) are output from the output terminal 6. That is, in the semiconductor memory device of the present invention shown in FIG.
0 are simultaneously in the operating state, which is the same as the actual operation.

As described above, according to the semiconductor memory device of the first embodiment of the present invention, the plurality of output buffers 10 operating in the actual use state are set to the operation state even in the test mode, and Can be output. For this reason, according to the semiconductor memory device according to the first embodiment of the present invention, it is possible to confirm the influence of noise at the time of actual operation, and to eliminate a characteristic difference from the actual operation.

(Second Embodiment) Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a part of the semiconductor memory device according to the second embodiment of the present invention.

As shown in FIG. 4, Embodiment 2 of the present invention
The semiconductor memory device according to the first embodiment also has a normal operation mode and a test mode similarly to the semiconductor memory device according to the first embodiment shown in FIG. The semiconductor memory device according to the present embodiment has a signal generation circuit 9 connected to each output buffer 10, and is otherwise configured similarly to the semiconductor memory device according to the first embodiment.

The signal generation circuit 9 includes a circuit for generating an H or L signal in a test mode, and a decoding circuit for outputting the generated H or L signal to an output buffer 10 arbitrarily selected. I have. Therefore, the signal generation circuit 9 can output the H or L signal from the output terminal 6 via all or some of the output buffers 10 in the test mode.

Also in the semiconductor memory device according to the present embodiment, since no signal is sent from test mode entry circuit 4 to circuit 2, output buffer 10 operates in the test mode. Therefore, when the signal generation circuit 9 is not operated, the data output from the output terminals (DOS0 to DOSn) of the output control circuit 1 is output from the output terminal 6, as in the semiconductor memory device shown in FIG.

However, in the semiconductor memory device according to the present embodiment, since the signal generating circuit 9 is provided, the content of the data output from the output terminal 6 can be freely controlled. Therefore, for example, data can be output with a maximum load equal to or higher than the standard, and the effect of noise can be confirmed at this time, so that the reliability of the semiconductor memory device can be further improved.

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the examples described in the first and second embodiments, and various changes can be made without departing from the gist of the present invention. It is possible. In the above first and second embodiments, the case where the semiconductor memory device is a dynamic RAM has been described, but the present invention is not limited to this. The semiconductor memory device of the present invention is not particularly limited as long as it has a test mode of, for example, a static RAM or the like, particularly a bit compression test mode.

[0035]

As described above, in the semiconductor memory device of the present invention, an output buffer which does not operate in the test mode in the past can be operated in the actual use state even in the test mode. Can output data. Therefore, the effect of noise can be confirmed in the test mode as in the actual use state, so that a semiconductor memory device with improved reliability as compared with the related art can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a unit circuit (memory cell) for storing 1-bit information in the semiconductor memory device of the present invention.

FIG. 3 is a block diagram showing a part of the semiconductor memory device according to the first embodiment of the present invention shown in FIG. 1;

FIG. 4 is a block diagram showing a part of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a part of a conventional semiconductor memory device;

[Explanation of symbols]

Reference Signs List 1 output control circuit 2 circuit for outputting data in normal operation mode 3 data compression circuit 4 test mode entry circuit 5 input terminal for test mode 6 plural output terminals 7 output terminal for test mode 8 test address input pad 9 Signal generation circuit 10 Multiple output buffers

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G11C 11/401 G11C 11/34 371A (72) Inventor Naoki Kuroda 1006 Odakadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 2G032 AA07 AK14 AK15 AL00 5B024 AA15 BA29 CA07 EA01 EA04 5L106 AA01 AA02 DD04 DD12 EE03 FF05 GG05 GG07

Claims (3)

[Claims] 1. A semiconductor memory device having a normal operation mode and a test mode, wherein a plurality of output terminals for outputting data to the outside of the semiconductor memory device are provided, corresponding to each output terminal. A plurality of output buffers, and at least an output control circuit that outputs data to each output buffer, and each output buffer operates in both the normal operation mode and the test mode to output data from the output control circuit. A semiconductor storage device characterized by outputting from an output terminal. 2. A semiconductor memory device having a normal operation mode and a test mode, comprising: a plurality of output terminals for outputting data to the outside of the semiconductor memory device; and a plurality of output terminals provided corresponding to each output terminal. At least a plurality of output buffers, an output control circuit for outputting data to each output buffer, and a signal generation circuit connected to each output buffer, wherein the signal generation circuit is H or L in a test mode.
A semiconductor memory device that outputs the signal from an output terminal via all or some output buffers. 3. A test mode input terminal for inputting a test mode selection signal, a test mode entry circuit for shifting to a test mode in accordance with the input test mode selection signal, and a test for outputting data in the test mode. 2. A mode output terminal, and a data compression circuit for reading data from an output control circuit in a test mode and outputting the read data from the test mode output terminal.
Or the semiconductor memory device according to 2.