KR970000330B1 - Semiconductor memory apparatus - Google Patents

Abstract

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Description

Refresh function semiconductor memory device

1 is a block diagram showing a first embodiment of a memory device according to the present invention;

FIG. 2 is a block diagram showing a memory block of the storage device of FIG.

3 is a circuit diagram of a sense amplifier power supply control circuit used in the memory device of FIG.

4 is a circuit diagram of a sense amplifier used in the memory device of FIG.

5 is a block diagram showing the time in the conventional memory device and the memory device of FIG.

Fig. 6 is a block diagram showing write / read time and refresh overhead time in the second embodiment and the conventional storage device.

7 is a block diagram showing a third embodiment of the semiconductor memory device according to the present invention;

8 is a block diagram showing a memory block of the storage device of FIG.

FIG. 9 is a circuit diagram of a sense amplifier power supply control circuit used in the memory device of FIG.

10 is a graph showing the amount of current flow in the conventional memory device and the first to third embodiments.

11 is a block diagram showing a fourth embodiment of the semiconductor memory device according to the present invention.

Fig. 12 is a block diagram showing time in the conventional storage device and the fourth embodiment.

13 is a timing chart of a refresher operation.

14 is a circuit diagram showing memory cells in a DRAM.

15 is a block diagram of a conventional DRAM.

FIG. 16 is a block diagram showing a memory block of the conventional DRAM shown in FIG.

17 is a block diagram showing refresh overhead time in a conventional DRAM.

18 is a block diagram showing a refresh time in a conventional video memory.

19 is a block diagram showing a conventional DRAM.

20 is a circuit diagram showing a leaf termination signal generating circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an improved refresh function for reducing the time required for refreshing.

Currently, dynamic lang (hereinafter referred to as DRAM) is used as a semiconductor memory device having the largest memory capacity, and its density is on the rise. In a DRAM, data is stored in a memory cell using the capacity. Because of this principle of holding data in memory cells, memory cells must be refreshed. If the memory cell is not refreshed, the data stored in the memory cell is destroyed. In addition, since the time period for performing the refresh is extended to improve the density of the DRAM, it is required to shorten the time required for the refresh. This time period is then referred to as the refresh overhead time.

The refresh operation in the memory cell will be described with reference to FIGS. 13 and 14. 14 shows a memory cell MA, a sense amplifier SA, a word line W, a pair of bit lines b and b, and a sense amplifier control circuit PLC. When the word line is operated, the data stored in the memory cell MA is read into the bit line pairs b and / b, and the sense amplifier SA is operated to amplify the read data. Then, the amplified data is written back into the memory cell M, thereby completing the refresh. In this method, since refresh is performed for each memory cell MA connected to the word line, the length of the refresh overhead time depends on the number of word lines.

15 to 18, the refresh operation in the conventional semiconductor memory device will be described in more detail. The memory device shown in FIG. 15 includes an input / output device (I / O), a pair of data lines (D, / D), a memory block (MB), a row decoder control circuit (ROC), a column decoder control circuit (COC), and a row. It consists of a decoder control line (RA), a column decoder control line (CA) and a control line for the sense amplifier power supply control circuit (PLCL). The internal structure of the DRAM is shown in detail in FIG. In FIG. 16, CD is a column decoder, ROW is a row decoder, PLC is a sensing amplifier power supply control circuit, SA ₁ to SA _n is a sensing amplifier, SW ₁ to SW _n is a switching element, SWC ₁ to SWC _n is a switching element control The lines, b ₁ to b _n and / b ₁ to / b _n, are non-paired pairs PL ₁ for the first sense amplifier power line, PL ₂ for the second sense amplifier power line, and W ₁ to W _n for the word line, respectively. .

In the DRAMs shown in Figs. 15 and 16, the memory is continuously executed from one of the memory cells MA connected to the word line W ₁ to one connected to the word line W _{n at a} predetermined unit time. Data is continuously rewritten in the cell. However, as the density of DRAM increases, the refresh overhead time becomes longer, resulting in a shorter time period for reading and writing data. In particular, when one of the two storage devices to be compared is four times larger than the other in terms of memory capacity, the refresh overhead time of the storage device having the large storage capacity is the refresh overhead time of the small storage device ( four times longer than a)). Especially in a special type of DRAM such as a video memory, since all the data in the memory cells must be read out and written in sequence, it becomes impossible to access all the memory cells while the memory cells hold those data, thereby reducing the refresh time. This results in a result that must be provided as shown in 18 degrees (b). If the DRAM has a small memory capacity, it is not necessary to provide such processing overhead time (Fig. 18 (a)).

As the density of DRAMs improves, the number of memory cells increases, resulting in a longer refresh overhead time not used for write and read operations. In order to alleviate this problem, the number of refreshes is reduced in highly integrated DRAM. This can be realized by improving the performance of the memory cell, that is, extending the data holding time of the memory cell. However, in view of the recent progress in the degree of integration, it is almost impossible to improve the performance of memory cells, and therefore, it is desired to shorten the refresh overhead time.

Typically, a memory cell in a DRAM is divided into several blocks as shown in FIG.

The DRAM of FIG. 19 is composed of a row address decoder 201 for decoding an external address signal, a refresh address counter 202 for generating a refresh address, an address change circuit 209 and memory blocks MB _A and MB _B. It is. The memory block MB _A includes a memory cell unit 203 and a sense amplifier 205. The other memory block MB _B includes a memory cell unit 204 and a sense amplifier 206. The address change circuit 209 changes the external address signal and the internal refresh address in accordance with the refresh request signal provided when the refresh is executed.

The row address decoder 201 decodes the external address signal, and the write / read address is input to the address change circuit 209. The refresh address signal counter 20 generates an internal refresh address signal and provides it to the address change circuit 209. In accordance with the refresh request signal, the address change circuit 209 converts the write / read address and the internal refresh address. In the write / read cycle, the address change circuit 209 only outputs the write / read address. This generates a corresponding word line in one memory block to operate, and the potential change is amplified by the sense amplifier to read or write the memory cell. When the word lines of a memory block (MB _A) is operated by a read or write is performed in the memory blocks (MB _A), because the address word lines in the other memory block (MB _B) not operate the refresh address is not performed. When the refresh is to be executed, the refresh address counter 202 outputs an internal refresh address through the address change circuit 209. Then, the word lines of the two memory blocks MB _A and MB _B are operated at the same time, so that the potential change on the word lines is amplified to refresh the memory cells of the address. The memory cells connected to one word line of two memory blocks MB _A and MB _B are amplified so as to be refreshed. After the refresh of the memory cells connected to one word line of the two memory blocks MB _A and MB _B is finished, the refresh address of the refresh address counter 202 is converted, and the refresh of the memory cells with respect to the new refresh address is performed. Is executed. In this way, all memory cells in the memory blocks MB _A and MB _B are refreshed in sequence.

In a conventional DRAM, when a memory block is written or read out, row address refreshes of other memory blocks in the DRAM cannot be executed. Therefore, the refresh overhead time is required for all word lines to refresh the connected memory cells, thereby reducing the time for writing and reading.

The semiconductor memory device of the present invention, which overcomes various drawbacks of the prior art, comprises a memory cell arranged in a matrix form, a pair of bit lines for selecting an open address of the memory cell, and a row address for selecting the memory cell. A plurality of memory blocks comprising a word line, a sense amplifier, and a sense amplifier control circuit for controlling the sense amplifier; Control means for controlling the word lines of all the memory blocks in common, selection means for selecting one or more blocks required for write and read operations in the memory block, and executing read and write operations in the selected memory block. And first process means for performing the refresh operation on the unselected memory block.

In a preferred embodiment, the sense amplifier control circuit comprises a first portion for writing or reading and a second portion for refreshing, the first portion being used for writing and reading operations and the second portion for a refresh operation. Used for

The semiconductor memory device of the present invention comprises a memory cell arranged in a matrix form, a pair of bit lines for selecting an open address of the memory cell, a word line for selecting a row address of the memory cell, a sense amplifier, A plurality of memory blocks composed of a sense amplifier control circuit for controlling the sense amplifiers; And control means for controlling the word lines of all the memory blocks in common, and process means for simultaneously executing a refresh operation in all the memory blocks.

In a preferred embodiment, the sense amplifier control circuit comprises a first portion for writing or reading and a second portion for refreshing, the first portion being used for write and read operations and the second portion for the refresh operation. Used.

The semiconductor memory device of the present invention comprises a plurality of memory blocks composed of memory cells arranged in a matrix form; Means for selecting one or more blocks required for write and read operations in the memory block, process means for performing write and read operations in the selected memory block, and refresh in an unselected memory block during the time of the write and read operation. Refresh means for executing an operation, memory means for storing an address of a memory cell refreshed during the time of the write and read operation in the memory block, and the time of the write and read operation based on the stored address And other selection means for selecting memory cells that have not been refreshed in the meantime, and other refresh means for refreshing the selected memory cells within a time set for refreshing.

In a preferred embodiment, the storage device further comprises signal means for generating a signal indicating that all the selected memory cells have been refreshed by the end of the time.

Accordingly, the present invention described herein provides (1) a semiconductor memory device having a reduced refresh overhead time, (2) a semiconductor memory device in which a refresh overhead time is not required, and (3) a write or read. It is possible to provide a semiconductor memory device having an extended time for the purpose, and (4) to provide a semiconductor memory device in which an increase in current level is suppressed.

Various objects and advantages of the invention will be apparent to those skilled in the art by reference to the accompanying drawings.

Example 1

A first embodiment of the present invention will be described with reference to FIGS.

This embodiment is a semiconductor memory device useful for a video memory.

1 shows an external block of a storage device. The memory device of FIG. 1 includes an input / output device (I / O), a pair of data lines (D, / D), four memory blocks (MB _A to MB _D ), a row decoder control circuit (ROC), and a column decoder control circuit. (COC), hang address bus (RA), open address bus (CA), and control lines for sense amplifier power supply control circuit (PLCL). Each memory block MB _A to MB _D is connected with one control line of the open address bus CA, m control lines of the row address bus RA common to each block, and a control line PLCL. have. The open dress bus CA includes all of the control lines 4L. The open address bus CA delivers the output of the column decoder control circuit COC, and the row address bus RA delivers the output of the row decoder control circuit ROC. The memory blocks MB _A to MB _D are connected to the input / output device I / O through the data line pairs D and / D.

The memory blocks MB _A to MB _D have a structure as shown in FIG. 2 and include a column decoder CO, a row decoder ROW, a sense amplifier power control circuit PLC, and a sense amplifier SA ₁ ~. SA _n ), switching elements CW ₁ to CW _n , switching element control lines SWC ₁ to SWC _n , bit line pairs b ₁ to b _n , / b ₁ to b _n , and word lines W ₁ to W _n ), the first power line PL ₁ and the second power line PL ₂ . The bit line pairs b ₁ to b _n and / b ₁ to b _n are arranged to vertically intersect the word lines W ₁ to W _n . The memory cell MA is disposed at the intersection point. A row decoder (ROW) controls the word line (W ₁ ~ W _n), selects one of the word lines (W ₁ ~ W _n). Bit line pair _{(b 1 ~ b n, /} b 1 ~ b n) is a sense amplifier coupled to the input of a (SA ₁ ~ SA _n), the sense amplifier output is a column decoder (CO) a (SA ₁ ~ SA _n) Are connected to the data line pairs D and / D through the switching elements SW ₁ to SW _n controlled by the output control lines SWC ₁ to SWC _n . The sensing amplifier power control circuit PLC controls the sensing amplifiers SA ₁ to SA _n through the first and second power lines PL ₁ and PL ₂ .

3 shows a sense amplifier power control circuit (PLC). When the state of the signal line PLCL for the control circuit PLC becomes high (H), since the MOS transistors MP ₃ and MN ₃ are turned on, power is supplied to the power lines PL ₁ and PL ₂ . IV1 in FIG. 3 is an inverter. The sensing amplifiers SA ₁ to SA _n have the structure shown in FIG. 4 and are composed of four MOS transistors MP ₁ , MP ₂ , MN ₁ , MN ₂ . When power is supplied to the power lines PL ₁ and PL ₂ , the sensing amplifiers SA ₁ to SA _n are activated to detect data read from the bit line pairs b ₁ to b _n and / b ₁ to b _n . do.

The operation of the storage device of FIG. 1 will be described. As described above, the storage device of FIG. 1 is a video memory which is sequentially accessed so that data stored in all memory cells can be written or read out. For example, when the memory block MBA is selected to be written or read out, the remaining memory blocks MB _B to MB _D are refreshed. Since the signal of the row address bus (RA) and control signal line (PLCL) they are connected in common to all the memory blocks (MB _A ~ MB _D), power supply control of the memory block (MB _A ~ MB _D) circuit (PLC) And row decoder ROW are controlled in common, and word lines W _m having an address common to the memory blocks are selected in all the memory blocks MB _A to MB _D. When the sense amplifiers SA ₁ to SA _n are activated, when the memory blocks MB _A to MB _D are activated, the memory cells connected to the word lines W _m having addresses in the memory blocks MB _A to MB _D The data stored in the read-out bit line pairs b ₁ to b _n and / b ₁ to bn are sensed and amplified. Of the amplified data, only data of the memory block MB _A is transferred to the data line pairs D and / D through the switching elements SW ₁ to SW _n , and the data of the remaining memory blocks MB _B to MB _{D are} transferred. The data is rewritten to the original memory cells respectively (that is, refreshing of the memory blocks MB _B to MB _D is performed).

In this way, the refresh of the memory blocks MB _B to MB _D is automatically executed while the memory blocks MB _A perform writing and reading. This is schematically shown in (c) of FIG. In Fig. 5, (a) shows the time in a conventional storage device having a small storage capacity, and (b) shows the time in a conventional storage device having a large storage capacity (4 times the memory capacity of a small DRAM). Indicates the time. As shown in FIG. 5, in the conventional large memory device shown in (b), a refresh overhead time is required. On the contrary, according to this embodiment, data can be rewritten without a refresh overhead time. According to the present invention, it is not necessary to provide a refresh overhead time even if the storage capacity or the number of memory blocks is increased.

Example 2

This embodiment is a DRAM having a structure similar to that of the embodiment of FIG. 1, but is designed such that all memory blocks MB _A to MB _D are refreshed at the same time. Therefore, in this structure, the refresh is executed for four bundled word lines. This means that the number of word lines is obviously reduced by a quarter. Although the DRAM of this embodiment has a storage capacity four times that of a conventional small DRAM (Fig. 6 (a)), the refresh overhead time of this embodiment (Fig. 6 (c)) is a conventional large DRAM. Since it is not increased as shown in (b) of FIG. 6, there is no need to reduce the recording / reading time in the unit time, and there is no need to reduce the number of refresh operations. As a result, it is possible to reduce conditions such as holding time to be considered in designing DRAM.

In other words, according to this embodiment, the refresh overhead time can be shortened by increasing the number of memory blocks, which can be expressed as follows.

Refresh time = Total word lines / blocks x Refresh time for one word line

Example 3

7 shows a third embodiment of the present invention. In the above structure of the first embodiment, when all four memory blocks are operated at the same time, that is, one word line and a sense amplifier are driven in each memory block, as compared with the conventional memory device as shown in FIG. The current is increased four times. This increased current is a problem in itself, causing malfunctions due to voltage drop in the power line, reducing performance, and adversely affecting the design of power circuits such as downconverters. The embodiment of FIG. 7 can eliminate this problem.

In the memory device of FIG. 7, the control lines PLCL _A to PLCL _D are connected to the sense amplifier power control circuits PLC of the memory blocks MB _A to MB _D , respectively, and for the sense amplifier power control circuits PLC. The refresh control line (RPLCL _A ~ RPLCL _D ) of is further provided. As shown in FIG. 9, each sense amplifier power supply control circuit PLC includes a write / read section PLCA connected to one of the control lines PLCL _A to PLCL _D and a refresh control line RPLCL _A to RPLCL. _D ) is divided into a refresh portion (PLCB) connected to one of them. The write / read portion (PLCA) is composed of a P-channel MOS transistor (MP ₄ ), an N-channel MOS transistor (MN ₄ ), and an inverter (IV ₂ ), and the refresh portion (PLCB) is a P-channel MOS transistor (MP ₅ ), N. It consists of a channel MOS transistor MN ₅ and an inverter IV ₃ .

The operation of the storage device of FIG. 7 will be described with reference to the case where the storage device is used as the video memory in which the memory cells are sequentially accessed. For example, the memory blocks MB _A are selected to be written or read, and the remaining memory blocks MB _B to MB _D are selected to be refreshed. In the memory block MB _A , a write / read portion PLCA is used. As shown in FIG. 8, a single word line W _n is connected to a plurality of memory cells MA. Since the memory cells MA connected to the single word line W _n in the memory block MB _A are continuously accessed, sufficient time is sufficient to access all the memory cells MA connected to the single word line W _n . Required. In contrast, refreshes are executed simultaneously on the memory cells MA connected to a single word line W _n . Therefore, in the memory blocks MB _A to MB _D , the refresh can be performed slowly while the memory cells MA of the memory blocks MB _A are continuously accessed, so that the sense amplifier power supply control circuit PLC is designed to be compact. I can do it. As a result, as shown in FIG. 10, the current or power consumption of the present embodiment can be reduced as compared with the memory device of FIG.

In the sense amplifier power supply control circuit PLC, the transistors MP ₅ and MN ₅ of the refresh portion PLCB are occupied by a relatively small area compared to the transistors MP ₄ and MN ₄ of the write / read portion PLCA. By design, the current flow in the refresh is suppressed. The load / capacity caused by the data pairs (D, / D) connected to the sense amplifiers SA ₁ to SA _n must be charged with the sense amplifier within a unit time, so that the transistors MP of the write / read section PLCA ₄ , MN ₄ ) needs to be configured to a rather large size.

As described above, according to the present embodiment, power consumption can be suppressed even when a plurality of memory blocks are simultaneously refreshed.

Example 4

11 shows a DRAM according to the present invention. The DRAM of FIG. 11 includes two memory blocks MB _A and MB _B , and also generates a row address decoder 101 for decoding an external address signal, and generates an internal refresh address for the memory block MB _A. for the first refresh address counter 111, a memory block (MB _B) a second refresh address counter 112 and the address change circuit 109 for generating an internal refresh address for further provided. The memory block MB _A includes a memory cell unit 103 and a sense amplifier 105. Another memory block MB _B includes a memory cell unit 104 and a sense amplifier 106. The address change circuit 109 converts the internal refresh address according to the refresh request signal when the refresh rate is performed with the external address signal. 113 is a refresh end signal generation circuit for outputting a refresh end signal indicating completion of refresh of all blocks in accordance with signals from the refresh address counters 111 and 112. FIG. A circuit diagram of such a refresh end signal generating circuit 113 is shown in FIG.

The refresh operation in the DRAM of FIG. 11 will be described. When data is written or read out from the memory block MB _A , the row decoder 101 decodes the external address signal, and the decoded external address signal is supplied to the address change circuit 109. An address change circuit 109 is hameuroseo outputs a write or read address to activate the word line corresponding to the memory block (MB _A), a write or read is executed in the memory block (MB _A). At the same time, the refresh address counter 112 outputs the internal refresh address to the memory block MB _B in a predetermined sequence through the address change circuit 109. A refresh in the memory block (MB _B) a write or read is executed in the memory block (MB _A) during the Run. On the other hand, when data is written or read out from the memory block MB _B , the row decoder 101 decodes the external address signal, and the decoded external address signal is supplied to the address change circuit 109. An address change circuit 109 outputs the stand because the write or read address to a word line corresponding to the memory block in the (MB _B) operation, the memory block (MB _B) the recording or reading running on. At the same time, the refresh address counter 112 outputs the internal refresh address to the memory block MB _A in a predetermined sequence through the address change circuit 109. Therefore, the refresh in the memory block (MB _A) a write or read is executed in the memory block (MB _B) during the Run.

According to this embodiment, since writing or reading is performed in another memory block while one memory block is refreshed, each refresh address counter 111 and 112 stores the address of the corresponding memory block to be refreshed. According to the address stored in each refresh address counter, memory cells that were not refreshed in the write or read operation are refreshed at the refresh overhead time. Therefore, the refresh overhead time can be reduced because it is not necessary to refresh all the memory cells during the refresh overhead time.

In Fig. 12, (a) shows a refresh overhead time for a conventional DRAM, and (b) shows a refresh overhead time for this embodiment. Reference numerals 114 and 116 denote time periods for writing or reading the conventional DRAM and this embodiment, and reference numerals 115 and 117 denote refresh overhead times in the conventional DRAM and this embodiment, respectively. As shown in FIG. 12 (a), in the conventional DRAM, the refresh overhead time 115 is constant and relatively long because refresh is performed for all memories during the refresh overhead time 115. In contrast to this, according to this embodiment, it is not necessary to refresh all the memory cells during the refresh overhead time 117. Therefore, the refresh overhead time 117 is not constant, which is shorter than the refresh overhead time 115 of the conventional DRAM. As a result, according to this embodiment, it is possible to increase the time for writing and reading.

When the refresh for all memory cells in the memory block is completed within the refresh overhead time, the refresh address counters 111 and 112 corresponding to the memory block finishes displaying the memory block refresh end signal indicating that the refresh of all memory cells in the memory block is completed. Output to the signal generating circuit 113. Therefore, as shown in FIG. 20, after receiving the refresh end signals of the memory blocks from all the refresh address counters (i.e., 111 and 112), the refresh end signal generating circuit 113 indicates that the refresh ends indicating that all the memory cells have been refreshed. Generate a signal. Therefore, the refresh end signal is output to the outside of the chip through the pin, and an external device such as the CPU detects the refresh end signal, so that the process can be executed smoothly without time loss during the write / read operation.

In the embodiment of FIG. 11, two memory blocks are provided, but the number of memory blocks can be freely selected in the present invention.

According to this embodiment, since the memory cells of one or more memory blocks not selected for writing or reading are refreshed simultaneously with the writing or reading of memory cells of another memory block selected for writing or reading, the refresh overhead time is shortened. When the refresh overhead time is not zero, the memory overhead of another memory block that has not been refreshed at the write / read time is refreshed using the storage address of the memory cell, thereby reducing the refresh overhead time. On the other hand, the use efficiency of DRAM is effectively improved by shortening the time during which the write / read operation is not performed.

It will be understood that various modifications of the invention are readily possible by those skilled in the art without departing from the scope of the invention. Accordingly, the appended claims are not intended to be limited to the description set forth but rather to include all features of patentable novelty in the invention, including all features that would be treated equally by those skilled in the art. Should be interpreted as

Claims (6)

A memory cell MA arranged in a matrix form, a pair of bit lines bm and bm for selecting an open dress of the memory cell, a word line Wm for selecting a row address of the memory cell, and a sense amplifier A plurality of memory blocks MB including SAm and a sense amplifier control circuit PLC for controlling the sense amplifier; Control means (ROC) for controlling the word lines of all the memory blocks; Selection means (COC) for selecting one or more blocks required for writing and reading among the memory blocks; First process means for performing write and read operations in the selected memory block and second process means for performing a refresh operation in an unselected memory block, the sense amplifier control circuitry comprising: a first for write or read operation; A refresh function-enhanced semiconductor memory comprising a portion (PLCA) and a second portion (PLCB) for refreshing, wherein the first portion is used for write and read operations and the second portion is used for refresh operations. Device. A memory cell MA arranged in a matrix form, bit line pairs bm and bm for selecting an open address of the memory cell, a word line pair Wm for selecting a row address of the memory cell, A plurality of memory blocks MB comprising a sense amplifier SAm, a sense amplifier control circuit PLC for controlling the sense amplifiers, control means ROC for controlling the word lines of all the memory blocks; Selecting means (COC) for selecting one or more blocks required for writing and reading among the memory blocks; First process means for executing write and read operations in the selected memory block and second process means for concurrently executing refresh operations in all the memory blocks, wherein the sense amplifier control circuitry is configured for writing or reading. A refresh function-enhanced semiconductor memory comprising a portion (PLCA) and a second portion (PLBB) for refreshing, wherein the first portion is used for write and read operations and the second portion is used for refresh operations. Device. A plurality of memory blocks MB composed of memory cells MA arranged in a matrix form; Selection means (COC) for selecting one or more blocks required for write and read operations in the memory block; Processing means 101, 109, 105 (or 106) for executing write and read operations in the selected memory block; refresh means 112 (or 111) for executing refresh operations in an unselected memory block within the time of the write and read operation. 106 (or 105); memory means (111, 112) for storing an address of a memory cell refreshed within the time period of the write and read operation in the memory block; Refresh selection means for selecting a memory cell not refreshed within the time period of the read operation and other refresh means for refreshing the selected memory cell within the time set for refreshing Semiconductor memory. The semiconductor memory device according to claim 1, wherein the memory device further comprises a signal means (113) for generating a signal indicating that the end of the time has been refreshed of all the selected memory cells. . The semiconductor memory device of claim 2, wherein a current level for driving the second portion (PLCB) is smaller than a current level for driving the first portion (PLCA). The semiconductor memory device of claim 2, wherein a current level for driving the second portion (PLCB) is smaller than a current level for driving the first portion (PLCA).

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