JP2574444B2 - Semiconductor storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device.

2. Description of the Related Art At present, a dynamic RAM (hereinafter, DRAM) is used as a semiconductor memory device having the largest storage capacity, and further higher integration is required. Due to the structural problem of the memory cell, which is the main part of the DRAM, if the refresh operation is not performed, the stored data will be lost, and the refresh will be performed with the high integration of the DRAM. As the time is getting longer, shortening the refresh time is an important issue.

The refresh operation of the DRAM will be briefly described with reference to FIGS. FIG. 11 is a timing chart of a DRAM refresh operation, and FIG. 12 is a circuit diagram of a DRAM memory cell and its periphery. MA is a memory cell, an SA sense amplifier, W is a word line, b, is a bit line pair, PLC is a sense amplifier control circuit, and PLCL is a sense amplifier control circuit control signal line. As shown in FIG. 11, when the word line W rises and the data of the memory cell MA is read to the bit line pair b, the sense amplifier SA is activated, and the data read on the bit line pair b is amplified. Is done. The amplified data is written into the memory cell MA again, and the refresh of the DRAM ends. As described above, the refresh operation is performed on the word line W.
Is performed for each memory cell MA connected to the memory cell MA, the refresh time becomes shorter as the number of word lines decreases.

FIG. 13, FIG. 14, FIG. 15, and FIG.
This will be described with reference to FIG. FIG. 13 shows a DRAM according to the prior art.
FIG. 14 is a circuit diagram in a memory block of a conventional DRAM, and FIG. 15 is a diagram comparing a refresh time ratio depending on a storage capacity of the DRAM according to the conventional technology.
FIG. 16 is a diagram comparing the timing of performing writing / reading and refreshing of the image memory according to the conventional technique with the magnitude of the storage capacity of the image memory.

1/0 is an input / output circuit, D, is a data line pair, MB _A to _D are memory blocks, ROC is a row decoder control circuit, COC is a column decoder control circuit, RA is a row decoder control signal line, CA is a column decoder control signal lines, PLCL sense amplifier power control circuit control signal line, CO is a column decoder, rOW row decoder, PLC sense amplifier power control circuit, SA ₁ ~ _n the sense amplifier, SW ₁ ~ _n switch elements, SWC ₁ To _n are switch element control lines, b ₁ to _n , ▲ ▼ to _n are bit line pairs,
PL ₁ is first sense amplifier power supply line, PL ₂ is a second sense amplifier power supply line.

Figure 13, refresh the DRAM shown in FIG. 14, and sequentially performed from the memory cell MA, which is connected to the word line W ₁ until the memory cell MA, which is connected to a word line Wn, which within a unit time To keep the data in the memory cell. However, as shown in FIG. 15, when the storage capacity is increased, the time for performing the refresh becomes longer, and the time for actually reading and writing the data becomes shorter. That is, in FIG. 15 (1. Conventional example)
With a storage capacity four times as large as that of (2. Conventional example), the refresh time is also required four times, and the reading and writing time is shortened accordingly. In particular, memories that write and read all memory cells sequentially, such as image memory, which is a special type of DRAM, always write and read all memory cells. As shown in (1. Conventional example), there is no need to provide a time for refreshing, but when the storage capacity increases, the time during which the memory cell can hold data as shown in (2. Conventional example) Since it becomes impossible to access all the memory cells within the memory, it is necessary to provide a time for performing refreshing.

Problems to be Solved by the Invention As described above, as the number of memory cells increases as the degree of integration of DRAMs increases, the useless refresh time from the outside becomes longer. To alleviate this, the number of refreshes is reduced as the degree of integration increases, but this is realized by improving the performance of the memory cell, that is, by increasing the data retention time of the memory cell. However, with the recent progress of high integration, it has become impossible to further improve the performance of the memory cell. Therefore, a device for shortening the refresh time is required. Especially for memories that sequentially access all data in memory cells, such as image memories, if the storage capacity was small, all memory cells could be accessed within the time that the memory cells could hold data. When the storage capacity becomes large, it becomes impossible to access all the memory cells within a time period in which the memory cells can hold data, so that it is necessary to perform refresh.

An object of the present invention is to provide a semiconductor memory device such as an image memory which does not need to be refreshed even when the storage capacity is increased, and a semiconductor memory such as a DRAM which has a short refresh time even when the storage capacity is increased. It is to provide equipment.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of memory cells arranged in a matrix, a plurality of word lines for selectively driving these memory cells, and a plurality of memory cells. A memory array portion in which a plurality of pairs of bit lines for exchanging information between the memory cells are arranged; a row decoder circuit for selecting the word lines; a column decoder circuit for selecting the bit line pairs; Of a sense amplifier control circuit having a sense amplifier circuit for detecting a potential difference between the current supply source, a write / read current supply source, and a refresh current supply source having a lower current supply capability than the write / read current supply source. Are provided, and some of the blocks activated simultaneously are blocks for writing and reading, and the remaining blocks are The block is a block that performs refreshing. The block that performs writing and reading uses the current supply source for writing and reading, and the block that performs refreshing uses the current supply source for refreshing. A plurality of blocks are refreshed at the same time by using a current supply source for the semiconductor memory device.

According to the present invention, the sense amplifier control circuit has two systems for writing / reading and refreshing, which have lower current supply capability than the above-mentioned writing / reading. In addition, when some blocks of a plurality of blocks that are simultaneously activated are blocks for writing and reading, and the remaining blocks are blocks for refreshing, the blocks for writing and reading use the blocks for writing and reading. Since the refreshing block uses the refreshing operation, especially for a memory such as an image memory which sequentially accesses memory cells, a memory having a large capacity can be realized without providing a time for performing the refreshing operation. The peak current at the time can be reduced.

Further, since a plurality of blocks are simultaneously refreshed using the refresh current supply source, the refresh time can be reduced without reducing the number of refreshes, and the peak current during operation can be reduced. Can be reduced.

Embodiment A first embodiment according to the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 4, FIG. 4 and FIG. FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention,
2 is a circuit diagram of a memory block of the semiconductor memory device according to the first embodiment of the present invention, FIG. 3 is a circuit diagram of a sense amplifier power supply control circuit, FIG. 4 is a circuit diagram of a sense amplifier circuit, and FIG. The figure is a comparison diagram of the timing between the present invention and the conventional example.

1/0 is an input / output circuit, D, is a data line pair, MB _A to _D are memory blocks, ROC is a row decoder control circuit, COC is a column decoder control circuit, RA is a row decoder control signal line, CA is a column decoder control signal lines, PLCL sense amplifier power control circuit control signal line, CO is a column decoder, rOW row decoder, PLC sense amplifier power control circuit, SA ₁ ~ _n the sense amplifier, SW ₁ ~ _n switch elements, SWC ₁ To _n are switch element control lines, b ₁ to _n , ▲ ▼ to _n are bit line pairs,
PL ₁ is a first sense amplifier power line, PL ₂ is a second sense amplifier power line, W ₁ to _n are word lines, MA is a memory cell, MP _1
1-4 is P-type MOS transistor, MN ₁ to ₄ N-type MOS transistor, VCC is the first power supply, VSS second power supply, l ₁ is an inverter.

In FIG. 1, each of the memory blocks MB _A to _D is connected to a signal of a column address bus CA one by one, and a row address bus which is a common signal to each block.
The number of RA signal lines is connected to the sense amplifier control signal line PLCL. The signal lines of the column address bus CA are 41 in total
The signal on the column address bus CA is the output of the column decoder control circuit COC, and the signal on the row address bus RA is the output of the row decoder control circuit ROC. Further, each of the memory blocks MB _A and _B is connected to the input / output circuit 1/0 via the data line pair D.

Each of the memory blocks MB _A ~ _D is in the structure as shown in Figure 2. In FIG. 2, bit line pairs b ₁ to _n , ▲
▼ to _n are arranged orthogonally to the word lines W ₁ to _n, and a memory cell MA is arranged at the intersection. The word lines W ₁ to _n are controlled by the row decoder ROW, and _{one of the} word lines is selected from W ₁ to _n . The bit line pairs b ₁ to _n and ▲ ▼ to _n serve as inputs to the sense amplifiers SA ₁ to _n , and the outputs of the sense amplifiers SA pass through switch elements SW ₁ to _n controlled by outputs SWC ₁ to _n of the column decoder CO. Connected to the data line pair D. The first and second power supply lines P of the sense amplifiers SA ₁ to SA _n
L ₁ and PL ₂ are controlled by a sense amplifier power supply control circuit PLC, and the sense amplifier is controlled by controlling the PL ₁ and PL ₂ .

Next, the operation of the semiconductor memory device according to the first embodiment will be described. The semiconductor memory device of the present embodiment is a memory for sequentially writing and reading data of a memory cell like an image memory. In FIG. 1, for example, a memory block MB _A is a block for writing and reading, and a remaining memory block MB is a memory block MB. Assuming that _B to _D are refreshing blocks, as shown in FIG.
Since the word lines and the sense amplifiers of MB _A to _D are controlled in common, the remaining blocks are written and read while the memory block MB _A is being written and read as shown in FIG. 5 (3. The present invention). memory blocks MB _B ~ _D is automatically since it is refreshed even memory capacity becomes four times without particularly providing the time for the refresh as the (2 conventional example), that holds the data of the memory cell Becomes possible. That is, as shown in FIG. 2, each of the memory blocks MB _A to _D is connected to the signal of the row address bus RA and the sense amplifier power supply control circuit
Because CL is common, will be the row decoder ROW and the power control circuit PLC of each memory block MB _A ~ in _D are controlled by a common, some word line W _m is selected with a common address, sense amplifier SA _{1 -n} are activated. Each of the memory blocks MB _A is activated by the activation of the sense amplifiers SA ₁ to SA _n.
~ Bit line pairs b _1-n in _D, data read out in b _1-n is the sense amplifies. Amplified data memory block MB _A only, are forwarded through the switch elements SW ₁ ~ _n data lines D, and D, the remaining memory blocks MB _B ~ _D
Is rewritten to the memory cell MA, so that the refresh is automatically performed. Here a sense amplifier power supply control circuit PLC is adapted to such as shown in FIG. 3 arrangement, MOS transistors MP3, MN3 when the sense amplifier power control circuit control signal line PLCL becomes H _i state to ON , Power line PL ₁ ,
Power is supplied to PL ₂ . Further, the sense amplifiers SA ₁ to SA _n have the configuration shown in FIG. 4, and are activated when power is supplied to the power supply lines PL ₁ and PL ₂ and read out to the bit line pair b _n and ▲ ▼. Data is sensed and amplified.

In this embodiment, the case where the storage capacity is four times has been described.
No matter how much the number of memory blocks increases due to the increase in storage capacity, it is not necessary to provide any time for performing refresh.

Embodiment 2 FIG. 6 is a diagram comparing the ratio between the write / read time and the refresh time when the present invention is used in a DRAM in the second embodiment of the present invention and the conventional example. Figures 1 and 2
In DRAM to take the structure shown in FIG., The memory block MB _A
Assuming that _D is a block for performing all refreshes, four word lines are collectively refreshed, which is the same as apparently reducing the number of word lines to 1/4. Even if the memory capacity is quadrupled as shown in the present invention), the refresh time does not increase as shown in FIG. 6 (2. Conventional example), and the time for writing / reading per unit time is reduced. In addition, since it is not necessary to reduce the number of refreshes, conditions such as the retention time of the memory cell can be relaxed. That is, the following equation holds, and it can be seen that the refresh time is reduced by increasing the number of blocks.

Embodiment 3 FIGS. 7, 8 and 9 show a third embodiment according to the present invention.
This will be described with reference to FIG. 10 and FIG. FIG. 7 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention, in which the semiconductor memory device according to the first embodiment of the present invention is improved, and FIG. 8 is a third embodiment of the present invention. FIG. 9 is a circuit diagram of a memory block of a semiconductor memory device according to an example, in which the memory block of the semiconductor memory device according to the first embodiment of the present invention is improved; Circuit diagram of sense amplifier power supply control circuit of device, 10th
The figure is a comparison diagram of the current consumption of the semiconductor memory device according to the conventional example and the first embodiment of the present invention and the semiconductor memory device according to the third embodiment of the present invention. PLCL _A to _D are sense amplifier power control circuit control signal lines, RPLCL _A to _D are sense amplifier power control circuit control signal lines for refresh, I ₂ and I ₃ are inverters, MP ₄ and MP ₅ are P-type MOS transistors, MN ₄ , MN ₅ is N-type MOS
The transistor and PLCA are a write / read sense amplifier power control circuit, and PLCB is a refresh sense amplifier power control circuit.

In the configuration of the semiconductor memory device according to the first embodiment, since four memory blocks are simultaneously activated, that is, a word line rises and a sense amplifier is activated, as shown in FIG. It is four times as large as. Although the increase in current consumption is a problem in itself, it causes malfunction due to a voltage drop in the power supply wiring, deteriorates the operation margin, and adversely affects the design of power supply circuits such as down converters. is there. Therefore, as shown in FIG. 9, the sense amplifier power supply control circuit PLC of the first embodiment shown in FIG. 3 is improved. That is, a sense amplifier power supply control circuit PLC is provided in two systems for writing / reading and refreshing. In a memory block for writing / reading, a memory block for refreshing is used by using a sense / amplifier power supply control circuit PLCA for writing / reading. Uses a refresh sense amplifier power supply control circuit PLCB. In FIG. 9, an inverter I ₂ , a P-type MOS transistor MP ₄ , and an N-type MOS transistor MN ₄ are a write / read sense amplifier power supply control circuit PLCA.
l ₃ , P-type MOS transistor MP ₅ , N-type MOS transistor MN ₅
Is a refresh sense amplifier power supply control circuit PLCB. Here, the sizes of MP ₅ and MN ₅ are smaller than those of MP ₄ and MN ₄ , so that the current consumption when refreshing is suppressed. Incidentally, the sense amplifier power control circuit PLCA for write and read necessary sense amplifiers SA ₁ ~ _n is charged in the sense amplifier SA ₁ ~ data line pair D, which is connected after the _n, the load capacity per unit time, such as Therefore, a somewhat large size is required. In the memory, such as successively accesses data of the memory cells as such as an image memory, for example, blocks of accessing the memory block MB ₄ in FIG. 7, when a block to be refreshed remaining memory blocks MB _B ~ _D , M
In B _A , a sense amplifier power control circuit PLCA for writing / reading is used, and in MB _B to _D , a sense amplifier power control circuit PLCB for refresh is used. The one word line is connected to a number of memory cells MA as shown in FIG. 8, in the memory block MB _A one word line W
for sequentially accessing the memory cell MA, which is connected to the _n, the memory cell MA, which is connected to one word line W _n
It will take enough time to access all of them. Meanwhile refresh order to perform the memory cell MA, which is connected to the word line W _n of a single time, the memory blocks MB _B ~ _D
It is possible to perform slowly refreshed while accessing the sequential memory array MA in the memory block MB _A in. Therefore, it is possible to use a small-sized sense amplifier power supply control circuit in order to prevent an increase in current consumption, and it is possible to reduce current consumption as shown in FIG.

By providing the sense amplifier power supply control circuit for writing / reading and the sense amplifier control circuit for refreshing as described above, it is possible to reduce power consumption even when refreshing a plurality of memory blocks simultaneously. .

As described above, according to the present invention, even if the storage capacity of a memory to be sequentially accessed is increased, it is not necessary to provide a time for performing a refresh operation. This has the effect of simplifying the design of the device to be used.

In addition, since refresh can be simultaneously performed in a plurality of blocks obtained by dividing the memory cell array, the refresh time can be reduced, and there is an effect that it is not necessary to reduce the number of refreshes. Conditions, such as the retention time of the material, can be relaxed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to the first and second embodiments of the present invention. FIG. 2 is a circuit diagram in a memory block of the semiconductor memory device according to the first and second embodiments of the present invention.
FIG. 4 is a circuit diagram of a sense amplifier power control circuit of the semiconductor memory device, FIG. 4 is a circuit diagram of a sense amplifier of the semiconductor memory device,
FIG. 5 is a comparison diagram of the timing between the first embodiment of the present invention and the conventional example, and FIG. 6 is a graph showing the ratio of the write / read time and the refresh time when the present invention is used in the DRAM. FIG. 7 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 8 is a memory block of the semiconductor memory device according to the third embodiment of the present invention. FIG. 9 is a circuit diagram of a sense amplifier power supply control circuit of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 10 is a conventional semiconductor memory device and a first embodiment of the present invention. FIG. 11 is a timing chart of a DRAM refresh operation, and FIG. 12 is a DRAM memory cell and its semiconductor memory device according to the third embodiment of the present invention. Peripheral circuit diagram, Fig. 13 FIG. 14 is a block diagram of a DRAM according to a conventional technology, FIG. 14 is a circuit diagram in a memory block of the DRAM according to the conventional technology, FIG. 15 is a diagram comparing refresh time ratios depending on the storage capacity of the DRAM according to the conventional technology, and FIG. FIG. 1 is a diagram in which the timing of writing / reading and refreshing of an image memory according to the conventional technique is compared according to the storage capacity of the image memory.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-203290 (JP, A) JP-A-63-86193 (JP, A) JP-A-60-696 (JP, A) JP-A 63-86193 282998 (JP, A) JP-A-61-259294 (JP, A) JP-A-62-68797 (JP, A)

Claims (3)

(57) [Claims] A plurality of memory cells arranged in a matrix, a plurality of word lines for selectively driving these memory cells, and a plurality of pairs of bit lines for exchanging information with each memory cell. , A row decoder circuit for selecting the word line, a column decoder circuit for selecting the bit line pair, a sense amplifier circuit for detecting a potential difference between each pair of bit lines, and a write / read circuit. And a plurality of blocks each including a sense amplifier control circuit having a current supply source for refresh and a current supply source for refresh having a lower current supply capability than the current supply source for writing / reading. Some of the plurality of blocks are blocks for writing / reading, and the remaining blocks are blocks for refreshing. In block for the write-read current source for the write and read is used,
2. A semiconductor memory device according to claim 1, wherein said refreshing block uses said refreshing current supply source. 2. The semiconductor memory according to claim 1, wherein refresh of said remaining blocks has been completed at the time of completion of writing / reading of data of said block to be written / read. apparatus. 3. A plurality of memory cells arranged in a matrix, a plurality of word lines for selectively driving these memory cells, and a plurality of pairs of bit lines for exchanging information with each memory cell. , A row decoder circuit for selecting the word line, a column decoder circuit for selecting the bit line pair, a sense amplifier circuit when detecting a potential difference between the bit lines of each pair, and a write / read circuit.
A plurality of blocks each including a read current supply source and a sense amplifier control circuit having a refresh current supply source having a lower current supply capability than the write / read current supply source are provided. A plurality of blocks are refreshed at the same time by using the current supply sources described above.