JPH04162665A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable operation current to be reduced and prevent malfunction from occurring by allowing a gate electrode to be controlled independently by first and second control lines and by connecting a bit line to two MOS transistors which are connected in series and a capacitor. CONSTITUTION:MN1 and MN2 are switching transistors and are controlled by two control lines of WLR and WLC. A memory cell MC allows data to be transferred between an electric charge accumulation part C1 and a bit line BL by setting two control lines of WLR and WLC to 'H' state. A VCP is cell-plate voltage, thus enabling the degree of freedom of control of memory cell for owning two switching transistors to be high. Also, data is read out of a selected memory cell only, no waste power is consumed since only the selected sense up and bit line are operated and malfunction due to noise from an adjacent bit line is also eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor memory devices.Prior art FIG. 10 shows a circuit diagram of a memory cell of a conventional semiconductor memory device. The stored charge is transferred to the switching transistor M controlled by the word line WL.
Figure 11 is an example of realizing the circuit shown in Figure 10 on a semiconductor chip.This example is currently used as a memory cell of a dynamic random access memory (hereinafter referred to as DRAM). It is the smallest DRAM memory cell currently being considered. Figure 12 shows a circuit around a conventional DRAM memory cell.45AI-3
An is a sense amplifier, WLl-WLmlt '7-de M
L BLI-BLn, XBLI-XBLn are bits ML MC4 and memory cell < SVC, SVS are the control lines of the sense amplifier. When reading data in the circuit shown in Figure 12, the word line WL is set to rHJ state and the memory cell MC is The data is read to the bit lines BL and XBL, and the data is amplified by operating the sense amplifier SA controlled by the sense amplifier power supply control circuit PLO. As DRAMs become more highly integrated, the following problems have arisen.For example, in Figure 12, read the data of the memory cell at the cross point of WLl and BL2. When you want to set the word line WLI to the "H" state, the data of all memory cells MC connected to the word line WLI will be read out ((The number of times that data other than the necessary data is also amplified is wasted. In particular, due to the high integration of current DRAMs,
Although the internal structure is divided into several blocks and each block is operated at the same time, the wasteful power consumption mentioned above is increasing, and the miniaturization technology for higher integration is progressing. Bit line pair BL2. Coupling capacitance (CI, C2) between adjacent bit lines placed extremely close to XBL2 has started to cause error differences.For example, the operation of sense amplifier SA2 is delayed for some reason.
and BL2. XBL2 and BL30) Potential b < different 6
Amplification delayer BL2 and xBL2 t'1
．． .

As described above, in conventional DRAMs, the operating current increases due to high integration and miniaturization for high integration, and malfunctions occur.The present invention takes this into consideration. Means for Solving the Problems of the Invention Aiming to Provide a Semiconductor Memory Device that Reduces Operating Current and Prevents Malfunctions 1. The gate electrode is independently controlled by the second control line, and First and second MC3 connected in series
A semiconductor memory device comprising a memory cell including a transistor, a capacitor connected to the source of the second MC3 transistor, and a bit line connected to the drain of the first MOS transistor. Furthermore, the semiconductor memory devices having the above configuration are arranged in a matrix to form a memory cell array, and the second control line is arranged perpendicularly to the second control line, and the bit line is parallel to the first or second control line. The first control line may be controlled by a row address, and the second control line may be controlled by a column address. A semiconductor memory device in which a sense amplifier is controlled by the second control line, and the semiconductor memory device is characterized in that every other bit line or every other bit line is paired to form the bit line pair. In a memory device, an active region surrounded by an element isolation region is provided on a semiconductor substrate, and first and second MC3s having the same polarity and connected in series are provided in the active region. To form a transistor, a wiring is connected to the drain part of the first MC3 transistor, and a wiring is connected to the drain part of the first MC3 transistor.
The transistor has a structure in which a capacitance storage part is connected to the source part of the transistor, and the gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor are formed using different wiring layers. Even if the gate electrode of the MOS transistor is formed so as to partially overlap the gate electrode of the first MOS transistor, the present invention operates because of the above-described structure, so that data is read only from the selected memory cell. Since only the sense amplifier and bit line operate, there is no wasted power consumption, and there is no malfunction caused by noise from adjacent bit lines.Embodiment Figure 1 shows a DRAM in an embodiment of the present invention. This figure shows a circuit diagram of a memory cell in FIG.
MN2 is a switching transistor, WLR,
This memory cell MC is controlled by the two control lines 1lLc and transfers data between the charge storage section C1 and the bit line BL by setting the two control lines IFLR and WLC to the rHJ state. Since the memory cell of this embodiment configured as described above has two switching transistors, the degree of freedom in controlling the memory cell is high. Figure 2 is similar to Figure 1. The memory cells of a DRAM are arranged in a matrix to form a memory cell array, and the two word lines that control the memory cells are arranged perpendicular to the bit lines. Although the word lines (WLRm-WLRm+7) placed horizontally with the bit lines are controlled by column addresses, the word lines (llncn-WLCn+1) placed horizontally with the bit lines are controlled by column addresses. data in unselected memory cells MC without reading data from unselected memory cells.
It is now possible to select only one memory cell and read data, eliminating unnecessary power consumption. Figure 3 is a more detailed circuit diagram of the memory cell arrangement shown in Figure 2. In Figure 3, the word lines WLRI-IN and Rm arranged perpendicularly to the bit lines are controlled by row addresses, and the word lines ILcI and WLC2 arranged horizontally to the bit lines are controlled by column addresses. Furthermore, the sense amplifiers SAI and SA2 connected to the bit lines are controlled by the word line WLCIJLC2 arranged horizontally with the bit lines.
Note that the word line controlled by the column address may be arranged perpendicular to the bit line, and the word line controlled by the row address may be arranged parallel to the bit line.
% Figure 4 is a circuit diagram of column decoder CO. Figure 5 is a circuit diagram of sense amplifier SA and sense amplifier control circuit PLC. Figure 6 is an operation timing diagram of the circuit shown in Figure 5.
The operation of this circuit will be explained using the following example ('L word l@WLRI and word line WLC1).
When reading data from memory cell MC controlled by word line wL selected by row address
(not shown, but controlled by a row decoder) is brought into the rHJ state. Next, the word line WLc1, which is controlled by the column decoder COI, is brought into the rHJ state and the data in the memory cell MC is read out onto the bit line BLI.

In FIG. 4, column decoder CO outputs WLC as rHJ by inputting column addresses CAa, CAb, CAc to AND circuit AND1 in rHJ state.
In addition, H and C are input to another AND circuit AND2 to control the output SWC together with the input signal PSW.The data ζ read out to the bit line BLI is amplified by the sense amplifier SAI along with its complementary bit line XBLI. In FIG. 5, the sense amplifier control circuit PLC outputs the output WLC of the column decoder CO and the sense amplifier activation signal PS.
E is input to a NAND circuit NANII and an AND circuit AND, each of which is a transistor MP3. Although MNIO is controlled and current is supplied to sense amplifier control lines svc and svs, MN6. MN7. MN8 is a circuit that equalizes and precharges the potentials of SVC and SVS, and even though it is controlled by the equalize precharge control signal PEQ, VFR is the potential of the precharge level. Also, the sense amplifier SA is the sense amplifier control circuit PL.

A circuit that amplifies data (MNI, MN2. MPI, MP2) is controlled by the outputs svc and svs of C, and a circuit that equalizes the bit line pair (MN3. M is controlled by the equalize precharge control signal PEQ).
N4. MN5) Karanati & MNI-MNIO
are N-type MOS transistors MP2-MP3 are P-type MO3
As shown in Figure 6, first WLR and WLC become "H", and the memory cell (not shown) connected to the bit line BL is selected, and the information stored in the memory cell becomes a bit. Next, when WLC becomes "H", the selected sense amplifier control circuit PLO causes the sense amplifier activation signal PSE generated by a timing generator (not shown) to become "H". When the equalize signal PEQ becomes L", the sense amplifier control circuit PLO starts operating. When the sense amplifier control circuit PLO starts operating, the sense amplifier control line svc
, svs go from the precharged state of 1/2 VCC to "H" and "L" respectively, and the sense amplifier SA starts operating to amplify the data read out to the bit line BL. Only the sense amplifiers SA selected by the column decoder CO are activated, which eliminates unnecessary current consumption. Similarly, by using the above configuration, it is possible to select only one memory cell and read data without reading data from unselected memory cells. Since only the selected sense amplifier is operated, there is no wasted power consumption and peak current can be suppressed. Since only the potential of the selected bit line is amplified by the selected sense amplifier, malfunctions due to noise in the potential amplitude of adjacent bit lines are eliminated.
This is an embodiment in which every other book is paired and connected to a sense amplifier. In this embodiment, the sense amplifiers and column decoders are divided into two groups a and b, each of which is connected to the semiconductor memory device shown in FIG. Even if they have the same configuration
Here, if sense amplifier 5Aa2 is selected and operates, bit line BLa2. Only the potential of XBLa2 has an amplitude (\The potential of other bit lines does not have an amplitude.) Here, in particular, the bit line BLb2 is
Eight bit lines B serve as shield lines between LaZ.
La2. XBLa2 has a large operating margin because it eliminates the influence of noise caused by the amplitude of each other's potentials, and data read from memory cells (not shown) can be amplified quickly and reliably. The power of connecting every other pair to the sense amplifier (the same effect can be obtained by connecting every other pair to the sense amplifier) is shown in Figure 8. FIG. 9 is a top view of the embodiment shown in FIG.
This is a cross-sectional view when the embodiment shown in the figure is cut along the line a-a'. On top of that, two N-type MOS transistors with gates of the first and second word lines WLI and WB2 are formed in series.
The N-type MO8 transistor whose gate is the first word line fLI is connected to the bit line BL and whose gate is the second word line WL2. C is connected to the structure 1 shown above.The power is the same as the conventional memory cell shown in FIG. The increase in area is not so large compared to the conventional memory cell shown in Figure 11.The second word line is also connected to the cell line. However, as described in the detailed explanation of the invention, the present invention can prevent malfunctions caused by miniaturization for high integration. Since it is possible to suppress the peak current to a low level, DR
The practical effects are great because AM can be easily designed and the design period can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a DRAM memory cell circuit according to an embodiment of the present invention @ Fig. 2 is a circuit diagram of the memory cell arrangement shown in Fig. 1 Fig. 3 is a more detailed memory cell arrangement shown in Fig. 2 Figure 4 is the circuit diagram of the column decoder in Figure 3. Figure 5 is the circuit diagram of the sense amplifier and sense amplifier control circuit in Figure 3. Figure 6 is the circuit diagram of the circuit in Figure 5. Figure 7 is the diagram of the operation timing of the circuit in Figure 5. is a block diagram in which every other bit line of the DRAM of the present invention is paired and connected to a sense amplifier. Cross section when cut between a-a' in the figure @ Figure 10 is a circuit diagram of a conventional DRAM memory cell Figure 11 is a structural diagram of a conventional DRAM memory cell
Figure 12 is a circuit diagram around the memory cell of a conventional DRAM. Name of agent: Patent attorney Akira Okaji and two others I
2 Figure: l : : i :: ith
4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 119

Claims (6)

[Claims] (1) First and second MOS transistors whose gate electrodes are independently controlled by first and second control lines and connected in series, and a capacitor connected to the source of the second MOS transistor. , and a bit line connected to the drain of the first MOS transistor. (2) The semiconductor memory device according to claim 1 is arranged in a matrix to form a memory cell array, the first and second control lines are arranged orthogonally, and the bit line is connected to the first or second control line. A semiconductor memory device, wherein the first control line is arranged in parallel to a line, and the first control line is controlled by a row address, and the second control line is controlled by a column address. (3) A sense amplifier is connected to the bit line pair made up of two bit lines, and the sense amplifier is controlled by the second control line. The semiconductor storage device described above. (4) The semiconductor memory device according to claim 3, wherein the bit line pairs are formed by forming pairs of every other or every plurality of bit lines. (5) providing an active region surrounded by an element isolation region on a semiconductor substrate; forming first and second MOS transistors having the same polarity and connected in series in the active region; A semiconductor memory device characterized in that the semiconductor memory device has a structure in which a wiring is connected to a drain portion of the first MOS transistor, and a capacitance storage portion is connected to a source portion of the second MOS transistor. (6) The gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor use different wiring layers, and the gate electrode of the second MOS transistor is the same as the gate electrode of the first MOS transistor. 6. The semiconductor memory device according to claim 5, having a structure in which portions are overlapped.