JPH023199A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the number of bits in a multi-bit test mode by simultaneously obtaining the connecting condition of plural complementary data lines to a complementary common data line and comparing the level of a non- inverting and inverting signals lines in the complementary common data line with a referring potential. CONSTITUTION:In the multi-bit test mode, one memory cell respectively from each sub memory array of memory cell arrays MARY0-3 is simultaneously connected to complementary common data liens CD0-CD7 by an (m+1)-number of the complementary data lines. At such a time, two lead amplifiers to be provided to respective main amplifiers MA1-3 are selectively connected only one of the lines CD0-CD7. The referring potential of an intermediate level is commonly supplied to the non-inverting input terminal of the lead amplifier. Thus, the lead amplifier is operated as a differential amplifier and it is identified whether the reading signals of the (m+1)-number of the memory cells are wholly same logical levels or not. Then, the signals are tabulated and outputted from a test logic circuit TL. Accordingly, the bit number of the multi-bit test mode can be increased without sacrificing high integration.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and is applicable to, for example, a large-capacity dynamic RAM (Random Access Memory) having a multi-bit test function. This is a particularly effective technique.

[Conventional technology]

There is a dynamic RAM that has a relatively large storage capacity. Furthermore, a so-called multi-bit test method is one method for efficiently performing a functional test of such a dynamic RAM and promoting cost reduction.

The multi-bit test method is described in, for example, Mitsubishi Giho JVO 1,59, No. 9, published by Mitsubishi Electric in 1985.

[Problem to be solved by the invention]

As the capacity of dynamic RAMs and the like progresses, the following problems arise in the conventional multi-bit test method as described above. In other words, the dynamic RAM employing the multi-bit test method described above has a plurality of memory arrays, and includes a plurality of complementary common data lines and a main amplifier provided corresponding to these memory arrays. When the dynamic RAM is placed in a multi-bit test mode, one memory cell is simultaneously selected for each complementary common data line, and the same data is written and read from these memory cells. . As a result, if all the read data match, the dynamic RAM is considered normal and outputs a high level or low level output signal corresponding to the read data. At this time, if data different from even one pin is read out, the dynamic RAM is determined to be abnormal and its output is placed in a high impedance state.

In other words, in the conventional multi-bit test method as described above, a dynamic RAM has a plurality of complementary common data lines and main lines corresponding to the number of memory cells that are simultaneously selected, that is, the number of data bits that are simultaneously written or read. It is essential to have an amplifier. As the capacity of dynamic RAM increases to, for example, 16M (mega) bits or 64M, this becomes a factor that hinders the high integration of dynamic RAM and prevents its cost from being reduced. Also, to avoid this,
Reducing the number of bits to be simultaneously tested in the multi-pint test mode will conversely increase the cost of testing the dynamic RAM.

The purpose of this invention is to increase the number of bits of multi-bit test function without sacrificing high integration.
An object of the present invention is to provide a semiconductor memory device such as a flash memory type RAM.

Another object of the present invention is to reduce the testing cost of a dynamic RAM'4 semiconductor memory device with an increased capacity, and to promote cost reduction.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief description of the main inventions disclosed in this application is as follows. That is, dynamic type R
In a multi-bit test mode such as AM, multiple complementary data lines are connected to the complementary common data line at the same time, and the levels of the non-inverted signal line and the inverted signal line of the complementary common data line are compared with a predetermined reference potential. It is something.

[For production]

According to the above means, in the multi-bit test mode,
The level of either the non-inverted signal line or the inverted signal line of the complementary common data line is higher than the reference potential, in other words, the level of either the non-inverted signal line or the inverted signal line remains at a predetermined precharge level. By determining that there is, it can be confirmed that the read signals of the plurality of complementary data lines connected to the complementary common data line are at the same logic level. Therefore, there is no need to add complementary common data lines and main amplifiers, that is, dynamic RAM
The number of bits in the multi-bit test mode can be increased without sacrificing high integration.

As a result, it is possible to reduce the testing cost of dynamic RAMs and the like, which are becoming increasingly popular, and to promote cost reduction.

[Example of fruit plum]

Figure 6 shows a dynamic 7-type RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Also, the first
2, and 5 each show a circuit diagram of an embodiment of the memory array and its peripheral parts of the dynamic RAM shown in FIG. 6, the memory array switching circuit, the main amplifier, and the column address decoder. There is. The configuration and operation of the dynamic RAM of this embodiment will be outlined with reference to these figures. Note that the circuit elements constituting each of the circuit elements in FIGS. 1, 2, and 5 and each block in FIG. It is formed on a single semiconductor substrate such as. Further, in the following figures, MOSFETs whose channel (bank gate) portions are marked with arrows are of P-channel type, and are shown to be distinguished from N-channel MO3FETs whose channel (bank gate) portions are not marked with arrows.

The dynamic RAM of this embodiment includes nine memory arrays, ie, four memory arrays MARYO to M, although it is not particularly limited.
ARY3 and a total of eight sets of complementary common data lines DDO, two sets each of which are provided corresponding to these memory arrays.
〜D7 (For example, the non-inverted signal line CDO and the inverted signal line CDO are collectively expressed as a complementary common data line -○DO.

(Below) In this embodiment, each of the memory arrays MARYO to MARY3 has m+1 sub-memory arrays, as will be described later. The complementary common data lines CDO/CDI to CD6\CD7 of each column are
Although not particularly limited, the corresponding main amplifier switching circuit M
Corresponding main amplifier MA via SWO-MSW3
Connected to O to MA3, respectively. Main amplifier MAO
-MA3 each includes two read amplifiers and two write amplifiers.

When the dynamic RAM is in normal read mode, complementary common data! Two designated memory cells of the corresponding memory arrays MARYO-MARY3 are connected to 61cDo to CD7, one each. At this time, the two read amplifiers provided in each main amplifier output the corresponding complementary common data ill CD O
~CD7, and has the function of amplifying the read signal output from the selected memory cell.

When the dynamic RAM is in the multi-bit test mode, one memory cell from each sub-memory array of the corresponding memory array MARYO-MARY3 is connected to the complementary common data lines CD0-CD7 at the same time for a total of +1 memory cells. state. At this time, the 21 read amplifiers provided in each main amplifier are selectively connected to only one of the pair of complementary common data line temperatures DO-CDI to CD6-CD7. That is, the non-inverting input terminals of the two read amplifiers provided in each main amplifier are connected to the corresponding complementary common data line CDO or the non-inverting signal line and the inverting signal line of DI to D6 or D7, respectively, A predetermined reference potential is commonly supplied to the inverting input terminal.

The reference potential is, although not particularly limited, approximately at a level between the high level and the low level of the read signal output to each complementary common data line in the normal read mode. Therefore, the two read amplifiers provided in each main amplifier are first and second differential amplifier circuits that compare the levels of the non-inverted signal line and the inverted signal line of the corresponding complementary common data line with the reference potential. , and determines that the level of these signal lines is higher than the reference potential and remains at a predetermined precharge level.

As a result, it is determined that the read signals of the m + 1 fa memory cells connected to each complementary common data line are all at the same logic level, and the result is transmitted to the test logic circuit TL. The test logic circuit TL has a function of summing test results transmitted from each main amplifier.

As a result, the dynamic RAM of this embodiment has a function of selecting a total of 4x(m+1)(1?j) memory cells at the same time and performing a multi-bit test on these memory cells. Increasing the number of bits of such a multi-bit test function can be achieved without adding complementary common data lines and main amplifiers, in other words, without hindering the high integration of dynamic RAM. RAM (7) test cost is reduced and cost reduction is significantly promoted.

In FIG. 6, the dynamic RAM of this embodiment
includes, but is not particularly limited to, two column address decoders CADO and CADI, and four memory arrays M arranged to sandwich these column address decoders.
ARYO, MARYI and MARY2. Contains MARY3.

Although the memory array MARYO is not particularly limited, the first
As shown in the figure, m+1 (hard sub-memory array S
Contains MO0 to 5M0m. Although not particularly limited, these sub-memory arrays each have a two-intersection system, and q+
One word line WO to Wq and n arranged in the horizontal direction
(q+1)x (n+1)f[! if dynamic memory cells.

Memory array MARYI is the memory array MARY
The configuration is symmetrical to O. In addition, memory array MAR
Y2 and MARY3 are configured to correspond to the memory arrays MARYO and MARYI, respectively, and form a pair.

The dynamic memory cells constituting the memory array MARYO-MARY3 include, but are not particularly limited to, an information storage capacitor C3 and an address selection MOS FETQm which are connected in series. A predetermined cell plate voltage vcp is commonly supplied to the other capacitor Cs. In each memory array, the drains of the address selection MO3FETQm of q+1 memory cells arranged in the same column are connected to the corresponding complementary common data line DOO/DOO-Don-DO.
They are alternately coupled to non-inverted signal lines or inverted signal lines of T to DmO-DmO to Dmn-Dmn with a predetermined regularity. Also, (m+1)X (n
+1) MOS F for selecting addresses of memory cells
The gates of ET are commonly coupled to corresponding word lines WO to Wq, respectively.

Word lines WO to Wq forming memory arrays MARYO to MARY3 are connected to corresponding row address decoders RAD.
They are each coupled to the O-RAD 3 and are alternatively set in a selected state.

The row address decoders RADO to RAD3 receive data from the row address buffer RAB to the i-
On the 1-bit complementary internal address signal xo-axi-2 (
Here, for example, the non-inverted internal address signal axQ and the inverted internal address signal axQ are collectively expressed as a complementary internal address signal axQ (the same applies hereinafter), and the timing signal φX is commonly supplied from the timing generation circuit TG. Supplied. Here, the timing signal φX is normally set to a low level, and is set to a high level at a predetermined timing when the dynamic RAM is placed in a selected state.

The row address decoders RADO to RAD3 are selectively brought into operation when the timing signal φX is set to a high level. In this operating state °ζ, the row address decoder RADO-RAD3 decodes the above-mentioned complementary internal address signals aXO-axi2, and decodes the corresponding word line WO of the corresponding memory array MARYO-MARY3.
~Wq is alternatively set to a high level selection state.

The row address buffer RAB converts the row address signal transmitted via the address multiplexer AMX into a timing signal ψa supplied from the timing generation circuit TG.
Capture and retain according to r. Also, based on these row addresses No. 6, complementary internal address No. 16 axo-waxi of i+1 pinto is formed. Of these, the complementary internal address signals axi-1 and axi of the upper two bits
is supplied to the array selection circuit ASL, although not particularly limited, and its false internal address signal axQ-axi-
2 is the row at 1 decoder RADO-RAD3
Commonly supplied to

One input terminal of the 71-channel multiplexer AMX has
X address signals AXO to Axr supplied in a time-division manner via external terminals AO to Ai are input, and a fresh address signal arO-ari from the refresh at/scown RFC is input to the other input terminal. be done. The address multiplexer AMX is further supplied with a timing signal φre (as a selection control signal) from the timing generation circuit TG.

The address multiplexer AMX is a dynamic type RA
M is in the normal operation mode and the timing signal ψre
When f is set to low level, external terminal A O・~Ai
X18i to X address signal AXO~ supplied via
Select one and use the row address buffer as the row address signal)? A Communicate to B.

Further, when the dynamic RAM is in refresh mode and the timing signal φrer is set to high level, the refresh address signal aro-ari supplied from the refresh address counter RFC is selected;
It is transmitted to the row address buffer RAB as a row address signal.

The novel address counter RFC is selectively activated when the dynamic type RAλ is placed in the refresh mode. In this operating state, the refresh address counter RFC performs a walk-through operation according to the timing signal φrc supplied from the timing generation circuit TO, and the refresh address counter RFC
form ri. These refresh address signals are supplied to the other input terminal of address multiplexer AMX, as described above.

On the other hand, the complementary data lines DOO/DOO–DOn/Don to D constituting the memory arrays MARYO–MARY3
mO-DmO~Dmn -Dmn are representatively shown in the memory array MARYO in FIG.
They are respectively coupled to corresponding unit circuits of P3. In addition, on the other side, the corresponding N-type sense amplifier 5AN
Through the corresponding unit circuits of O~5AN3, the corresponding switches MO of the corresponding column switches C3WO-C3W3
They are coupled to 3FETs Q1B, Q19 to Q20, Q21, etc., respectively.

The P-type sense amplifier 5APO-3AP3 includes (m+1)×(n+1) unit circuits provided corresponding to each complementary data line of the memory arrays MAI"2YO to MARY3, and these unit circuits are not particularly limited. is a 21-pin P whose gate and drain are cross-connected to each other.
An N-channel precharge MO3FET Q13 provided between the channel MO3FETs Q2 and Q3, etc., and the non-inverted signal line and inverted signal line of the corresponding complementary data line.
etc., respectively.

MOS F iE, 'The sources of Q 2 and Q 3 are commonly coupled to a common source line CP, and are further coupled to the power supply voltage of the circuit via a P-channel type drive MOS F +2.T Q l. Here, the power supply voltage of the circuit is not particularly limited, but is set to be a positive power supply voltage such as +-5V.
An inverted signal from the inverter circuit Nl of the timing 1-3 φp3 supplied from the timing generation circuit TG is supplied to the gate of the inverter circuit Nl. Here, the timing signal φpa
is generally considered to be a low-level RAM.
When the signal is selected, it is set to a high level at a predetermined evening/f timing. This allows MOS FETQ2 and Q
3, etc. are selectively put into operation by the above-mentioned tie-off signal φpa being set to high level and rqAilJMO8FETQl being turned on, and the corresponding N-type sense antennas 5ANO to S A N 3 (unit of D vs Wi Together with the circuits, they function as one unit amplifier circuit. In this operating state, these unit amplifier circuits are coupled to the selected word line (m+1) x (n + 1
) The corresponding minute read signal from the memory cell Ill is amplified and made into a high level or low level binary read signal.

M of each unit circuit of P-type sense amplifier 5APO-3AP3
The gates of O3FETQ13 etc. receive a timing signal φpc from the timing ordering circuit TO! It is supplied to E. Here, the timing signal φpc is a dynamic type R
When AM is in a non-selected state, it is selectively set to high level. MO3FETQ13 etc. are dynamic type RA
By setting M to a non-selected state and setting the above-mentioned timing signal φpC to a high level, it turns on all at once, and the pair Q
The non-inverted signal lines and the inverted signal lines of DmO-DnIO to Dmn-Dmn are short-circuited to form a half precharge level.

Similarly, each unit circuit of the N-type sense amplifiers 5ANO to 5AN3 is composed of, but not limited to, two N-channel MO3FEs whose gates and drains are cross-connected to each other.
Contains TQI 4・C15 to C16・C17, etc., respectively. These MO3FETQ14・C15 to C1
Sources such as 6 and C17 are shared with common source 28 CN!
Combined with N-channel type MO3FET
It is coupled to the ground potential of the circuit via Q11. Drive MO
The above timing signal φ is applied to the gate of 3FETQI I.
pa is supplied. As a result, MO3FETQ14・
C15 to Q10, C17, etc. are driven by MO5FETQII when the timing signal φp3 is set to the \f level.
is turned on. 2, the iB P-type sense amplifier S A P O ~ is selectively activated.
SA? Along with the corresponding star circuit of 3, 1 (numbered as a solid unit amplification circuit).

The column switches CS'wV O to CS 17/3 are connected to the corresponding memory arrays MARYO to MAR, as represented by the column switch CS W O in FIG.
(m+1) provided corresponding to each complementary data line of Y3
X (n+1) pair of switch MO3FETQ18・C1
These switches M include 9 to C20-C21 etc.
As described above, one of the OS F BTs is coupled to the corresponding complementary data lines of the corresponding memory arrays MARYO to MARY3, and the other one is connected to the corresponding two sets of complementary common data establishment DO, stand D1 to CD6, and - Alternately commonly bonded to CD7. Column switch CS W (
2 pairs of adjacent switches MO3F with 1” CS W 3
The gates of ET are commonly coupled, and a corresponding data line selection signal YOO~YOn-1 to YmO-Ymn-1 is sent from Dl to a corresponding column decoder CADO or C4.
are supplied respectively.

Data line selection signal yoo~Yon-1 or YmO~Y
mn-1 is normally set to low level, and dynamic type R
When AM is brought into a selected state in the normal operation mode, it is alternatively set to a high level at a predetermined timing. At this time, in the column switches C3W0 to CSW3, the corresponding two sets of switches MO3FET are turned on, and the corresponding two sets of complementary data lines of the memory array MARY O-M ARY3 are connected to the corresponding complementary data lines. It is selectively connected to the common data line temperature DO/Dan DI to -CD6/D7. On the other hand, when the dynamic RAM is set to the selective state in the multi-bit aX test mode, the data line selection signal YO
O~YOn-1 to YmQ-Ymn-1 are the corresponding data line selection signals yoo~Y+nO to YOn-1~
'/mrl-1 are respectively set to high level by rn+1 at the same time. At this time, column switch C3WO
~C3W3, the corresponding 2x(m+1) sets of switch MOS FETs are simultaneously turned on.

As a result, memory array MARYO-M ARY 3
sub-memoria [/i SMOO ~ SM Q rn or SM 30 ~ SM 3 m to the corresponding 2x (m+
1) A set of complementary data lines is selected and the corresponding complementary common data 1liil-CD O-layer D1 to D6-C
Each m+1 set is selectively connected to D7.

By the way, the column switches C3WO to C8W3 are
As exemplarily shown in the figure, two bias circuits BCO and BCI are provided corresponding to the complementary common data line temperatures DO/CDI to -CD6/D7 of each column, respectively. Although these bias circuits are not particularly limited,
Diode-type N-channel MO3FETs Q22 to Q25 are provided between the non-inverted signal line and inverted signal line of each complementary common data line and the circuit power supply voltage, and the non-inverted signal line and inverted signal line of each complementary common data line. N-channel MO3FETQ26 installed between the circuit ground potential and
Q29 and Q29 respectively. MOSFETQ26~Q29
are designed to have negligibly small conductance, and their gates are commonly supplied with a timing signal φce from a timing generation circuit TG, although this is not particularly limited. Here, the timing signal φce is selectively set to a high level when the dynamic RAM is in a selected state. As a result, complementary common data line -C
The non-inverted signal lines and inverted signal lines of DO~-CD7 are connected to the bias circuits BCO and BC1f71M from the power supply voltage of the circuit when the dynamic RAM is in the blue selection state.
A predetermined precharge level is obtained by subtracting the threshold voltages of O3FETs Q22 to Q25. In addition, the dynamic RAM is in the selected state and the corresponding memory array M
By selectively connecting designated complementary data lines of ARYO to MARY3, selectively discharging is performed.
It is set to a predetermined low level.

The operation of the readout circuit including the complementary common data lines -CDO to CD7 and the bias circuits BCO and BCI of the column switches cswo to C3W3 will be described in detail later.

Column address decoders CADO and CADI are supplied with complementary internal address signals yO to y1 excluding the most significant bit from column address buffer CAB, and are supplied with timing signal φy and internal control signal tm from timing generation circuit TG. Ru. Here, the timing signal φ
y is normally set to a low level, and set to a high level at a predetermined timing when the dynamic RAM is placed in a selected state. Furthermore, the internal control signal Lm is of a dynamic type R
When AM is selected in multi-bit test mode, it is selectively set to high level.

Column address decoders CADO and CAD 1 may be column address decoders C in FIG. 5, although they are not particularly limited.
As represented by ADO, n+1 NOR gate circuits N001 to N0G3 receive lower complementary internal address signals ayO to ayk in corresponding negative logic combinations.
and the upper complementary internal address signal a yk+1=a y
m + which receives i-1 by a combination of corresponding positive logics
Each of the circuits includes one Nant gate circuit NAGI to NAG3.

Among these, the output signals of the NOR gate circuits N0CI-NOG3 are used as internal selection signals dsQ-dsn to output signals from the NOR gate circuits NAG1-NAG9 to NAGIO corresponding to 9J.
- are respectively supplied to the first input terminals of NAG12.

This is 47. The internal selection signals dsQ to dsn are the non-inverted internal address signal ayQ supplied in the corresponding combination.
~ayk or inverted internal address signal ayQ-ayk are all set to low level, alternatively set to high level. At this time, internal selection signals dsQ-wdsn are provided as selection signals for selectively selecting corresponding complementary data lines from each sub-memory array of memory arrays MARYO-MARY3.

On the other hand, the output signals of the Nantes gate circuits NAGI-NAG3 are respectively supplied to one input terminal of the corresponding Nantes gate circuits NAG4-NAG6. The other input terminals of these Nant gate circuits NAG4 to NAG6 are commonly supplied with an inverted signal of the internal control signal tm by the inverter circuit N3, that is, an inverted internal control signal Lm.

The output signals of the Nante gate circuits NAG4 to NAG6 are used as internal selection signals asQ-wasm to output signals from the corresponding Nant gate circuits NAG7 to NAG9 to NAGIO to NAGIO.
They are commonly supplied to second input terminals of AG12. The internal selection signal asQ-asm is the non-inverted internal alarm signal ayk+1 to ayi-1 or the inverted internal address supplied in the corresponding combination when the output signals of the corresponding Nant gate circuits NAGI to NAG3 are set to low level. (When the M number ay k+ 1 to ay;-t are all set to high level, they are alternatively set to high level. At this time, the internal selection signal asQ-asm is set to the submemory of the memory array MARYO-MARY3. Array SM OO~SM Om~5M30~5M3m
It is provided as a selection signal for selecting one sub-memory array from among the sub-memory arrays. When the dynamic RAM is put into the multi-bit test mode and the internal control signal Lm is set to high level, the internal selection signals asQ to asm are set to high level all at once. As a result, the memory array M
A total of 2x(m+1) sets of complementary data lines, two sets each from all sub-memory arrays of ARYO-MARY3, are simultaneously selected.

Nant gate circuit NAG7 to NAG9 or NAGIO
The timing signal φy is commonly supplied to the third input terminals of ~NAG12. The output signals of these Nant gate circuits are inverted by corresponding inverter circuits N4 to NG to N7 to N9, and then outputted to the data line selection signals YOO"YOn-1 to YmO to Ymn, respectively.
-1, the corresponding memory array MARYO, MAR
YI or MARY2. Supplied to MARY3. Needless to say, the data line selection signals Y00 to YOn-1 to YmO-Ymn-1 are set when the timing signal φy is at a high level when the corresponding internal selection signals dsQ to dsn and asQ to asm are both at a high level. It is selectively set to a high level under certain conditions.

That is, when the dynamic RAM is brought into the selected state in the normal operation mode, the data line selection signals YOO to YO
n-1 to YmO to Ymn-1 are set to complementary internal address signals ayQ to Ymn-1 when the timing signal φy is set to high level and the internal control signal tm is set to low level.
It is alternatively set to high level according to ayi-1. As a result, two sets of corresponding complementary data lines are selected from memory arrays MARYO-MARY3 and connected to complementary common data edges DO/CDI to CD6-CD7, respectively. On the other hand, when the dynamic RAM is selected in the multi-bit test mode, the data line selection signal YOO"YO
n-1 to YmQ-Ymn-1 are the lower complementary internal address signals ayQ-ayk when both the timing signal φy and the internal control signal [m are set to high level.
Accordingly, each m+1 signal goes high at the same time and becomes a bell. As a result, a total of 2×(m+
1) Complementary data lines of the string are selected, and m+1 pairs of corresponding complementary common data IjlCDO-CDI to -C are connected to 6 and CD7, respectively.

Column address buffer CAB connects external terminals AO to Ai
Y address signal AYO” supplied in a time-division manner via
AYi is taken in and held in accordance with the timing signal φaC supplied from the timing start circuit TG. Also,
Based on these Y address signals AYO=AYi, H+
A 1-bit complementary internal address signal yyo-yi is formed.

Of these, although not particularly limited, the complementary internal address doubler ayi of the most significant bit is supplied to the array selection circuit ASL, and the other complementary internal address signals ayQ to ayj-1
is supplied to the column atlas decoders CADO and CADI.

The array selection circuit f23AsL decodes the complementary internal address signals axi-1, axi, and ayi supplied from the row address buffer RAB and column buffer CAB, and alternatively sets the selection signals sO to s7 to a high level. . These selection signals sO to s7 are
The signals are respectively supplied to the corresponding main amplifiers MA O-MA 3.

Complementary common data line temperature Do-andD1~danD6・2D7 is,
Corresponding main amplifier switching circuit M S W O ~ MSW
3 to corresponding main amplifiers MAO-MA3, respectively. Main amplifier switching circuit MSWO~M
The internal control signal tm and the timing signals φce and φy are supplied to the S W 3 from the timing generation circuit TG. In addition, the above power ram address 2, buffer CA
The main amplifier MAO-MA3, which is supplied with the complementary internal address signal ayi of the most significant bit from B, is supplied with timing signals φW and φ" from the timing generation circuit TG, and the corresponding selection signal is supplied from the array selection circuit ASL. The signals SO.Sl to s6.s7 are respectively supplied in combination.Here, the timing signal φW is temporarily set to a high level at a predetermined timing when the dynamic RAM is in the selected state in the write mode. .

Further, the timing signal φr is set to a high level at a predetermined timing when the dynamic RAM is in a selected state in a read mode.

The main amplifier switching circuits MSWO to MSW3 are each composed of a pair of P-channel MO3FET and an N-channel MO3FET, although not particularly limited, as shown in the main amplifier switching circuit MSWO in FIG.
A P-channel MOS F comprising two transmission gates TG1 to TG12, respectively, and constituting these transmission gates.
The ET and N-channel MO3FET are designed to have a relatively large conductance that does not affect the level of the signal transmitted via the complementary common data line, although this is not particularly limited. The transmission gates TG1 to TG4 and TG5 to TG8 are supplied with the internal control signal (m) and its inverted signal by the inverter circuit N2, that is, the inverted internal control signal tm, in a predetermined combination. Also, the transmission gates TG9TGIO and TGI1 .TGI2 is supplied with a non-inverted internal address signal ayi or an inverted internal address signal ay+ in a predetermined combination.As a result, transmission gates TGI to TG4 are dynamic RAM
is the normal operation mode and the above internal control (No. N trr+
The transmission gates TG5 to TG8 are selectively brought into a transmission state when the dynamic RAM is in a multi-bit test mode and the internal control signal Lm is brought to a high level. Ru. Similarly,
Transmission gates 1-TG9 and TGIO are selectively put into a transmitting state when complementary internal address signal ayi is set to logic "0", and transmission gates TGII and TGI2 are set to a transmitting state when complementary internal address signal ayi is set to logic "1". It is selectively put into the transmission state when

For these reasons, when the dynamic RAM is in the normal operation mode and the internal control signal Lm is set to low level, the complementary common data lines CDO/CDI to CD6-CD7 are connected to the corresponding main amplifier switching circuit MSWO-
It is connected to the non-inverting input terminal + and the inverting input terminal - of the read amplifiers RAO and RAl of the corresponding main amplifier MAO-MA3 via the transmission gates TOI to TG4 of the MSW3, respectively. On the other hand, when the dynamic RAM is in the multi-bit test mode and the internal control signal Lm is set to high level, the complementary common data line CD0-
Only one of CD6 and D7 is selected according to the complementary internal address signal ayi. At this time, the non-inverted signal line of the selected complementary common data line is connected to the transmission gates TG5 and T of the corresponding main amplifier switching circuits MSWO to MSW3.
Corresponding main amplifier MA via G9 or TGII
-0 to MA3 are connected to the non-inverting input terminals of read amplifier RAO. In addition, the inverted signal line of the selected complementary common data line is connected to the corresponding main amplifier switching circuit MSWO~
MSW3 transmission game 1-TG7 and TGIO or TGI2
are connected to the non-inverting input terminals of the read amplifiers RAI of the corresponding main amplifiers MAO to MA3. A predetermined reference potential Vr is supplied to the inverting input terminals of the read amplifiers RAO and RAI through the transmission gates 1-TC; 6 and TG8 of the corresponding main amplifier switching circuits MSWO-MSW3.

By the way, the main amplifier switching circuits MSWO-MSW3 each include a constant voltage generating circuit VRG for forming the reference potential ■r, although not particularly limited. N-channel MOSFETs Q30 and Q31 are connected in series between the power supply voltage and ground potential of
Each includes four N-channel MOSFETs Q32 to Q35 provided in series between the commonly coupled sources and drains of TQ30 and Q31 and the above-mentioned common source line CN. Here, MO3FETQ30 is the bias circuit BC of the column switches cswo-cSW3.
Designed to have the same electrical characteristics as MOSFETQ22 to Q25 contained in O and BCl, MO3FET
Q31 is designed to have the same electrical characteristics as MO3FETs Q26 to Q29 included in the bias circuits BCO and BCl. Furthermore, MO5FETQ32 and Q33 are the column switches csw.

~C3W3 switch MO3FETQI8・Q19~
MO3FETQ34 and Q35 are designed to have the same electrical characteristics as Q20, Q21, etc.
It is designed to have the same electrical characteristics as Q15, Q16, Q17, etc.

MO5FETQ30 has its gate and drain commonly coupled to form a diode form.

The timing signal φce is supplied to the gate of MOSFETQ31, and the timing signal φy is commonly supplied to the gates of MOSFETQ32 and Q33. The gates of MO3FETs Q34 and Q35 are commonly coupled and further coupled to the circuit power supply voltage. MO3FET
The potential of the commonly coupled sources and drains of Q30 and Q31 is set to the reference potential ①.

For these reasons, the reference potential Vr is set to the timing signal φca when the dynamic RAM is in a non-selected state.
and φy are set to low level, MO3FETQ3
1 and MOS FETQ32 and Q33 are turned off, MO5FETQ is removed from the circuit power supply voltage.
A predetermined precharge level is obtained by subtracting a threshold voltage of 30. When the dynamic RAM is selected and the timing signals φce and φy are both set to high level, the MO3FETs Q31, Q32, and Q
33 is turned on. As a result, the reference potential Vr
is a predetermined level substantially determined by the ratio of the combined conductance of MO5FETQ32 to Q35 and the conductance of MO3FETQ30.

As described above, when the dynamic RAM is in the non-selected state, the non-inverted signal line and the inverted signal line of the complementary common data lines CDO to C-D7 are connected to the corresponding column switch C3.
Corresponding bias circuit BCO or BC of WO-C3W3
Precharged by I. These precharge levels are determined by the response of the corresponding column switches cswo to C3W3 when the dynamic RAM is selected in the normal read mode and the designated complementary data line is alternatively connected. Switch MO3FE
TQ18, Q19 to Q20-Q21, etc. and corresponding MOS of the corresponding N-type sense amplifier 5ANO-3AN3
One of them is selectively pulled out via FETs Q14, Q15 to Q16, Q17, etc., and set to a predetermined low level. At this time, the low level of the complementary common data line drawn out is the MO3FET QI8 and Q14 to Q
20 and Q16 or the above MO3FETQ19 and Q
15 to Q21 and Q17, etc., and the corresponding bias circuit BCO or BCl MO3FET
It is determined by the ratio with the conductance of Q22 to Q25. As mentioned above, MO3 of the constant voltage generation circuit VRG
FETQ30 and MO5FETQ32 and Q33 and MO3FETQ34 and Q35 are column switch cs
lol.

~ C3W3 bias circuit BCO or BCI MO3F
ETQ22~Q25 and switch MO3FETQ1B/Q
19~Q20, Q21 etc. and N type sense amplifier 5A
MOSFETQ14/Q15~Q16 of NO-5AN3
・Designed to have the same electrical characteristics as Q17 etc. As a result, the reference potential Vr when the dynamic RAM is in the selected state is substantially at an intermediate level between the precharge level of the complementary common data line and the low level of the drawn complementary common data line, that is, the normal readout level. In this mode, the level is approximately intermediate between the high level and the low level of the read signal output to the complementary common data line.

The main amplifier MA O-MA 3 includes, but is not particularly limited to, two write amplifiers WAO and WAI, and two read amplifiers RAO and RAl, as represented by the main amplifier MAO in FIG. , the input terminals of the write amplifiers WAO and WAI are connected via the write common data line WCD, although not particularly limited.
It is commonly coupled to the output terminal of the data input cover sofa of the data input/output circuit I10, and its output terminal is connected to the corresponding complementary common data DO\CDI to D6-g-D7.
are respectively combined. In addition, as described above, the input terminals of read amplifiers RAO and RAI are connected to the corresponding complementary common data lines CDO/DanDI to -CD6/- via the corresponding main amplifier switching circuits MSWO to MSW3.
9-D7 or the reference potential Vr in a predetermined combination.

In this embodiment, the read amplifiers RAO and RAI are connected to an output terminal ao from which an output signal is output at a normal logic level, and another output terminal that can be connected directly to an output terminal ao, which can be configured as a wired logical sum, although this is not particularly limited. Equipped with wo. The output terminals ao of the read amplifiers RAO and RAI are each supplied to a pair of input terminals of a correspondingly provided exclusive OR circuit EO1, although this is not particularly limited. Furthermore, the output terminals wo of the read amplifiers RAO and RAI are commonly coupled to the input terminal of the data output buffer of the data input/output circuit I10 via the read common data line RCD. The output signal of the exclusive OR circuit EOI of main amplifier MA O-MA 3 is the test output signal toQ
~Lo3 is supplied to the test logic circuit TL.

The above timing signal φW is commonly supplied to the write amplifiers WAO and WAI of the main amplifiers MAO to MA3, and the corresponding selection signal 5Q-s is supplied from the array selection circuit ASL.
1 to S6 and S7 are respectively supplied. Similarly, lead amplifiers RAO and R of main amplifiers MAO to MA3
The timing signal φr is commonly supplied to AI,
The corresponding selection signal 5 (lsl
S6 and S7 are respectively supplied. Here, the selection signal 5O-sl is normally set to a low level, although it is not particularly limited, and when the dynamic RAM is in the selected state in the normal operation mode, the selection signal 5O-sl is
It is alternatively set to a high level according to i-1, soil xi, and soil y1. When the dynamic RAM is selected in the multi-bit test mode, the selection signal 5Q=s7 is
Regardless of the complementary internal address signals, they are all set to high level.

The write amplifiers WAO and WAI of the main amplifiers MAO to MA3 are selectively brought into operation by the timing signal φW being set to high level and the corresponding selection signals SO to S7 being set to high level at the same time. In this operating state, the write amplifiers WAO and WAI are in phase mode according to the write data supplied from the data buffers of the data input/output circuits 2 and /Q via the write common data line WCD. j! Form the i write signal and write the corresponding complementary common data ENRIDO/Dan DI or -CD6/Dan D7.
Communicate to each person.

In the read amplifiers RAO and RAI of the main amplifiers MAO to MA3, when the dynamic RAM is in the normal read mode, the timing signal φ" is set to high level, and at the same time, the corresponding selection signals 5Q-S7 are alternatively set. By being set to a high level, it is selectively put into an operating state.In this operating state, read amplifiers RAO and R
AI is the corresponding memory array MARYO-MARY3
The binary read signal output from the selected memory cell through the corresponding complementary common data line -CDO/-CDI or D6/D7 is further amplified, and the data is input/output via the read common data line RCD. It is transmitted to the data output buffer of circuit I10.

When the dynamic RAM is in the multi-bit test mode, the corresponding complementary common data line temperature Do is applied to the non-inverting input terminals of the read amplifiers RAO and RAI, as described above.
, DanD2. DanD4. D6 or CD1. CD3. DanD5. A non-inverting signal line and an inverting signal line of D7 are connected to each other, and a predetermined reference potential V is connected to the inverting input terminal.
r is commonly supplied. At this time, lead amplifier RAO
and RAI is a difference for comparing the signal levels of the non-inverting signal line and the inverting signal line of the complementary common data line coupled to the non-inverting input terminal and the reference potential supplied to the inverting input terminal -. Functions as a dynamic amplifier circuit.Read amplifier R
The output signals ao of the AO and RAI are set to a logic low level, for example, when the level of the non-inverted signal line or the inverted signal line of the corresponding complementary common data line is lower than the reference potential ■r,
Conversely, when it is higher than the reference potential Vr, it is set to a logic high level. If the result of the multi-pint test of the dynamic RAM is normal, the output signals ao of the read amplifiers RAO and RAI are set to a high level or a low level in a complementary manner, as will be described later. Therefore, the output signal of the exclusive OR circuit EOI, that is, the test output signal toQ to to3
4×(m
It can be confirmed that all +1) memory cells are normal.

The test logic circuit TL is supplied with the test output signals toQ to to3 from the main amplifiers MAO to MA3, and is also supplied with the internal control signal Lm from the timing generation circuit TG.

The test logic circuit TL is selectively put into an operating state when the dynamic RAM is placed in a multi-bit test mode and the internal $lJ control signal tm is set to a high level. In this operating state, the test logic circuit 'rL selectively sets its output signal, that is, the error detection signal te, to a low level or a high level in accordance with the test output signals tQQ to to3. That is, when all of the test output signals toQ to to3 are set to a high level, the test logic circuit TL sets the error detection signal te to a low level, although not particularly limited, to indicate that the result of the multi-bit test is normal. .

When any of the test output signals L o Q to 3 is set to low level, the test logic circuit TL sets the error detection signal Lc to the c level, indicating that the result of the multi-bit test is not normal. indicate. error detection signal te
is supplied to the data input/output circuit I10.

The data input/output circuit I10 includes, but is not particularly limited to, a data manual buffer and a data output buffer.
The timing signal φoe is supplied from the test logic circuit TL, and the error detection signal [e is supplied from the test logic circuit TL. Here, the timing signal φoe is normally set to a low level, although it is not particularly limited, and is temporarily set to a high level at a predetermined timing when the dynamic RAM is selected in the read mode.

The data input/output circuit I/O data manual buffer is
The write data supplied through the dynamic RAM fJ (data input terminal 1 when set to f write mode)in is taken in and held.

These write data are written on the hot common data line vv
The three write amplifiers WAO and WAI are commonly supplied to the main amplifier MAO-M through the co. on the other hand,
When the dynamic RAM is in the read mode, the data output buffer of the data input/output circuit I10 operates as follows by setting the timing signal φoe to high level.
Selectively activated. In this operating state, the data output buffer outputs read data supplied from the read amplifiers RAO and RAI of the main amplifiers MAO to MA3 via the read common data line RCD to the outside via the data output terminal DouL. When the dynamic RAM is placed in the multi-pint test mode and the error detection signal to is set to a high level because the test result is normal, the data output buffer puts its output in a high impedance state.

The timing generation circuit TG forms the above-mentioned various internal control signals and timing signals in accordance with the row address strobe signal page enable signal WE, refresh control No. 12 RF and test mode No. f8 TM supplied as control signals from the outside, Supplies each circuit.

FIG. 3 shows an equivalent circuit diagram of an embodiment of the readout circuit of the dynamic RAM shown in FIG. Further, FIG. 4 shows a signal waveform diagram of one embodiment of the readout circuit of FIG. 3 in a normal readout mode and a multi-bit test mode.

Note that FIG. 3 shows a memory array MARYO, a corresponding N-type sense amplifier 5ANO, and a column switch cs.
wo, main amplifier MAO and complementary common data line CDO
A readout circuit consisting of is exemplarily shown. Further, in FIG. 4, a complementary common data line -g-Do corresponding to the memory array MARYO is illustratively shown, and its non-inverted signal line CDO is shown as a solid line, and the inverted signal line σr below is shown as a dotted line. shown. In FIG. 4, the vertical axis shows the signal level V of each signal line, and the horizontal axis shows the passage of time. Below, sub memory array S M of memory array MARYO
The dynamic type R of this embodiment is taken as an example where the respective top complementary data lines DOO-DOO to DmO and DmO in 00-SM Om are all set to the selected state at the same time.
An overview of the AM multi-bit test mode will be explained.

The multi-pint test mode of the dynamic RAM of this embodiment is not particularly controlled, but first the memory array MARY
From O-MAR'/3, m+1 (1!l, a total of 4x(rn+1) memory cells are set to the selected state at the same time, and after writing the same test data, these memory cells are set to the selected state again. Note 1.a Data is read (this is done by outputting it now). During the write operation in the multi-bit test mode, the m + i + a memory cells selected from each memory array are connected to the corresponding main amplifier MAO. ~MA3 light amplifier WAO or WAI
A complementary heat input signal corresponding to the test data is supplied from the test data through the corresponding complementary common data lines -CDO/DI to -CD6/-CD7. When the read mode of the multi-bit test mode is started, the m + 1 memory cells are again selected and connected as shown in FIG.

In FIG. 3, the non-inverted signal line CDO of the complementary common data line temperature DO is connected to the switch MO3 of the column switch cswo.
FETQ18 to Q20 etc. and N type sense amplifier 5A
Via NO MO3FET QI 4 to Q16 etc.
Coupled to common source line CN. Similarly, inverted signal line C
101 is the column switch cswo switch MO3FE
TQI 9 to Q21 etc. and N type sense amplifier 5AN
It is coupled to the common source line CN via the MO3FETs QI5 to Q17 and the like. The common source line CN is coupled to the ground potential of the circuit via the driving MO3FET QI1. When the dynamic RAM is in multi-bit test mode, MO3 of column switch c s w o
FETQ1fl to Q21 etc. are turned on all at once, and N
Type sense amplifier 5ANO MO3FETQI 4・Q1
5 to Q16, Q17, etc. are the corresponding complementary data lines DO
Each of O-DOO-Dmo-DmO is turned on in a complementary manner according to the logic level of the read signal.

The field inversion signal line CDO of the complementary common data line ΩDO is further connected to the inversion input terminal 10 of the read amplifier RAO of the main amplifier MAO via a main amplifier switching circuit @MSWO (not shown). In addition, column switch csw
It is coupled to the power supply voltage of the circuit via the MO5FETQ22 of the bias circuit BCO of 0, and to the ground potential of the circuit via the MO3FETQ26. Similarly, inverted signal line C
10 is connected to the non-inverting input terminal of the lead amplifier RAI of the main amplifier MAO via a main amplifier disconnection circuit MSWO (not shown). In addition, bias circuit BC
It is coupled to the power supply voltage of the circuit through the MO3FET Q24 of O, and to the ground potential of the circuit through the MO3FETQ28.

The inverting input terminals of read amplifiers RAO and RAI have
Constant voltage generation circuit V R of main amplifier switching circuit MSWO
A predetermined reference potential Vr is commonly supplied from G. Constant voltage generation times 1i! 8VRG is a MOS FET' connected in series between the power supply voltage and ground potential of the circuit.
Q30 and Q31, 41 M+') SFE's provided in series between the commonly coupled sources and drains of these MOSFETs and the common source line CN.
Contains rQ32 to Q35.

Here, as described above, the MOSFET Q30 is designed to have the same electrical characteristics as the MO3FETQ22 and Q24 of the bias circuit SCO,
MO3FETQ31 is MO3FETQ26 and Q28
designed to have the same electrical characteristics as Also, M
O3FETQ32 and Q33 are
Thousand CS W (l(7) M OS F E T Q
MO3FETQ34 and Q35 are designed to have the same electrical characteristics as L8~Q21 etc., and MO3FETQ34 and Q35 are designed to have the same electrical characteristics as L8~Q21 etc.
It is designed to have the same electrical characteristics as TQ17 etc.

For these reasons, the non-inverted signal line CDO and the inverted signal line CDO are connected to the dynamic RAM7! l'When the egg selection state is set, MO3FETQ of the bias circuit BCO
The MO3FET Q22 and Q24 are precharged to a predetermined precharge level obtained by subtracting the threshold voltage of the MO3FET Q22 or Q24 from the circuit power supply voltage.

When the dynamic RAM is selected in the normal read mode and the timing signal φy is set to high level, the corresponding data line selection signals Y00 to YOn-1 or YmO to Ymn-1 are alternatively set to high level. Then, the switch Mo5FETQ1 of the column switch C3WO
8.Q19 to Q20.Q21 etc. are alternatively turned on. At this time, when a read signal of logic "1" is output from the memory cell coupled to the selected complementary data line, the N-type sense amplifier 5ANO selects the corresponding MO5F
ETQI 5 to Q17, etc. are selectively turned on. Therefore, the inverted δ side line CDO of the complementary common data line CDO is connected to the corresponding pair of MOSFE′rQ19 and Q
15 through Q21, Q17, etc. As a result, the inverted signal line 〒1 is as shown in Fig. 4(a).
A corresponding set of MO3FETQ19 as shown in
and the combined conductance of Q15 to Q21 and Q17, and the MOS FETQ2 of the bias circuit BCO.
It is set to a predetermined low level determined by the ratio with the conductance of 4. The non-inverted signal line CDO holds the precharge level.

By the way, MO3FETQ30 of constant voltage generation circuit VRG
and Q31 are M of the bias circuit BCO as described above.
Designed to have the same electrical characteristics as O3FETQ24 and Q28, respectively, and MO3FETQ32 and Q3
3 and Q34 and Q35 are the above MO3FETQI
9 to Q21, etc. and Q15 to Q17, etc., are designed to have the same electrical characteristics, respectively. Therefore, the commonly coupled sources and drains of MO3FETQ30 and Q31 are substantially
2 to Q35, that is, the MO3FET that constitutes the discharge path of the inverted signal line CDO.
It is coupled to the common source line CN through conductances corresponding to half of the MO3FETs Q19 to Q21, etc. and MO3FETs QI5 to Q17, etc. As a result, the reference potential Vr is approximately halfway between the precharge level of the non-inverted signal line CDO of the complementary common data line CDO and the low level after discharge of the inverted signal line CDO, as shown in FIG. 4(a). In other words, the level is approximately intermediate between the high level and the low level of the read signal output to the complementary common data line CDO in the normal read mode.

When the dynamic RAM is selected in the multi-pin 1 to test mode and m+1 sets of complementary data lines DoO, DOO-DmO-DmO of the memory array MARYO are connected to the complementary common data line CDO, the non-inverted signal line Either CDO or inverted signal line CDO is selectively discharged according to the read signal of these complementary data lines. That is, for example, the complementary data line DOO-DOO-
When the read signals of DmO and DmO are all logic "1", as shown in FIG. 4(b), the inverted signal line C
DO is discharged through m+1 sets of MO5FETs Q19 and Q15 to Q21 and Q17!4,
It is set to a relatively low low level corresponding to the combined conductance of these MOSFETs. At this time, the non-inverted signal line CDO holds the precharge level. As a result, the output signal ao of the read amplifier RAO is set to a logic high level, and the output signal ao of the read amplifier RAI is set to a logic low level, so the output signal of the exclusive OR circuit EOl, that is, the test output signal toQ becomes a high level. Become.

At this time, the complementary data lines DOO・DOO~DmO・
When an abnormality occurs in a memory cell or the like connected to one of D m O and its read signal becomes logic "0", as shown in the fourth EiU (c), the inverted signal line 5] becomes MO3FETQI 9 and Q15 to Q21 and Q
The non-inverting signal line CDO is discharged through m MOSFETs among the 17 etc.
It is discharged via TQ1B and any one of Q14 to Q20 and Q16. Therefore, the inverted signal line CDO is set to a slightly higher low level than in the above-mentioned Masatomi case, and the non-inverted signal line CDO is set to the same low level as in the normal read mode. the result,
The output signals aO of read amplifiers RAO and RAI are both at logic low level, and exclusive logic homology E! The output signal of 8EO1, that is, the test output signal LoQ becomes low level.

On the other hand, dynamic RAM is selected in multi-focus test mode! When the m+1 sets of complementary data lines DOO, DmO, and Dm of the memory array MARYO are connected to the complementary common data line -CDO, for example, when reading these complementary data lines [signs are all logic " 0°, as shown in fpS4 diagram (d), non-inverted iJ+tXcoo is discharged through m+1 sets of MO3FETs Q1B and Q14 to Q20 and Q16, etc., and the combined conductance of these MO3FE!, T The corresponding relatively low level is set to a low level. At this time, the inverted signal line CDO is set to a relatively low low level.
Stunned! Ki. As a result, the output signal ao of the read amplifier RAO is set to a logic low level, and the output signal ao of the read amplifier RAI is set to a logic high level.
Q becomes a high level.

At this time, the complementary data 1jlDOO・DOO~D
When an abnormality occurs in a memory cell or the like connected to either IlI O or D m O, and the read signal is set to logic "1", the non-inverted signal line CDO is MO3FETQ18 and Q14 or Q
The inversion signal line CDO is discharged through the m-channel MOSFETs such as 20 and Q16, and the inverted signal line CDO is
O3FETQI 9 and Q15 to Q21 and Q17
It is discharged via either of the following. Therefore, the non-inverted signal line CDO is set to a low level slightly higher than that in the normal case, and the lower level of the inverted signal line ττ is set to the same low level as in the normal read mode. As a result, the output signals ao of read amplifiers RAO and RAl
are both at logic low level, exclusive OR circuit EO
The output signal of I, that is, the test output signal toQ becomes low level.

As described above, the test output signal toQ of the main amplifier MAO is supplied to the test logic circuit TL together with the test output signals tol to t03 of the other main amplifiers MAL to MA3, and the error detection signal te is selectively formed. . As a result, the dynamic RAM of this embodiment can test the multi-bit function of a total of 4x(m+1)fl memory cells that are simultaneously selected. It is assumed that this can be done.

As mentioned above, the dynamic RAM of this embodiment? ,
t, 4 (7) memo +/7 tz i MARYO-MARY
3, and corresponding to these memory arrays, 2 each.
A total of 8 sets of complementary common data Entate DO・
The complementary common data lines of each column, including DI to -c-D6 and D7, are connected to the corresponding main amplifier switching circuit MSWO.
- Via MSW3, the corresponding main amplifier MA O -
When the dynamic type RA which is selectively connected to the write amplifiers WAO and WAI of MA 3 and the read amplifiers RAO and RAI, respectively, is set to the multi-byft 1 type T moxibustion mode, the complementary common data line -ICDO-, CD
7, m+1 sets of complementary data lines are simultaneously set to the selected state. At this time, the pair of complementary common data lines -
9DO.D1 to D6.-CD7 are selectively connected to corresponding main amplifiers MAO to MA3. Therefore, the lead amplifier RAO and RAI of each main amplifier
The non-inverting signal line and the inverting signal line of the selected complementary common data line are connected to the non-inverting input terminal of W?, respectively. continued,
A predetermined reference potential Vr is commonly supplied to the inverting input terminal -.

The read amplifiers RAO and RAI of each main amplifier compare the levels of the non-inverted signal line and the inverted signal line of the selected complementary common data line with the reference potential Vr, and selectively set the output signal aO to a high level. . lead amplifier RAO
and RAI output signal ao is output from exclusive OR circuit EOI
and its output signal, that is, the test output signal toQ
-to3 is further supplied to the test logic circuit TL. As a result, the lead amplifier RAO of either main amplifier
The output signal of the test logic circuit TL, that is, the error detection signal t, on the condition that the output signal aO of the test logic circuit TL and the output signal aO of the RAl are both at a high level or a low level.

is selectively set to a high level, and it is displayed that an abnormality has occurred in one of the 4X(m+l) memory cells that are simultaneously selected. For this reason, the dynamic RAM of this embodiment can be used without sacrificing its high integration.
The number of bits of the multi-bit test function can be increased to 4x(m+1) pins. This reduces the cost of testing a dynamic RAM with a large capacity, and promotes cost reduction.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a large-capacity dynamic RAM having a multi-bit test function, the following effects can be obtained. That is, (1) in a multi-bit test mode for dynamic RAM, etc., a plurality (m+1) sets of +\J complementary data lines are connected to the complementary common data line at the same time, and the non-inverted signal line of the complementary common data line is connected. By comparing the levels of the non-inverted signal line and the inverted signal line with a predetermined reference potential, it can be said that the level of either the non-inverted signal line or the inverted signal line is higher than the reference potential. By determining whether either the line or the inverted signal line remains at a predetermined precharge level, it is easy to ensure that the read signals of multiple complementary data lines that are connected are at the same logic level. This has the effect of being able to be identified.

(2) According to the above item (11), the number of bits in the multi-bit test mode can be increased without adding complementary common data lines, main amplifiers, etc., that is, without sacrificing high integration of dynamic RAM, etc. This effect can be obtained.

(3) In the above item (1), the dynamic RAM includes a plurality of complementary common data lines (p
) memory array, dynamic type R
Further increase the number of bits in multi-bit test modes such as AM by pX(
The effect is that the number of bits can be increased to m+i) bits.

(4) In item (3) above, two sets of complementary common data lines and two read amplifiers are provided corresponding to each memory array, and when a dynamic RAM or the like is placed in multi-bit test mode, these By using the read amplifier as a differential amplifier circuit that determines the level of the non-inverted signal line or the inverted signal line of any of the corresponding complementary common data lines, it is possible to further increase the integration of dynamic RAM, etc. This effect can be obtained.

(5) Items ([) to (4) above have the effect of reducing testing costs for dynamic RAMs and the like, and promoting cost reduction.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described above, and various changes can be made without departing from the gist of the invention. Needless to say. For example, in FIG. 1, the memory array M・ARYO-MARY3 may not particularly include a plurality of sub-memory arrays;
P-type sense amplifiers 5APO-3AP3 and N-type sense amplifiers 5ANO-5AN3 may be arranged together in one of the corresponding memory arrays.

The complementary common data line is connected to the memory array M A R”/0
You may provide one set each corresponding to MARY3. Each switch MO3FET constituting the column switches cswo to C3W3 has a pair of P(-Yannel M
It can be replaced by a transmission gate consisting of an O3FET and an N-channel MO3FET. In this case, MO3FETQ32 provided in the constant voltage generation circuit VRG of the main amplifier switching circuits MSWO to MSW3 in FIG.
and Q33 need to be replaced with similar transmission gates. In Figure 2, the main amplifier switching circuit MSWO~
If the conductance of the transmission gates TO1 to TG12 constituting MSW3 cannot be ignored, for example, the transmission gate
It is preferable to provide a transmission gate with the same electrical characteristics as the transmission gates TG9 to TG12 between G6 and TG8 and the constant voltage generation circuit VRG. If both differential amplifier circuits dedicated to the multi-bit test mode can be provided for each complementary common data line, there is no need to provide the main amplifier switching circuits MSW0 to MSW3. The logical OR circuit EOI may be provided together in the test logic circuit 1?1) TL. Also, in the multi-bit test mode, the output of the dynamic RAM is set to high level when the test result is normal. In FIG. 6, in the dynamic RAM, the X address signal A may be set to low level when the
The XO-AXi and Y address signals AYO to AYi may be input from separate input terminals, and the refresh control signal W and the test mode signal f may be, for example, the row address strobe signal RAS and the column address strobe signal. A dynamic RAM, in which a predetermined combination of CAS and write enable signal WE may be substituted, is a memory array MARY as described above.
It may be provided with a plurality of memory mats whose basic configuration is O-MARY3. Furthermore, the specific circuit configurations of the memory array and its peripheral parts shown in FIG. 1, the main amplifier switching circuit and main amplifier shown in FIG. 2, and the column address decoder shown in FIG.
Various embodiments may be adopted, such as the block configuration of the dynamic RAM shown in M and combinations of address signals and control signals.

In the above explanation, we have mainly explained the case where the invention made by the inventors of the present f1 was applied to dynamic type RAM, which is the field of application that formed the background of the invention, but it is not limited thereto. It can also be applied to multi-baud RAMs and other various semiconductor storage devices having a basic configuration of . The present invention is widely applicable to semiconductor memory devices having at least a multi-bin 1-test function and digital devices including such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a multi-bit test mode for dynamic RAM, etc., multiple sets of complementary data lines are connected to the complementary common data line at the same time, and the levels of the non-inverted signal line and the inverted signal line of the complementary common data line are set to a predetermined level. By comparing each with the reference potential, it can be easily determined that the read signals of the plurality of connected complementary data lines are at the same logic level. As a result, there is no need to add complementary common data lines, main amplifiers, etc., or in other words, without sacrificing high integration of dynamic RAM, etc.
Since the number of bits/bits in the multi-bit test mode can be increased, testing costs for large-capacity dynamic RAM can be increased! ? It is possible to reduce J and promote cost reduction.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of the memory array and its peripheral parts, and FIG.
A circuit block diagram showing an example of the main amplifier and main amplifier switching circuit of M is a dynamic RAM to which the present invention is applied.
Fig. 4 is a signal waveform diagram showing an example of the readout circuit of Fig. 3, and Fig. 5 is a dynamic RAM to which the present invention is applied.
Figure 6 shows an example of a column address decoder for a dynamic RAM to which this invention is applied.
It is a blog diagram showing one example of. MARYO~MARY3...Memory array, SMO0
~5M0m --- Sub memory array, 5APO-3AP
3-- ・P-type sense amplifier, 5ANO to 5AN3...
・N-type sense amplifier, C5WO to C3W3...column switch, BCO, BCl...bias circuit. Cs... Capacitor for information K11m, Qm... MOS FET for address selection, N1-N9... Inverter circuit, Q1-Q3... P-channel MO3FE
T, QI I~Q35...N channel MO3FET
. MSWO~MSW3...Main amplifier switching circuit, VR
G... Constant voltage generation circuit, MAO to MA3... Main amplifier, WAO, WAI... Light amplifier, RAO,
RAI...read amplifier, TGI-TGI2...transmission gate, EOI...exclusive OR circuit. CADO, CADI...Column address decoder, N
AGl-NAGl 2...Nant gate circuit, Noah gate circuit N0G1~N0G3...RADO~RAD3
...Row address decoder, RAB...Row address buffer, AMX...Address multiplexer, R
FC...Refresher address counter, CAl3-
...Column address buffer, ASL...Array selection circuit, 1'L...Test logic circuit, Ilo...Data input/output circuit, 1'G...Timing generation circuit.

Claims (1)

[Claims] 1. A complementary common data line to which a plurality (m+1) sets of complementary data lines are connected simultaneously in a predetermined test mode, and a complementary common data line to which one of the input terminals in the test mode is 1. A semiconductor memory device comprising an inverted signal line and first and second differential amplifier circuits connected to the inverted signal line, the other input terminal of which is commonly coupled to a predetermined reference potential. 2. The semiconductor according to claim 1, wherein the reference potential is set to approximately an intermediate level between a high level and a low level of a read signal transmitted to the complementary common data line in a normal read mode. Storage device. 3. The non-inverted output signal or the inverted output signal of the first and second differential amplifier circuits is supplied to an exclusive OR circuit, and the output signal of the exclusive OR circuit is set to a high level. Claim 1 or 2, characterized in that it is provided for determining whether read signals of a plurality of complementary data lines connected to the complementary common data line are all at the same logic level. The semiconductor storage device described above. 4. The semiconductor memory device is a dynamic RAM, and the test mode is a multi-bit test mode that is performed on a plurality of memory cells that are simultaneously selected. The semiconductor memory device according to item 1, item 2, or item 3. 5. The dynamic RAM has a plurality of (p) memory arrays in which the complementary common data lines are provided correspondingly, and simultaneously performs the multi-bit test mode on p×(m+1) memory cells. A semiconductor memory device according to claim 1, 2, 3, or 4, which is capable of being implemented. 6. The complementary common data lines are provided in two sets corresponding to the memory arrays, and the dynamic type R
The AM includes the same number of read amplifiers provided corresponding to the complementary common data lines, and the two read amplifiers provided corresponding to each pair of complementary common data lines are used for the multi-bit test. mode, the circuit selectively functions as the first and second differential amplifier circuits, respectively. The semiconductor memory device according to item 5.