JPH04238193A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed up the cycle time of a DRAM to the time equal to access time. CONSTITUTION:One piece of cell capacity is commonly used by two pieces of cell transistors and two pieces of the cell TRs are respectively connected to different word lines and different data lines. The 1st cell TR T11A is turned on and reading out and rewriting are executed on D1, D2. The reading out and rewriting can be executed again on D1', D2' in parallel with the precharge being executed on the D1, D2 if the T11A is turned off and the T11B is turned on after the large amplitude necessary for rewriting arises on the D1, D2. The cycle time is speeded up to the time equal to the access time in this way.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit configuration of a high-speed DRAM.

0002

2. Description of the Related Art Conventionally, a dynamic random access memory (Dynamic Random Access Memory) equipped with a readout circuit is disclosed in FIGS. DRAM) is used.

0003

BACKGROUND OF THE INVENTION Reading a conventional DRAM typically requires a cycle time twice as long as the access time. For this reason, compared to static random access memory (SRAM), which can equalize the access time and cycle time, DRAM has become unable to adapt to the speeding-up of recent information processing equipment.

[0004] The reason why a DRAM requires a cycle time twice as long as the access time is that rewriting and precharging must be performed every cycle, which takes time. Figure 14 shows a conventional DRAM.
The circuit diagram of the memory cell array shown in FIG. 15 shows the operating waveforms of this one cycle. Let the high level of the cell storage voltage be VD and the low level be VE. In one cycle, first, when a memory cell is selected by the rising edge of a word line, it is precharged to HVD, which is a voltage in which the absolute value of the voltage difference with VE is equal to the absolute value of the voltage difference with VD. A small signal voltage is generated on the data line pair. At this time, the information in the cell is destroyed. Next, the minute signal on the data line pair is amplified to the accumulated voltage amplitude VD-VE of the cell, and the same information as the first time is rewritten into the cell. In parallel with this operation, although not explicitly shown in FIG. 14, a readout output appears at the output terminal Dout. This does not require large amplitude data line to signal voltages. For example, if the circuit configuration disclosed in FIGS. 5 and 6 of Japanese Patent Application Laid-Open No. 61-142594 is used, it is possible to perform this operation using only a small signal from a pair of data lines. After rewriting is completed, the data line pair is precharged to HVD in preparation for the next cycle. In the above cycle, it is necessary to amplify the minute signal of the pair of data lines to a large amplitude cell storage voltage, and then precharge the HVD. This amplification is
Since it is necessary to perform this on all memory cells connected to the data line at the same time, there is a delay due to the wiring resistance delay of the drive signal lines PP and PN.Furthermore, all data line pairs must be precharged to HVD. As a result, the cycle time increases to about twice the access time.

[0005]

[Means for Solving the Problems] The above problems can be solved by the following configuration. Two cell transistors share one cell capacitor, and each of the two cell transistors is connected to a different word line and to a different sense amplifier via a different data line.

[0006]

[Operation] First, the first cell transistor is turned on, and thereby the minute signal generated on the first data line is amplified by the reading circuit, and the signal is outputted to Dout, and rewriting is performed by the sense amplifier. At this time, when the sense amplifier generates a large amplitude for rewriting on the data line and charges are stored in the cell capacitance, the word line voltage is changed to turn off the first cell transistor. After this, precharging is performed to the HVD on the first data line where a large amplitude has occurred, but in the conventional method, the next readout is performed on memory cells belonging to other mats until this precharging is completed. Random access was not possible. However, in the present invention, by turning on the second cell transistor, it is possible to generate and rewrite a minute signal to the second data line connected thereto, which has already been precharged to the HVD. When this second cell transistor is turned off after a large amplitude signal for rewriting is generated on this second data line, this second cell transistor is turned off.
The first cell transistor can be used to read out the same cell while the data line is being precharged. By repeating this process, it is possible to speed up the cycle time in reading any cell to the point where it is equal to the access time.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. In addition, in the following explanation, symbols may be overlaid on the drawings.
Complement signals shown with a line are shown in the text with a / in front of the symbol. Further, unless otherwise specified, signal names serve as both node names and wiring names at the same time.

FIG. 1 shows a first embodiment of the present invention. C1
1 to C4n are cell capacitances, and each cell capacitance has two cell transistors T11A, T11B to T4nA, T
4nB is connected. SA11-SA22 are sense amplifiers, and D1, D1'-D4, D4' are data lines. In the sense amplifier, for example, SA11 has a cell transistor T1 connected to cell capacitances C11 to C1n.
Data line D1 connected to 1A to T1nA and data line D connected to cell transistors T21A to T2nA connected to C21 to C2n.
2 are connected. On the other hand, SA21 has data lines D1' and T21B for the other cell transistors T11B to T1nB connected to the same cell capacitance corresponding to SA11.
It is connected to the data line D2' for T2nB. The same applies to other sense amplifiers. In Figure 1, data lines connected to cell transistors with A at the end, B at the end
The data lines connected to the cell transistors are connected as a pair to one sense amplifier. According to the embodiments of the present invention as described above, the cycle time can be increased to be equal to the access time as shown below. Figure 1
The operation will be explained using the timing diagram of FIG. Let us focus on a memory cell having a cell capacitance C11. Word line W11
goes from low level to high level, and W12 to W14 remain at low level. T11A turns on and a minute voltage is generated on the precharged data line D1. Although not shown in FIG. 1, due to the minute voltage difference between this minute voltage and the precharged D2, the output terminal Dout is Reading is performed to. In addition, sense amplifier S
A11 causes the large amplitude voltage for rewriting to become D1,
D2 occurs, and the original signal is rewritten into the cell capacitor C11. When the rewriting is completed, the word line W11 changes from a high level to a low level, and the cell transistor T11A is turned off. After this, precharging to the HVD level is performed in D1 and D2. In the conventional example, as shown in FIG. 14, the next readout could not be performed on any cell until these series of operations were completed. However, in the present invention, when the word line W11 becomes low level as shown in FIG. 2, the word line W13 is set to high level and the cell transistor T11B is turned on to drain the charge stored in the same cell capacitor C11. Can be read continuously. Reading other cells connected to the same data line can be similarly performed by selecting word lines W23 to Wn3 after turning off word line W11. Of course, this is possible between cells connected to other data lines, and therefore, continuous word line selection is possible between arbitrary cells. As described above, by using the present invention, the cycle time can be increased to be equal to the access time.

Using the present invention, writing and refreshing can similarly be completed in a cycle time equal to the access time. Figure 3 shows the case where reading and writing are continuous.
FIG. 4 shows a case where reading and refreshing are successive.

In FIG. 3, W11 is first selected and C11
is read out. As in the case of FIG. 2, the data lines D1 and D2
When a large amplitude appears at the top, W11 is deselected, W13 is subsequently selected, and writing can be performed to the same cell C11. Thereafter, when writing is completed, W13 is deselected, and in parallel with precharging being performed on D1' and D2', W11 can be selected and the same cell C11 can be read. Although it has been shown above that the process can be performed on the same cell, it can also be performed on cells in any order. The same holds true when writing only continues.

In FIG. 4, W11 is initially selected and C1
When 1 is read out and a large amplitude appears on the data lines D1 and D2, W11 is deselected. Thereafter, while precharging is performed on D1 and D2, W13 can be selected to refresh the same cell. Therefore, it can be performed on cells in any order. The same applies not only to the case where only refresh is performed continuously but also to the case where write and refresh are performed consecutively. Thus, using the present invention,
In all operations of the DRAM, the cycle time can be increased to be equal to the access time.

FIG. 5 shows a second embodiment of the present invention. In this embodiment, a data line connected to a cell transistor whose suffix is ``A'' and a data line which is connected to a cell transistor whose suffix is ``B'' are connected to one sense amplifier. This method requires a dummy data line (for example, DD) for the sense amplifier at the end of each mat, but since adjacent data lines are connected to the sense amplifier, the data line capacitance The feature is that the imbalance is small and malfunctions are less likely to occur.

Note that if the embodiment of FIG. 1 or FIG. 5 is used,
Reading and refreshing, and writing and refreshing can also be performed in parallel. FIG. 6 shows a case in which the embodiment shown in FIG. 1 is used. Although this method requires a cycle time twice as long as the access time, it has the advantage that there is no need to provide a special refresh period.

Next, a method of controlling word line selection in continuous cycle operation will be described. In the selection of memory cells in FIG. 1, for example, in C11, when word line W11 is selected first and then the same cell is selected continuously, W13 is selected in the next cycle. The same applies to normal random word line selection, and the sense amplifiers SA11 and SA1
The cell transistor connected to 2 and the sense amplifier SA
21 and the cell transistors connected to SA22 are alternately selected. Therefore, the word lines must be selected in this order. This function can be easily implemented as shown below. In FIG. 7, a MOS transistor is inserted in series with the MOS transistor to which the normal decode signal AXi is connected and connected to AXs and this via an inverter. A word line W11 is output from the circuit connected to AXs, and a word line W13 is output from the circuit connected via the inverter. For example, W11 is connected to the cell transistor whose end is A in FIG. 1, and W13 is connected to the cell transistor whose end is B. As a result, if AXs is switched high and low every cycle as shown in FIG. 8, W11 is selected when AXs is at a high level, and W13 is selected when AXs is at a low level, so that the desired This means that a word line signal can be generated. That is, N11 and N13 are precharged to VL while XDP is at a low level. When XDP becomes high level, N11 and N13 flow.
It becomes ting. Next, when AXi becomes high level, suppose that AXs becomes high level in the first cycle, then N11
is discharged, and word driver WD11 drives W11. In the next second cycle, AXs remains at a low level, so when AXi becomes high level, N13 is discharged and W13 is driven by word driver WD13. AXs may be generated by applying a clock from outside, or may be generated internally using an address switching detection circuit (ATD).

FIG. 9 shows the sense amplifier section SA1 shown in FIG.
1 to SA22 are shown in detail. Japanese Patent Publication No. 1-155
Part DA of the readout circuit disclosed in FIG. 4 of 589
11 and a precharge circuit DS11 are included inside SA11. PP1 and PN1 are activation signal lines for the sense amplifier. Without waiting for activation of the sense amplifier by this signal line, the DA11 outputs a current signal corresponding to the accumulated charge of the cell to the RO1 and /RO1, which is amplified by the subsequent circuit and becomes the Dout signal. In parallel with this, large amplitude rewriting and precharging are performed by the sense amplifier. This takes time compared to outputting to the Dout signal. However, if the configuration of the present invention specifically shown in FIG. 9 is used, as long as large amplitudes that can be rewritten appear on D1 and D2 after W is selected, W is unselected and W' is selected. This makes reading possible again. This makes it possible to speed up the cycle time to the point where it is equal to the access time.

Furthermore, if the sense amplifiers are shared by adjacent memory cell arrays, the layout area can be reduced. A configuration for this purpose is shown in FIG. In FIG. 10, SA11 and SA12 are both adjacent memory cell arrays.
It is shared by y1 and Ary2, and which memory cell array
The signal line f1 or f2 is selected by the MOS transistor whose gate is connected to the signal line f1 or f2. The same applies to SA21 and SA22, which are switched between f3 and f4.

FIG. 11 shows the overall mat structure. In some cases, only these semiconductor memory devices are arranged on the chip, and in other cases, other logic devices are arranged together. These Ary111 to Ary4n1 are memory cell arrays having memory cells shown in FIG.
-SA4(n+1) are the sense amplifiers shown in FIG. 9, for example, and WD11-WD4n are X decoders and word drivers. PM11 to PM4 (n+1) are preamplifiers, and MA is a main amplifier and output buffer, as shown in Figure 6 of JP-A-62-311945 and JP-A-1-1571.
The one disclosed in FIG. 2 of No. 19 may be used. When an address is input and a selection signal of this chip is input, or when a change in address input is detected, for example, WD1
1 operates and selects a cell in Ary 111 having the same configuration as in FIG. SA11 has the same configuration as in FIG. 9, and the RO in FIG.
1, a read signal is generated on /RO1. At this time, P.M.
11 is selected and the amplified signal is transmitted to MA and becomes the Dout output. In parallel with this, Ary111 in SA11
will be rewritten. As explained above, by using the present invention, in Ary 111, if a large amplitude necessary for rewriting occurs on one end of the data line, the cell transistor connected to it is turned off, and the cell transistor is connected to the same storage capacitor. Reading and rewriting can be performed using the other precharged data line by turning on the other cell transistor. This makes it possible to speed up the cycle time to the point where it is equal to the access time.

FIG. 12 shows an example of the layout of a 6-bit memory cell. W11 to W24 are word lines, D1 to D3'
is a data line, and C11 to C32 are cell capacitances, which correspond to the embodiment shown in FIG. The cell transistor in Figure 1 is as shown in Figure 1.
2, this is the portion where the n-type impurity layer and the word line intersect, marked as a transistor region. One end of the cell capacitor is connected to the transistor region. For this reason, for example, when the word line W11 is selected, the cell capacitance C11 changes to the data line D1.
When word line W13 is selected, one end thereof is electrically connected to data line D1'. By using such a memory cell and using the above-described sense amplifier configuration, it is possible to speed up the cycle time to the same level as the access time.

FIG. 13 is a diagram showing a system configuration using the present invention. Arrows represent signal flow. CPU indicates a processing unit that controls the entire system, RAG indicates a refresh address generator, TC indicates a control signal generator for the storage device section using the present invention, and SLCT indicates an address signal sent from the CPU and from RAG. The select device that switches the refresh address signal sent is M.
shows a DRAM using the present invention. Further, the PFY is another device within the system, such as an external storage device, a display device, a numerical calculation device, etc., and may be connected to other information processing devices through a communication line. DATA is CPU and M
Aic represents the data exchanged between CP and
Air indicates an address signal generated at U, Air indicates a refresh address signal generated at RAG, and Ai indicates an address signal selected by SLCT and sent to M. ST is CP
A status signal is sent from U to RAG, and BS is a busy signal sent from TC to CPU. SE is a signal sent from TC to activate the SLCT, and /CE is a signal to activate the DRAM using the present invention. SG is C
It collectively represents the signal exchange between the PU and other devices in the system. These are exactly the same as in the case of conventional DRAM. The external control signals of the DRAM using the present invention are used in the operation modes shown in FIGS. 2 to 4, and are used in the operation modes shown in FIGS.
When generating the Axs signal in DRAM, the conventional D
It is exactly the same as RAM and does not require any special control signals. Nevertheless, the present invention allows the cycle time to be equal to the access time. By using the present invention, a system requiring high-speed cycle operation of DRAM can be easily constructed without adding any special equipment compared to the case of conventional DRAM.

[0020]

Effects of the Invention According to the present invention, by connecting two cell transistors to one cell capacitor and connecting these cell transistors to different data lines, the first cell transistor is turned on and connected to the first cell transistor. While reading and rewriting are performed by the sense amplifier on the connected first data line, the second data line connected to the second cell transistor maintains a precharge voltage. For this reason,
When a large amplitude that can be rewritten appears on the first data line, the first cell transistor is turned off, the second cell transistor is turned on, and precharging is performed on the first data line. Since data can be read using the second data line, the cycle time can be increased to be equal to the access time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first operation of the present invention.

FIG. 3 is a diagram showing a second operation of the present invention.

FIG. 4 is a diagram showing a third operation of the present invention.

FIG. 5 is a diagram showing a second embodiment of the invention.

FIG. 6 is a diagram showing a fourth operation of the present invention.

FIG. 7 is a diagram showing a word line selection circuit required in the present invention.

FIG. 8 is a diagram showing the operation of the word line selection circuit.

FIG. 9 is a diagram showing a specific configuration of a sense amplifier.

FIG. 10 is a diagram showing a configuration for sharing one sense amplifier with two memory cell arrays.

FIG. 11 is a diagram showing the overall structure of the chip.

FIG. 12 is a diagram showing a layout example of a memory cell according to the present invention.

FIG. 13 is a diagram showing a system configuration using the present invention.

FIG. 14 is a diagram showing a conventional example.

FIG. 15 is a diagram showing the operation of a conventional example.

[Explanation of symbols]

T11A to T4nB...Cell transistor, C11 to C4
n...Cell capacity, SA11-SA4(n+1)...Sense amplifier, D1, D1'-D4, D4', D5...Data line,
W11~Wn4, W, W'...word line, AXi, AXs
...Predecoder signal, XDP...Precharge signal, RO
, /RO, RO1, /RO1, RO2, /RO2...Read signal line, PP, PN, PP1, PN1...Sense amplifier activation signal line, Ary1~Ary3, Ary111~Ar
y4n1...Memory cell array, PM11 to PM4 (n+
1)...Preamplifier, MA...main amplifier and Dout buffer, Dout...output terminal, MC1 to MC8...memory cell, RA1, RA2...rewrite amplifier, DS1, DS
2...Short circuit, DA1, DA2...Readout circuit, HV
D...Precharge voltage line, PC...Short circuit activation signal line, PL...Plate, YS1, YS2...Column selection signal line,
VE...Data line low level, VD...Data line high level, V
CH...word line power supply voltage, CPU...system control device,
PFY...Other devices in the system, RAG...Refresh address generator, TC...Control signal generator, SLCT
...Address select device, M...DRAM using the present invention
.

Claims (2)

[Claims] Claim 1: A memory cell having one terminal of one capacitor shared by two switching elements, and means for independently opening and closing the two switching elements, the memory cell having one terminal of one capacitor shared by two switching elements, A semiconductor memory device characterized in that the other terminal not connected to the capacitor is connected to a different amplifier circuit. 2. The two switching elements read and replay data on a first data line connected to the first switching element when the first switching element is on and the second switching element is off. After writing, when the first switching element is turned off and the first data line is precharged, the second switching element is turned on in parallel with this and the corresponding second data line is turned on. 2. The semiconductor memory device according to claim 1, wherein reading and rewriting can be performed on a data line.