JP3231310B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of performing a precharge operation at high speed.

[Prior Art] A conventional semiconductor memory device will be described with reference to FIG.

In FIG. 4, 41 is a conventional bit line precharge circuit, 42 is a data bus line precharge circuit, 43 is a column switch circuit, 44 is a memory cell, and 45 is a data amplifier circuit. W1 to Wl are word lines, D1, ▲ ▼ to Dn, ▲
▼ indicates n pairs of bit lines and DB, and ▲ ▼ indicates a data bus line pair.

Here, Y1 to Yn are column selection signals for controlling the column switch circuit 43, and φj is a precharge signal for controlling the operation of the precharge circuits 41 and 42. As shown in FIG. 3, the precharge signal φj is a pulse that rises in the negative direction and is issued each time the address input changes.

When the address input changes, the address input change detection circuit detects this change and generates a precharge signal φj which rises in the negative direction. While the precharge signal φj is at “L” level, the precharge signal φ of the bit line precharge circuit 41 and the data bus line precharge circuit 42
p-channel MOS transistor with j as gate input is ON
Then, the bit lines and the data bus lines are precharged to the V _CC level. The bit line and the data bus line are precharged, the precharge signal φj goes to “H” level, and the p-channel MOS transistors of the precharge circuits 41 and 42 are turned off.
After that, the selected word line goes to “H” level and the column selection signal Yi
Is at the “L” level, the bit line pair Di, ▼ above the selected memory cell 44, and the data bus line pair DB, DB through the column switch circuit 43 where the column selection signal Yi is at the “L” level. It is transmitted to ▲ ▼. Data bus line pair DB,
The above information is amplified by the data amplifier circuit 45, transmitted to the output circuit, and output.

[Problems to be Solved by the Invention] In the conventional circuit described above, the bit line precharge circuit and the data bus line precharge circuit are controlled by the precharge signal φj. Therefore, the load capacitance to be driven by the precharge signal φj is the wiring capacitance (C _L ) and the gate capacitance (C _G ) of the p-channel MOS transistors of the bit line precharge circuit and the data bus line precharge circuit. Here, the memory is an m-bit system, and the bit line precharge circuit and the data bus line precharge circuit
Assuming that the gate length of the channel MOS transistor is L, the gate width is W, and the gate capacitance per unit area is C ₀ , the gate capacitance _CG is: C _G = 3 × L × W × C ₀ × (n + 1) × m Become. With the adoption of the word line division method, the number n × m of bit line precharge circuits controlled by the precharge signal φj is about 128 for a 256K to 1M SRAM, and is 128K.
× C _G is about 7pF in 8 bit 1MSRAM.

As described above, in the conventional circuit, since the gate capacitance of the transistor of the precharge circuit among the load capacitances to be borne by the precharge signal φj is very large, the time delay from the change of the address input to the completion of the precharge operation is reduced. The rounding of the waveform of the precharge signal φj occurs, which causes an access delay.

[Means for Solving the Problems] In order to solve the above-mentioned problems, according to the present invention, a precharge circuit controlled by a precharge signal generated from an address change detection circuit is only a data bus line precharge circuit, A large number of bit line precharge circuits include a column selection signal Yi for controlling a column switch circuit connected to the bit line to which the precharge circuit is connected.
Controlled by.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 11 is a bit line precharge circuit, 12 is a data bus line precharge circuit, 13 is a column switch circuit,
14 is a memory cell, 15 is a data amplifier circuit, W1 to Wl are word lines, D1, ▲ to Dn, ▲ are n pairs of bit lines, DB and ▲ are data bus line pairs. Also, Y1 ~
Yn is a column selection signal, and φj is a precharge signal that rises in the negative direction when an address changes.

The data bus line precharge circuit 12 and the column switch circuit 13 are controlled by a precharge signal φj and column selection signals Y1 to Yn generated from the address change detection circuit, respectively, as in the conventional example. While the precharge signal φj is at “L” level, the p-channel MOS transistor of the data bus line precharge circuit 12 having the gate input of the precharge signal φj is turned on, and the data bus line pair DB, ▲
▼ is precharged to the V _CC level. After the precharge signal φj goes to “H” level, the word line corresponding to the selected address goes to “H” level, the column signal Yi goes to “L” level, and the information of the selected memory cell is ,
The data is output via the data bus line, the data amplifier circuit 15, and the output circuit via the column switch circuit 13.

Next, the operation of the bit line precharge circuit 11 will be described.

When the column selection signal Yi is at “H” level, the p-channel MOS transistor of the bit line precharge circuit 11 is turned on, and the bit line pair Di, ▼ is precharged to the _VCC level. When the column selection signal is at "L" level, the p-channel MOS transistor of the bit line precharge circuit 11 is turned off. Since the column selection signal of the non-selected column is at “H” level and the column selection signal of the selected column is at “L” level, each bit line is precharged by the bit line precharge circuit 11 during the non-selection cycle.

The bit line precharge operation when each address changes will be described with reference to the waveform diagram of FIG. In the case illustrated in FIG. 3, the selected column in cycle 1 is column 1,
The selection column in cycles 2 and 3 is column n. Address change from cycle 0 to cycle 1 and cycle 1
The address change from the cycle to the cycle 2 is a change of only the column address or a simultaneous change of the row address and the column address, and the address change from the cycle 2 to the cycle 3 is a change of the row address only.

At the time of an address change including a column address change leading to cycle 1 or cycle 2, the bit line pair of the selected column has already been precharged when it was in the non-selected state in the previous cycle. There is no problem even if Yi goes to “L” level and the p-channel MOS transistor of the bit line precharge circuit 11 is turned off.

When only the row address changes, as in the case of shifting from cycle 2 to cycle 3, the p-channel MOS of the bit line precharge circuit 11 connected to the bit line pair Dn of the selected column and ▲ ▼ Transistor is O
Although it remains FF, the transfer gate of the column switch circuit 13 remains ON, and the bit line pair Dn, ▲
Since ▼ is in conduction with the data bus line pair DB and ▲ ▼, the p-channel MOS transistor of the data bus line precharge circuit 12 is turned on by the precharge signal φj to bring the data bus line pair DB and ▲ ▼ to the V _CC level. When precharging, the bit line pair Dn and n are also precharged to the V _CC level at the same time.

In summary, at the time of an address change including a column address change, the selected bit line pair is precharged by the bit line precharge circuit 11 in a non-selected state during the previous cycle, and when only the row address changes. That is, the selected bit line pair is precharged together with the data line pair by the data bus line precharge circuit 12 via the column switch circuit 13 which remains in the ON state from the previous cycle.

As described above, according to the circuit shown in FIG. 1, the precharge circuit driven by the precharge signal φj is only the data bus line precharge circuit. It is reduced. For example, in the case of a 1 MSRAM having a 128K × 8-bit configuration, the capacitance of the conventional circuit was about 7 pF, whereas the transistor of the data bus line precharge circuit in the circuit of the present embodiment has the same size as that of the data bus line. In preparation for simultaneous precharging of the bit line and the
Even if it is doubled, C _G = 3 × L × W × C ₀ × 2 × m ≒ 0.8 pF.

Furthermore, in the circuit embodiment, the wiring for the precharge signal, the capacitance due to the wiring because it requires the data bus line precharge circuit component only C _L is also greatly reduced.

As a result, the time from the address change to the completion of the precharge can be shortened, and the access can be speeded up.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.
In the figure, 21 is a bit line precharge circuit, 24 is a memory cell, Wl is a word line, Di, ▲ ▼ is a bit line pair,
Yi is a column selection signal. Bit line precharge circuit
In 21, a transistor controlled by a column selection signal Yi and precharging a bit line pair is formed of an n-channel MOS transistor. The circuit operation is the same as in the previous embodiment. The level at which the bit line pair is precharged is V
_CC -V _T (V _T is the threshold voltage of the n-channel MOS transistor) becomes, but can be exemplified the same effect as the previous embodiment.

[Effect of the Invention] As described above, in the precharge circuit according to the present invention, the bit line precharge circuit is controlled by the column selection signal, and only the data bus line precharge circuit is the precharge circuit generated from the address change detection circuit. According to the present invention, since the load capacitance to be driven by the precharge signal is controlled by the charge signal, the gate capacitance (C _G ) of the MOS transistor of the precharge circuit and the wiring capacitance (C _L ) can greatly reduce both. Thus, according to the present invention,
The operation from the address change to the completion of the precharge can be speeded up, and the access can be speeded up. Further, in the conventional circuit, the precharge signal controls the bit line precharge circuit and the data bus line precharge circuit, so that the precharge signal wiring is provided at two places with the cell array interposed therebetween. However, in the present invention, since the precharge signal controls only the data bus line precharge circuit, the area for wiring can be reduced.

[Brief description of the drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, respectively. FIG. 3 is a waveform diagram of pulses used in the embodiment of the present invention and a conventional example. FIG. 4 is a circuit diagram of a conventional example. FIG. 11, 21, 41 ... bit line precharge circuit, 12, 42 ...
Data bus line precharge circuit, 13, 43 ... column switch circuit, 14, 24, 44 ... memory cell, 15, 45 ... data amplifier circuit, φj ... precharge signal, W1 to Wl ...
Word line, D1, ▲ ▼ to Dn, ▲ ▼ ... bit line pair, Y1 to Yn ... column selection signal, DB, ▲ ▼ ... data bus line pair.

Claims (1)

(57) [Claims] A plurality of pairs of data bus lines; a plurality of pairs of bit lines provided for each pair of data buses; a plurality of memory cells provided for each pair of bit lines; First switching means connected between a power line and the bit line provided corresponding thereto and controlled by a column selection signal, and connected between a power supply and the bit line and controlled by the column selection signal; A second switching means for performing a precharge operation by operating complementarily with the first switching means, and being controlled by a precharge signal connected between the data bus line and a power supply and issued from an address change detection circuit; A third switching means, and when an address change including a column address change occurs, the selected bit line pair is forwarded via the second switching means. Are precharged when the non-selected state of the cycle, when only the row address is changed,
A semiconductor memory device, wherein a selected bit line pair is precharged together with the data bus line pair via the first switching means and the third switching means, which remain on from a previous cycle.