JPH03224200A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the access speed by controlling a bit line precharging circuit by a column selecting signal. CONSTITUTION:A bit line precharging circuit 11 is controlled by a column selecting signal Yn which controls a column switch circuit 13 connected to a bit line Dn-Dm to which this precharging circuit 11 is connected. The bit line Dn-Dm is precharged in a non-selection cycle by the precharging circuit 11. Consequently, only a data bus line precharging circuit 12 is driven by a precharge signal phij to reduce the load capacity which the precharge signal phij takes charge of. Thus, the time from the address change to the precharging completion is shortened to increase the access speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can perform a precharge operation at high speed.

[Prior Art] A conventional semiconductor memory device will be described with reference to FIG.

In FIG. 4, 41 is a conventional bit line precharge circuit, 42 is a data bus line precharge circuit, 43 is a column switch circuit, 44 is a memory cell, and 45 is a data amplifier circuit. In addition, w1 to Wg are word lines, Dl, ■
]-~Dn, ■1- is one bit line pair, DB, ITπ
is a data bus line pair.

Here, ¥1 to Yn are column selection signals that control the column switch circuit 43, and φJ is a precharge signal that controls the operation of the precharge circuits 41 and 42. The precharge signal φ] is, as shown in FIG.
This is a pulse that rises in the negative direction every time the address input changes.

When the address input changes, the address input change detection circuit detects this change and generates a precharge signal φj rising in the negative direction. This precharge signal φj is
During the period of "'' level, the p-channel MOS transistors of the bit line precharge circuit 41 and the data bus line precharge circuit 42 whose gate input is the precharge signal φj are turned on, and the bit line and the data bus line are set to V. The bit line and data bus line are precharged, the precharge signal φj becomes "H" level, and the p-channel MOS of the precharge circuits 41 and 42 is precharged.
After the transistor is turned off, the selected word line becomes the "H" level, the column selection signal Yl becomes the "L° level," and the information of the selected memory cell 44 is transferred to the bit line pair Di, Tf'.
T, the data bus line pair DB via the column switch circuit 43 in which the column selection signal Yi is at the ``L'' level.
-11115'-U. Data bus line pair DB
, r is amplified by the data amplifier circuit 45, transmitted to the output circuit, and output.

[Problems to be Solved by the Invention] In the conventional circuit described above, the bit line precharge circuit and the data bus line precharge circuit are controlled by the precharge signal φj. Therefore, the load capacitance to be driven by precharge signal φj is the wiring capacitance (CL) and the gate capacitance (C
G). Here, if the memory is m-bit type, and the p-channel MO3) of the bit line precharge circuit and the data bus line precharge circuit is - the gate length of the transistor,
When the gate width is W and the gate capacitance per unit area is C8, the gate capacitance Co is CG = 3XLXW'XCo
X (n+1)Xm. By adopting the word line division method, the number nXm of bit line precharge circuits controlled by the precharge signal φj is reduced to 256~IM
The value is around 128 for a 128K x 8-bit IMSRAM, and approximately 7 pF for a 128K x 8-bit IMSRAM.

As described above, in conventional circuits, the gate capacitance of the transistor in the precharge circuit is extremely large among the load capacitance that the precharge signal φj has to bear, so there is a delay in the time from the address input change to the completion of the precharge operation. The waveform of the precharge signal φj is rounded, causing an access delay.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, the precharge circuit controlled by the precharge signal generated from the address change detection circuit is only the data bus line precharge circuit, A large number of bit line precharge circuits receive a column selection signal Yi that controls a column switch circuit connected to the bit line to which the precharge circuit is connected.
controlled by.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 11 is a bit line precharge circuit, 12 is a data bus line precharge circuit, 13 is a column switch circuit, 14 is a memory cell, 15 is a data amplifier circuit, W1
~W! I is a word line, DI, positive T to Dn, D1- is a bit line pair 0, DB and D are a data bus line pair. Furthermore, Y1 to Yn are column selection signals, and φj is a precharge signal that rises in the negative direction when an address changes.

Data bus line precharge circuit 12 and column switch circuit 13 are controlled by precharge signal φj and column selection signals Y1 to Yn, respectively, which are generated from an address change detection circuit, as in the conventional example. During the period when the precharge signal φj is at the "L" level, the p-channel MO3 transistor of the data bus line precharge circuit 12 whose gate input is the precharge signal φj is turned on, and the data bus line pair DB, TTτ- is turned on. Precharge to level 0. After the precharge signal φj goes to 'H' level, the word line corresponding to the selected address goes to 'H' level, the column signal Y1 goes to L' level, and the information of the selected memory cell is transferred to the bit line. , column switch circuit 1
3, the data bus line, the data amplifier circuit 15, and the output circuit.

Next, the operation of the bit line precharge circuit 11 will be explained.

When the column selection signal Yi is at “H” level, the p-channel MO8)-transistor of the bit line precharge circuit 11 is set to O.
NI,, bit line pair Di, ■]- to V. . Precharge to level. When the column selection signal is at the "'L'° level, the p-channel MO3I- transistor of the bit line precharge circuit i?811 is turned off. The column selection signal for the unselected column is at the 'H'° level, and the column selection signal for the selected column is Since is at the ``L'' level, each bit line is precharged by the bit line precharge circuit 11 during non-selection cycles.

The bit line precharge operation at each address change will be explained using the waveform diagram in FIG. In the case illustrated in FIG. 3, the selected column for cycle 1 is column 1, and the selected column for cycle 2.3 is column n. The address change from cycle 0 to cycle 1 and the address change from cycle 1 to cycle 2 are changes in only the column address or simultaneous changes in the row address and column address, and the address change from cycle 2 to cycle 3 is Only the row address changes.

The bit line pair of the selected column at the time of an address change including a column address change leading to cycle 1 or cycle 2 has already been precharged when it was in the non-selected state in the previous cycle, so the column selection signal Yi “
There is no problem even if the p-channel MOS transistor of the bit line precharge circuit 11 is turned off due to the low level.

When only the row address changes, such as when moving from cycle 2 to cycle 3, the p-channel MOS of the bit line precharge circuit 11 connected to the bit line pair Dn and Tl of the selected column The transistor remains OFF, but the transfer gate of the column switch circuit 13 remains ON, and the bit line pair Dn (lower) is in a conductive state with the data bus line pair DB, ■■, so the precharge is not completed. In response to signal φj, the p-channel MOS transistor of data bus line precharge circuit 12 sets ONL data bus line pair DB-r to ■. . When precharging to the VCC level, the Bi-Node line pair Dn, Ti is also precharged to the VCC level at the same time.

To summarize the above, during an address change including a column address change, the selected bit line pair is precharged by the bit line precharge circuit I\811 when it was in the non-selected state during the previous cycle, and the selected bit line pair is When only the address changes, the selected bit/node line pair changes from the previous cycle.
This means that it is precharged along with the data line pair by the data bus line precharge circuit 12 via the column switch circuit 13 which remains in the N state.

As explained above, according to the circuit shown in FIG.
Since the precharge circuit driven by the signal φj is only the data bus line precharge circuit, the load capacitance to be borne by the precharge signal φj is significantly reduced.

For example, in the case of an IMSRAM with a 128K x 8-bit configuration, the capacitance in the conventional circuit was approximately 7 pF, whereas in the circuit of the embodiment, the transistor size of the data bus line precharge circuit is reduced by the size of the transistor between the data bus line and the bit line. Co = 3xLxWxCo
X2Xm#0.8pF.

Furthermore, in the circuit of the embodiment, the wiring for the precharge signal is only required for the data bus line precharge circuit, so the capacitance CL due to the wiring is also significantly reduced.

As a result, it becomes possible to shorten the time from address change to completion of precharge, and it is possible to speed up access.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. In the figure, 2] is a bit line precharge circuit, 24 is a memory cell, Wρ is a word line, Di and 'W are below a bit line pair, and Yi is a column selection signal. In the bit line precharge circuit 21, the transistor that is controlled by the column selection signal Yi and precharges the bit line pair is composed of an n-channel MO3 transistor. The circuit operation is the same as in the previous embodiment. The level at which the bit line pair is precharged is Vcc Vt (Vt is the threshold voltage of the n-channel MOS transistor), but
The same effects as in the previous embodiment can be achieved.

[Effects of the Invention] As explained above, in the precharge circuit according to the present invention, the bit line precharge circuit is controlled by the column selection signal, and only the data bus line precharge circuit controls the precharge circuit generated from the address change detection circuit. Since it is controlled by the charge signal, according to the present invention, the load capacitance to be driven by the precharge signal is determined by the gate capacitance (CG) of the MOS transistor of the precharge circuit and the wiring capacitance (CL) of the precharge signal wiring. Both can be significantly reduced. Therefore, according to the present invention, it is possible to speed up the process from changing the address to generating the precharge signal, and it is possible to speed up access. In addition, in conventional circuits, the precharge signal controls the bit line precharge circuit and the data bus line precharge circuit, so the precharge signal wiring is routed in two locations across the cell array. However, in the present invention, since the precharge signal controls only the data bus line precharge circuit, the area for wiring can also be reduced.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing embodiments of the present invention, FIG. 3 is a waveform diagram of pulses used in the embodiment of the present invention and the conventional example, and FIG. 4 is the circuit of the conventional example. It is a diagram. 11.21.41...Bit line precharge circuit, 12.42...Data bus line precharge circuit, 13.43...Column switch circuit, 1
4.24.44...memory cell, 15.45.
...Data amplifier circuit, φj...Precharge signal, W1~W! 2...word line,
Dl, ■T~Dn, Ti・=-bit line pair, ¥
1~Yn・・・Column selection signal, DB, D・・
...Data bus line pair.

Claims (2)

[Claims] (1) One or more pairs of data buses, multiple pairs of bit lines provided for each pair of data buses, multiple memory cells provided for each pair of bit lines, and the data bus and its corresponding components. a first switching means connected between the bit line provided in the column and controlled by a column selection signal;
A semiconductor memory device comprising a second switching means connected between a power supply and the bit line and controlled by the column selection signal and operating complementary to the first switching means. (2) The semiconductor memory device according to claim 1, further comprising a third switching means connected between the data bus and the power supply and controlled by a precharge signal generated when an address input changes.