GB2286272A - Data memory sense amplifier operation - Google Patents

Abstract

A data memory comprises a memory cell operable to generate one or more data signals indicative of a data bit stored in that memory cell; a sense amplifier associated with the memory cell, for generating an output signal indicative of the state of the one or more data signals; and means for disabling operation of the sense amplifier in response to the generation of the output signal by the sense amplifier. The memory may also include an output latch and two sense amplifiers each responsive to one of the two output states of the one or more data signals. <IMAGE>

Description

DATA MEMORY SENSE AMPLIFIER OPERATION This invention relates to data memory sense amplifier operation.

Many random access memories (RAMs) employ sense amplifiers to increase the speed of reading data stored in respective memory cells.

In typical RAMs the memory cells are arranged in groups (or rows), with each sense amplifier being connected in parallel to a respective memory cell in each of the rows. A part of a memory address supplied to the RAM is used to select and activate one of the rows; the outputs of the memory cells in the activated row are connected via bit-lines to the inputs of the sense amplifiers.

A RAM read or write cycle may be initiated either by placing a new address on an address input of the RAM (which is usually the case for individual RAM chips) or by a transition in a clock or other control signal (which is generally the case for a RAM in an embedded controller device). A number of events then take place. Firstly, a state of RAM pre-charge is disabled, releasing the RAM from an idle condition and priming it for an active read or write operation. At the same time, or very shortly after, a row decoder starts to decode the input address, in order to generate a unique row-line output. For a medium sized RAM this may involve decoding eight address inputs to select one of 256 row control lines. After the row control line has been selected, all of the memory cells which are controlled by that row control line are activated, and those particular memory cells can be read-from or written-to.

In the case of a read cycle, the selected memory cells begin to charge or discharge bit-lines connecting the memory cells to the respective sense amplifiers, and subsequently the charge currents or resulting voltage changes on the bit-lines are detected by the sense amplifiers. Each memory cell is physically small and so the drive strength is weak, yet the bit-lines are shared by many memory cells.

Inevitably, the rate of voltage or current change on the bit-lines is slow, and so high-gain sense amplifiers are used for high-speed RAMs because they can react quickly to small changes in input. Finally the outputs of the sense amplifiers (i.e. the data output of that row of the RAM) are written to the system or output data bus via a powerful buffer.

Between the bit-lines and the sense amplifier there may also be a multiplexing stage (column decode) which further reduces the selection of RAM cells before presentation at the sense amplifier inputs, though this stage is often absent; column decoding is often enabled at the same time as row decoding.

Sense amplifiers are designed to be particularly fast and responsive to small changes in their inputs. This however has the corollary that the sense amplifiers consume relatively large supply currents.

It is a constant aim in the design of data memories to reduce the power consumption of the data memories.

This invention provides a data memory comprising: a memory cell operable to generate one or more data signals indicative of a data bit stored in that memory cell; a sense amplifier associated with the memory cell, for generating an output signal indicative of the state of the one or more data signals; and means for disabling operation of the sense amplifier in response to the generation of the output signal by the sense amplifier.

The invention recognises that in modern RAM designs, the sense amplifiers may complete the sensing of the state of the memory cell at a relatively early stage in a RAM read cycle. Maintaining operation of the sense amplifiers after the sensing has been completed can give rise to a considerable and unnecessary power drain.

The invention addresses this problem by arranging for operation of the sense amplifier to be disabled (switched off) in response to the completion of the sensing operation. Thus, the high current consumption of the sense amplifiers is avoided during at least part of a RAM read cycle. By making the disabling of the sense amplifier responsive to the completion of the sensing operation, the sense amplifier is thus 'self timed'. This avoids potential problems which might occur if the sense amplifier was turned off before completion of the sensing operation, e.g. at the end of a predetermined time period.

The skilled man will appreciate that the quiescent supply current of the sense amplifiers (i.e. the supply current when operation of the sense amplifier is disabled) need not necessarily be zero, but is considerably lower than the operational current of the sense amplifiers.

Further advantageous power savings can be achieved in an embodiment of the invention, in which the means for disabling is operable to disable operation of the memory cell in response to the generation of the output signal by the sense amplifier.

Preferably the data memory comprises a group of memory cells associated with the sense amplifier; and an address decoder, responsive to a memory address supplied to the data memory, for controlling one of the group of memory cells to generate respective data signals.

In a preferred embodiment the data memory comprises a plurality of groups of memory cells, each group having an associated sense amplifier.

Another problem which can occur in previous data memory designs is that of output 'glitches'. These glitches result from a common feature of fast sense amplifier designs known as 'internal pre-charge', where the internal circuit nodes within the sense amplifier are pre-set to a certain logic value, or equalised. Internal pre-charging leads to a rapid settling time when a new input is presented to the sense amplifier. However, a drawback of the use of internal pre-charging or equalisation is that the sense amplifier can initially output one value, and then quickly over-write it with a new value once sensing has taken place.

Accordingly, in a preferred embodiment, the data memory comprises, for each group of memory cells: an output latch; a first sense amplifier, for setting the output latch to a first output state in response to a first state of the one or more data signals; and a second sense amplifier, for setting the output latch to a second output state in response to a second state of the one or more data signals.

This embodiment provides a convenient means of detecting completion of the sensing operation by the sense amplifiers (since one of the sense amplifiers will always change state during sensing), and also addresses the problem of output glitches described above by the counter-intuitive step of doubling the number of sense amplifiers used in the data memory. This can lead to overall power reduction by allowing better control of the RAM output stages. Two sense amplifiers are used to read data stored in one memory cell, an output latch is employed whose output is set by a positive detection of a particular logical polarity of the stored data. The latch is only overwritten when one or other of the sense amplifiers has positively responded to an input change, and therefore no glitch is propagated.

For example, one sense amplifier acts on positive input data from the memory cell and the other acts on negative input data from the memory cell. Both may be internally pre-charged or equalised to a certain logic-level, then when sensing is complete, either one or the other (but not both) of the sense amplifier outputs will have changed from the pre-charge level, depending on the input change. There is therefore some positive indication that sensing has been completed because one of the sense amplifier outputs must have changed from the initial idle state. However, multiple sense amplifiers are not necessary for all embodiments of the invention; a similar positive indication could be obtained in other embodiments by, for example, precharging a single sense amplifier to a level between a logical high and a logical low level, and then detecting movement of the sense amplifier output.

Preferably the data memory comprises means for pre-charging the or each sense amplifier to a predetermined state.

In a preferred embodiment, the data memory comprises a data buffer connected to buffer the output of the data memory.

In order to allow output onto a shared data bus, it is preferred that the data buffer is a tri-state buffer; and the data memory comprises means for setting the data buffer from a high impedance output state to an output state indicative of the output signal generated by the sense amplifier, in response to the generation of the output signal by the sense amplifier. In this way the data buffer is not changed from a high impedance state until the sensing operation has been completed. However, advantageously, the data buffer can be made ready for output immediately after the sensing operation has been completed, using the same 'self timing' arrangement as that described above.

Viewed from a second aspect this invention provides a method of operation of a data memory comprising a memory cell operable to generate one or more data signals indicative of a data bit stored in that memory cell and a sense amplifier associated with the memory cell, for generating an output signal indicative of the state of the one or more data signals; the method comprising the step of disabling operation of the sense amplifier in response to the generation of the output signal by the sense amplifier.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a schematic block diagram of a random access memory; Figure 2 is a schematic diagram of a sense amplifier circuit; and Figure 3 is a timing diagram illustrating the operation of the sense amplifier circuit of Figure 2.

Figure 1 is a schematic block diagram of a random access memory comprising an array of memory cells 10 arranged as a number of rows 20 of memory cells.

Each of the memory cells 10, when selected during a read operation, produces two output signals referred to as 'bit' and 'nbit'.

The bit and nbit outputs of memory cells at corresponding positions in each of the rows 20 are connected to common signal lines 30, referred to as 'bit-lines'.

During a memory read operation, a row decoder 40 receives an address signal 50 specifying a single one of the rows 20 and, in response to the address signal 50 and a read enable signal 60, generates a single row enable signal 70 which enables one of the rows 20 of memory cells for a read operation. Thus, memory cells in the selected row place their respective bit and nbit outputs onto the bitlines 30, and all other memory cells in unselected rows present a high impedance to the bit-lines 30.

The enabling of the rows of memory cells is also under the control of a further row enable signal 62, to be described further below. In this embodiment, the signals 62 and 70 are combined in each row 20 by a logical AND operation (not shown), so that a row is enabled if both of the signals 62 and 70 are high.

The bit-lines 30 are connected to respective sense amplifier circuits 80. Between reading operations, the outputs (bit and nbit) of each memory cell 10 are pre-charged to a logical high state. When the selected row of memory cells is read, either the bit or the nbit output falls from the pre-charged high state to a low state (thereby indicating the storage of a logical one or a logical zero in that memory cell). However, because the two outputs of the memory cells 10 are connected to physically long bit-lines 30 having a high capacitance, the rate at which the outputs of the selected memory cells change is slow. For this reason, the sense amplifier circuits 80 amplify small changes in the bit-line voltage or current to detect which of the bit and nbit outputs is changing at an early stage. This increases the reading speed of the data memory.

A stage of column decode multiplexing (not shown) may be included between the memory cells and the sense amplifier circuits 80.

The sense amplifier circuits 80 generate an output signal 90 representing the stored bit in the corresponding memory cell 10 in the currently selected row 20. The sense amplifier circuits 80 incorporate a stage of tri-state buffering, which allows the output 90 to be connected to a shared system data bus (not shown).

Figure 2 is a schematic diagram of a sense amplifier circuit.

The sense amplifier circuit 80 comprises two sense amplifiers 200, 210, a sense amplifier output latch 220, an output enable latch 230 and a tri-state buffer circuit 240. The sense amplifier circuit 80 receives the bit and nbit signals from a pair of bit-lines 30 and generates the buffered output signal 90 at its output. The output 90 is connected, with other tri-state buffered devices, to a common (shared) data bus.

The two sense amplifiers 200, 210 are connected in parallel with opposite polarities, so that the non-inverting input of the sense amplifier 200 is connected to the bit signal of the bit-lines 30, and the non-inverting input of the sense amplifier 210 is connected to the nbit signal. Both of the sense amplifiers 200, 210 are pre-charged to provide a fast response. This involves setting the internal nodes and the outputs of the sense amplifiers to a predetermined state before they are used in a read operation. In particular, the outputs of the sense amplifiers 200, 210 are pre-charged to a low logical state, with the output rising to a high logical state if the signal at the noninverting input of that sense amplifier falls towards a low logical state. If the signal presented at the inverting input of a sense amplifier falls then the output of that sense amplifier remains at a low logical state.

Accordingly, if the signal on the 'bit' line falls (indicating that the memory cell under consideration stored a logical zero) then the output of the sense amplifier 200 rises and the output of the sense amplifier 210 remains low. Conversely, if the signal on the 'nbit' line falls (indicating that the memory cell under consideration stored a logical one) then the output of the sense amplifier 210 rises and the output of the sense amplifier 200 remains low.

The sense amplifiers 200, 210 are enabled, and subsequently disabled (switched off), by a sense enable signal 61 derived from the read enable signal 60 and the output of the output enable latch 230.

The respective outputs of the sense amplifiers 200, 210 are supplied in parallel as inputs to the sense amplifier output latch 220 and the output enable latch 230.

The sense amplifier output latch 220 comprises a flip-flop circuit 225 and a pair of NOR gates 223, 224. In the case where the memory cell stores a logical zero, the rising output of the sense amplifier 200 causes the flip-flop 225 to assume a state in which a node 221 is high and a node 222 goes low. The flip-flop outputs are combined with the sense amplifier outputs by the two NOR gates 223, 224. With the output of the sense amplifier 200 high, the output of the NOR gate 223 is low and the output of the NOR gate 224 is high.

The outputs of the NOR gates 223 and 224 are supplied to the tri-state buffer circuit 240.

In this way, the outputs of the sense amplifier output latch 220 (i.e. the outputs of the NOR gates 223, 224) reflect the detected state of the memory cell being sensed. If the output of the gate 223 is high and that of the gate 224 low, the state of the memory cell has been detected to be high, and vice versa.

The flip-flop circuit 225 therefore changes state only in response to one of the sense amplifier outputs rising. When both sense amplifiers 200, 210 are pre-charged (low), the previous state of the flip-flop circuit 225 remains valid. However, the previous state of the flip-flop circuit 225 is not output by the circuit 80. This is because the output enable latch does not control the tri-state buffer circuit 240 to place a valid output onto the bus until the current state of the sense amplifier outputs has been detected.

As mentioned above, the respective outputs of the sense amplifiers 200, 210 are also supplied as inputs to the output enable latch 230, which receives the read enable signal 60 as a further input.

The output enable latch 230 controls the tri-state buffer circuit 240 so that the sense amplifier circuit 80 produces an output 90 onto the shared data bus only when the content of the memory cell has been detected. In other words, the output enable latch 230 controls the tri-state buffer circuit 240 to remain in a high impedance output state until one of the sense amplifier outputs has risen to a high state.

The output enable latch 230 comprises an OR gate 231, which receives the sense amplifier outputs as its respective inputs, coupled to a NAND gate 232 and a flip-flop circuit 233. The outputs of the flip-flop circuit 233 are supplied as control inputs to the tri-state buffer 240.

When the sense amplifiers 200, 210 are pre-charged, their outputs are at a low logical state. The output of the OR gate 231 is therefore low and so the output of the NAND gate 232 is high. This forces the control output 234 low and the control output 235 high. As described above with reference to Figure 2, this controls the tri-state buffer circuit 240 to assume a high impedance output state.

When the output of one of the sense amplifiers 200, 210 rises, the output of the OR gate 231 goes high. Assuming the read enable signal 60 is also high, the output of the NAND gate 232 goes low. This forces the control output 234 high and the control output 235 low. As described below, these states of the control outputs 234, 235 enable the tri-state buffer circuit to provide a valid output 90 on the shared bus.

The tri-state buffer circuit 240 is a conventional design comprising a logical-NAND gate 241, a logical-NOR gate 242 and a pair of output transistors. The circuit receives as inputs the respective outputs 234, 235 of the output enable latch and the respective outputs of the NOR gates 223, 224.

If the signal 234 is low and the signal 235 is high, then the output of the NAND gate 241 is high and the output of the NOR gate 242 is low. These signals switch off (i.e. set to high impedance) the output transistors (a p-channel transistor and an n-channel transistor respectively) connected to the NAND gate 241 and the NOR gate 242. The output 90 is now not driven, which allows other tri-state buffers access to the common bus.

Conversely, if the signal 234 is high and the signal 235 is low, then the NAND gate 241 and the NOR gate 242 are enabled and the buffered output 90 is dependent on the polarity of the outputs of the NOR gates 223 and 224.

In either case, the tri-state buffer circuit 240 is not enabled for output (changed from a high impedance state) until one of the sense amplifier outputs has risen. This means that a valid output is not produced until the current state of the memory cell has been detected.

In addition, the polarity of the output 90 reflects the respective outputs of the NOR gates 223, 224 and therefore the detected state of the memory cell.

The sense enable signal 61 is derived by a logical combination of the read enable signal 60 and the control signal 234. In particular, the read enable signal 60 is inverted by an inverter 201, and the inverted signal is combined with the control output 234 by a NOR gate 202.

The sense enable signal is therefore enabled only when the read enable signal is high and the output 234 is low. During a read operation, when the output 234 rises, the sense amplifiers are disabled, thus reducing unnecessary power consumption of the circuit 80. However, this does not lead to incorrect sensing of the stored data because, as described above, the rising of the signal 234 does not take place until one of the sense amplifier outputs has risen, i.e.

when the data has already been sensed. This means that the sense amplifiers are 'self timed', so that the time at which they are switched off is controlled to be immediately after they have completed their function of sensing the state of the bit-lines 30.

The sequence of operations of the circuit 80 is summarised by a schematic timing diagram shown in Figure 3 of the accompanying drawings.

In Figure 3, a RAM read operation is initiated by the read enable signal going high. Since at this stage the sense amplifiers 200, 210 are both pre-charged to a low output, the control output 234 is low.

The combination of the low state of the control output 234 and the high state of the read enable signal 60 causes the sense amplifiers to be enabled by the sense enable signal 61.

When the sense amplifiers have sensed the state of the bit-lines 30, i.e. when one of the sense amplifier outputs has risen, the sense amplifier output latch is set to store the sensed state of the bitlines and the control signal 234 goes high. This has two effects: the tri-state buffer circuit 240 is enabled for output, and the sense amplifiers 200, 210 are switched off.

The tri-state buffer circuit 240 is finally switched off by the read enable signal returning to a low state at the end of the read cycle.

A further power reduction may also be achieved in this embodiment by forming the row enable signal 62 from the sense enable signal 61.

In this way, the currently selected row 20 of memory cells 10 is deselected when the sense enable signal falls (i.e. when the current states of the memory cells have been sensed). This can be performed either by combining the respective row enable signals 62 from all of the sense amplifier circuits 80, so that the whole of the currently selected row is deselected only when all of the sense amplifier enable signals have fallen.

Claims (11)

1. A data memory comprising: a memory cell operable to generate one or more data signals indicative of a data bit stored in that memory cell; a sense amplifier associated with the memory cell, for generating an output signal indicative of the state of the one or more data signals; and means for disabling operation of the sense amplifier in response to the generation of the output signal by the sense amplifier.

2. A data memory according to claim 1, in which the means for disabling is operable to disable operation of the memory cell in response to the generation of the output signal by the sense amplifier.

3. A data memory according to claim 1 or claim 2, comprising: a group of memory cells associated with the sense amplifier; and an address decoder, responsive to a memory address supplied to the data memory, for controlling one of the group of memory cells to generate respective data signals.

4. A data memory according to claim 3, comprising a plurality of groups of memory cells, each group having an associated sense amplifier.

5. A data memory according to claim 4, comprising, for each group of memory cells: an output latch; a first sense amplifier, for setting the output latch to a first output state in response to a first state of the one or more data signals; and a second sense amplifier, for setting the output latch to a second output state in response to a second state of the one or more data signals.

6. A data memory according to any one of the preceding claims, comprising means for pre-charging the or each sense amplifier to a predetermined state.

7. A data memory according to any one of the preceding claims, comprising a data buffer connected to buffer the output of the data memory.

8. A data memory according to claim 7, in which: the data buffer is a tri-state buffer; and the data memory comprises means for setting the data buffer from a high impedance output state to an output state indicative of the output signal generated by the sense amplifier, in response to the generation of the output signal by the sense amplifier.

9. A method of operation of a data memory comprising a memory cell operable to generate one or more data signals indicative of a data bit stored in that memory cell and a sense amplifier associated with the memory cell, for generating an output signal indicative of the state of the one or more data signals; the method comprising the step of disabling operation of the sense amplifier in response to the generation of the output signal by the sense amplifier.

10. A data memory substantially as hereinbefore described with reference to the accompanying drawings.

11. A method of operation of a data memory, the method being substantially as hereinbefore described with reference to the accompanying drawings.