JPH0743925B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory array configuration method suitable for high integration and low power consumption.

[Background of the Invention]

As semiconductor memory devices become highly integrated and have large capacities in the future, it will become increasingly important to design with due consideration for low power consumption.

FIG. 1 shows the structure of a conventional semiconductor memory device. The memory cells MC are arranged in a matrix at the intersections of the word lines W _{0 to} W ₃ and the data lines D _{0 to} D ₃ . In this structure, the read operation is performed as follows. When the address signals A _{0 to} A ₃ from the outside are input, the X decoder (XDE
C) is determined. As a result, for example, when the word line W ₃ is selected, a selection pulse is output to the word line W ₃ by the X driver (XDRV), and a read signal is output from the memory cells connected to the word line W ₃ to each of the data lines D _{0 to} D _3. Appears. On the other hand, if the data line D ₀ is selected by the Y decoder (YDEC), the signal read to D ₀ is output to the I / O line through the switch YG ₀ and is output to the outside as the data output D _out. Is output.
Writing is performed by the data input D by the write control signal WE.
_in is sent to the I / O line, switch YG ₀ , and data line D ₀ , and the data is written to the memory cell MC connected to the intersection with the selected word line W ₃ . Here, various internal timings are generated from the timing generation circuits TMG1 and TMG2 by the clock φ, and various circuit operations are controlled. Further, in the figure, AR indicates a memory array, and CHIP indicates the entire chip.

Now, in the conventional configuration shown in FIG. 1, the switch YG for transferring data is located close to the word line (for example, W ₃ ).
The entire data line, that is, the connection point from the switch YG to the farthest end, is involved in the read or write operation of the memory cell connected to, and the entire data line is charged and discharged with the memory operation. There was a problem from the viewpoint of reduction.

[Object of the Invention]

An object of the present invention is to improve the conventional memory array configuration described above and provide a memory array configuration capable of reducing power consumption.

[Outline of Invention]

The present invention for achieving the above object divides a data line into a plurality of portions by a switch, and separates a data line portion that does not form an access path of a selected memory cell from the access path by opening and closing the switch, This makes it possible to reduce power consumption.

Example of Invention

 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 2 shows an embodiment of the present invention, which corresponds to the memory array section of the conventional configuration shown in FIG. In this embodiment, the data line is divided into two by the switch SW, and the first data line portion (D ₀₁ , D ₁₁ , D ₂₁ , D from the connection switch YG of the divided data lines connected to the I / O line). ₃₁ )) when the memory cell connected to
Set to F state and the second data line part (D ₀₀ , D ₁₀ , D ₂₀ , D ₃₀ ).
Is separated from the first data line portion (D ₀₁ , D ₁₁ , D ₂₁ , D ₃₁ ). On the other hand, when the memory cell connected to the second data line portion is selected, the switch SW is turned on, and the selected memory cell and the I / O line are connected through the switch SW and YG. According to this embodiment, when the memory cell connected to the first data line portion viewed from the switch YG is selected, the data line capacitance charged and discharged during the memory operation disconnects the switch SW in the OFF state. data line portion reduced by _{(D 00, D 10, D} 20, D 30) minute, can be reduced correspondingly power consumption. That is, when the data line is divided into two equal parts by the switch SW as shown in FIG. 2, when the word line W ₂ or W ₃ is selected, the data line capacitance becomes half as compared with the conventional example shown in FIG. , Word line W ₀ or
When W ₁ is selected, it is equal to the conventional example, and as a result, the average power consumption due to the charging / discharging of the data line can be 3/4 times that of the conventional example. In addition, in FIG. 2, the switch SW
Although the case where one data line is provided and the data line is equally divided is shown, n-1 number of switches may be provided and the data line may be divided into n (it is not necessary to be evenly divided). When selecting the memory cell in the m-th data line part of the data line from the switch YG, similarly, the m-1st switch SW from the switch YG is turned on and the m-th switch is turned off. You can do this. As a result, the average power consumption is You can Here, n is 1 ≦ n ≦ (the number of memory cells connected to one data line).

FIG. 3 shows another embodiment of the present invention. The present invention is applied to the case where the memory array is equally divided and the memory cells are respectively operated in the divided memory arrays (AR _a , AR _b ). Here is an example. As shown in the figure, the data line in each memory array is divided by the switches SW _a and SW _b . In such a configuration, the memory cell connected to the second data line portion (D _a0 ) _viewed from the connection switch (YG _a ) with the I / O line of one memory array (eg, AR _a ) is operated. At this time, in the other memory array (AR _b ), the memory cell connected to the first data line portion (D _b1 ) is operated. In this case, the switch (SW _a ) dividing the data line in the former memory array (AR _a ) is turned on, and the switch (SW _b ) of the latter memory array is turned off. According to this embodiment, the data line portion (D _a0
Alternatively, since D _b0 ) is disconnected, the power consumption can be reduced to 3/4 times as compared with the conventional method of charging and discharging the entire data line. Further, in the embodiment shown in FIG. 2, the average power consumption can be reduced, whereas in the present embodiment, the power consumption can be always 3/4 times that of the conventional method even if an arbitrary memory cell is selected. In FIG. 3, the data line of each memory array is equally divided by a switch, that is, when the number of memory cells connected to each part of the divided data line is equal, power consumption is always maintained even if an arbitrary memory cell is selected. The conventional method 3/4
Can be doubled.

FIG. 4 shows another embodiment of the present invention in which the data line shown in FIG. 3 is further divided into four equal data lines, and the selected word line is divided. Table 1 shows the relationship with the state of each switch.

According to this example, in any of the cases shown in the table, the power consumption can be reduced to 5/8 times that of the conventional method. Similarly, when the data line is divided into n equal parts by the switch, the memory cell connected to the m-th data line part from the connection switch with the I / O line in one memory array and the other In memory array (n + 1-m)
The memory cell connected to the second data line portion may be operated. In addition, the mth switch of the former memory array and the (n + 1-m) th switch of the latter memory array are turned off, and the switches on the side of the switches connected to the I / O line are connected to both memory arrays. Tomo
Turn on. As a result, the power consumption is always higher than that of the conventional method. Can be reduced to

Although the concept of the present invention has been shown by using some examples as described above, in order to describe the present invention more specifically,
An embodiment will be shown taking a one-transistor MOS memory composed of n-channel MOS transistors as an example.

FIG. 5 shows a memory cell (folded bitline arrangement or 2) in which the data line D is laid out in close proximity.
FIG. 6 is a specific example of FIG. 2 using an intersection cell).
The figure shows a more detailed example of FIG. That is, the fifth
The figure shows the data pair line as D _i0 , ▲ ▼ with the switch SW.
An example of division into D _i1 , ▲ ▼ (i = 0 to n in the figure) is shown. In this configuration, the divided data line part
When the memory cell connected to D _i0 or ▲ ▼ is selected, the switch SW is switched by the X decoder (XDEC).
Is turned on, the read signal voltage from the memory cell is amplified by the differential amplifier circuit SA, and the amplified signal is read out to the I / O line by the signal line YC controlled by the Y decoder (YDEC). Is controlled. Similarly in the write operation, data input from the outside of the chip is written to the selected memory cell through the I / O line, YG, D _i1 (or ▲ ▼) and SW. On the other hand, the data line part D _i1 or ▲ ▼
When the memory cell connected to is selected, SW is turned off by XDEC, D _i0 and ▲ ▼ are disconnected, and the memory operation is performed. This operation will be described in more detail with reference to FIGS. 6 and 7. First, both the precharge signal φ _P and the signal φ _G that controls the switch SW that divides the data line are set to a high level (V + α), and the precharge circuit PC
To precharge data pair lines D ₀₀ , ▲ ▼ and D ₀₁ , ▲ ▼ to a certain level V. At the same time, the node in the dummy cell DM is set to the ground potential (V _SS ). Then, when the high level of the memory cell MC _k is read after the fall of φ _P , φ _G is dropped by XDEC,
Separate D ₀₀ , ▲ ▼ from D ₀₁ , ▲ ▼. The word line W _k is selected by XDEC and the word pulse φ _W is applied, and the dummy word line DW ₂ is selected by XDEC and the dummy word pulse φ _DW is applied. Thus, the D ₀₁ a signal voltage from the memory cell, ▲ ▼ the output reference signal voltage from the dummy cell, D _01, ▲
▼ A minute differential signal is generated between them. Then start pulse φ
_S is lowered and SA is operated to amplify the differential signal. At this time, the switch SW is in the OFF state,
D ₀₀ , ▲ ▼ will keep the precharge level. After that, a pulse φ _y is output to YC ₀ selected by YDEC, and the amplified differential voltage is taken out to the I / O line via the switch YG.

When the memory cell MC _i is selected, the signal φ _G is kept at a high level (V + α) (shown by the dotted line in FIG. 7). In this case D ₀₀ and D ₀₁ are again ▲ ▼ and ▲
▼ is connected and D ₀₀ , D ₀₁ or ▲ ▼, ▲
▼ is discharged to the ground potential.

The signal φ _G for controlling the switch SW can be easily controlled by using, for example, the upper bit of the address signal input to the X decoder for selecting the word line.

According to the present embodiment, when the memory cell connected to the data line portion D _i1 , ▲ ▼ is selected, the data line portion
Since the precharge state can be maintained even when D _i0 , ▲ ▼ is in memory operation, the capacity of the data line charged and discharged can be reduced as compared with the conventional example in which the switch SW is not provided. The capacity of the data line to be charged / discharged can be reduced not only to reduce the power consumption but also to reduce the peak value of the power supply current or noise due to the coupling between the substrate and the data line. Moreover, power consumption can be reduced when the memory cell information is inversely written.

In FIGS. 5 and 6, the dummy cell DM and the differential amplifier SA are arranged near the switch YG for connection with the I / O line, but they may be arranged near the switch SW, for example. Well, it just needs to be placed between SW and YG. The data line precharge circuit PC is D _i0 , ▲ ▼
It may be arranged on the side.

FIG. 8 is a specific example of FIG. 3 using a 2-intersection cell,
An example in which the memory array is divided into two and the data lines are divided into two will be described. The structure and operation of each of the divided memory arrays are the same as those in FIGS. 5, 6, and 7, but the memory cells and D connected to the data line portion ▲ ▼ as described in FIG. The memory cell of _bi1 or ▲ ▼ is operated, φ _Ga is maintained at a high level, and φ _Gb is lowered to the ground potential. Meanwhile, D _ai1 or ▲ ▼
The memory cell of and the memory cell of D _bi0 or ▲ ▼ are operated to lower φ _Ga to the ground potential and maintain φ _Gb at a high level. In the one-transistor MOS memory, as shown in this embodiment, the memory array may be divided according to the relationship of the refresh cycle, S / N, etc., and each divided memory array may operate a memory cell. According to the example, the data line capacity to be charged / discharged can be reduced, and the reduced amount can be made equal regardless of which memory cell is selected. Although FIG. 8 shows an example in which two sets of I / O lines are provided, the number of I / O lines does not have to be two and may be one set, four sets, that is, any set.

FIG. 9 shows another embodiment of the present invention. In the embodiment shown in FIG. 8, the differential amplifier circuit SA, the dummy cell DM and the data line precharge circuit are arranged on the switch SW side, and further these circuits and the memory are arranged. It has a configuration in which switches XG _a and G _b are added to the cell. By adding this switch, for example, switch XG _a is turned off (switch SW _a is on as described above) during the read operation of the memory cell connected to D _ai0 or ▲ ▼, and the signal voltage is changed by SA. and oN state XG _a after amplifying. Meanwhile D
_During the read operation of the memory cell connected to _ai1 or ▲ ▼, XG _a remains on (SW _a is off). The operation of XG _b is similar. According to this embodiment, in addition to the effect shown in FIG. 8 (equal reduction of power consumption),
_{D ai0, ▲ ▼, D bi0} , ▲ ▼ read signal voltage of the connected memory cell can be increased _{to, D ai1, ▲ ▼, D} bi1, ▲ ▼ connected to a memory cell equivalent is The read signal voltage can be obtained.

FIG. 10 shows another embodiment of the present invention, and shows an example in which a high potential compensation circuit RST for the data line is added to the embodiment shown in FIG. This RST is, for example, ISSCC'81 Techi
cal Digest Consists of circuits described in P.85, SA
After the signal is amplified by, the level of the data line on the high potential side is compensated to obtain a sufficient rewriting voltage. First
As shown in FIG. 10, RST is the S value described in FIGS. 5 and 6.
Like A, it is placed between SW and YG. For the method of precharging the data line between the rewrite voltage obtained by RST and the ground potential, the dummy cell is used.
It is also possible to omit DM.

The embodiments described above with reference to FIGS. 5 to 10 show the case where the precharge levels of the divided data line portions are the same, but even if the precharge levels of the respective data line portions are different. Good. The example is shown below.

In FIG. 11, the data line portion D ₀₀ , ▲ ▼ is set to the potential V ₀ , D ₀₁ ,
An example of precharging ▲ ▼ to V ₁ (V ₀ > V ₁ ) is shown. FIG. 12 shows the case where the memory cell MC _i is selected, and FIG.
The operation waveforms when C _k is selected are shown. MC _i
The read signal voltage obtained in the case of selection is smaller than that in the case of selecting MC _k because the data line capacitance is larger. As a result, the amount of drop from the precharge level on the high potential side of the data line after the signal is amplified by SA becomes large, and the rewrite voltage becomes small. Therefore, as shown in Fig. 11, D ₀₀ , ▲ ▼
By setting the precharge level of the data line higher than that of D ₀₁ , ▲ ▼, even if the high potential side of the data line drops, the same rewrite voltage can be obtained for both. In this embodiment, as shown in FIGS. 12 and 13, unlike the operation shown in FIG. 7, the signal φ _G for controlling the switch SW is at a low level during the precharge operation, and the switch SW is D _00. Work to separate, ▲ ▼ and D ₀₁ , ▲ ▼. Note that in FIG. 11 the transistor
Q _S1 and Q _S2 are D ₀₀ and ▲ ▼, D ₀₁ and ▲ ▼, respectively
Can be omitted because it is for equipotential.

Contrary to FIG. 11, FIG. 14 shows an example of precharging a high potential at D ₀₁ , ▲ ▼. The circuit configuration is the same as that shown in FIG. 10, with dummy cells DM ₁₀ , DM ₂₁ and a short circuit SC.
The configuration is added to the D ₀₀ , ▲ ▼ side. FIG. 15 shows operation waveforms when the memory cell MC _i is selected, and FIG. 16 shows operation waveforms when MC _k is selected. The operation will be described below using this. First, set the precharge signal φ _P to a high level (V + α), and φ _G
Is set to an intermediate level V _G , and the precharge circuit RC and the short circuit SC set D ₀₁ , ▲ ▼ to level V and D ₀₀ , ▲.
Precharge ▼ to (V _G −V _T ). Where V _T is the threshold voltage of the switch SW transistor. And φ _P
When the high level of the memory cell MC _i is read out (FIG. 15) after the falling of, the word line W _i is selected by the X decoder, the word pulse φ _Wi is applied, and the dummy word pulse φ _DW0 is applied. There is applied to the dummy word line DW _20, D _00, ▲ ▼ to D _00, ▲ ▼ differential signal is generated that is determined by the capacitance and the memory cell capacitor section. This differential signal is transferred to D ₀₁ , ▲ ▼ through the switch SW and then amplified by SA. Then, D ₀₁ is restored to the rewriting voltage V by RST, φ _G is boosted to V + α, D ₀₀ is raised to V, and rewriting is performed. Meanwhile M
When reading the high level of C _k (Fig. 16), after φ _P is lowered, φ _G is also lowered and D ₀₀ and D ₀₁ , ▲ ▼ and ▲
The ▼ is separated, and the MC _k signal is read and rewritten. In this embodiment, D ₀₀ or ▲
Even when reading the memory cell connected to ▼,
Set the differential signal amplified by SA to D ₀₁ or ▲ ▼
There is an advantage that it can be made as large as the memory cell. In this embodiment, V _G is If it is smaller, it will not work.

FIG. 17 shows an example in which the switch SW is controlled by two signals φ _G1 and φ _G2 , unlike the embodiment described above. In the configuration shown in FIG. 6, the switch SW is controlled by two control lines GC ₁ and GC ₂ , and a differential amplifier, an I / O line and a switch YG are also arranged on D ₀₀ , ▲ ▼ side. ing.
Further, the so-called full-size dummy cell system is used in which the number of memory cells connected to D ₀₀ , ▲ ▼ is made equal and the dummy cell capacity is made equal to the memory cell capacity. FIG. 18 shows operation waveforms when reading the high level of the memory cell MC _i . As shown in the figure, the gate of the switch (GC ₂ ) connected to the data line on the dummy cell side when reading the signal.
Is maintained at a high level (φ _{G2 in} FIG. 18) and the data line capacitance on the dummy cell side is doubled on the memory cell side to obtain the reference signal voltage. After that, φ _G2 is also lowered to a low level before amplification by SA, the signal line capacitance is unbalanced, and then the signal is amplified. Read MC _{k in} the same way. In this embodiment, it is an advantage that a full size dummy cell can be used in this way. Although FIG. 18 shows the case where only MC _i is operated, MC _k can also be operated simultaneously.

So far, an embodiment using a two-intersection cell has been shown, but a cell of a method in which data pairs are spatially separated (open bitli
The present invention can also be applied to a memory configured by a ne arrangement or one intersection cell. One example is shown in FIG. FIG. 19 corresponds to FIG. 5, which is an example of a two-intersection cell. In the figure, since the data pair lines extend to the left and right around SA, the switch SW (SW _L , SW _R ) that divides the data line also extends to the left and right, and the signal line (GC _L , G _{C R} ) is required for each switch. According to the present invention, the power consumption can be reduced even in the one-intersection cell as described in the two-intersection cell.

Furthermore, the present invention is a memory array configuration in which the data lines are subdivided and I / O lines are arranged for each (for example, Japanese Patent Application No. 56-81).
042, Japanese Patent Application No. 57-125687, Japanese Patent Application No. 58-4162), an example of which is shown in FIG. As shown in the figure, a switch YG controlled by an output control signal YC by a Y decoder and a Y-triver is provided on the divided data line, and data is exchanged with the I / O line. Further, each divided data line is further divided by a switch SW controlled by an output control signal line GC by an X decoder and an X driver, and the selected memory cell has which data line portion (for example, ▲).
The switch SW is opened / closed depending on whether it is connected to ▼, ▲ ▼) to reduce power consumption. Also in this embodiment, the relationship between the selection of the word line and the opening / closing of the switch shown in FIG. 3 or 4 is expanded and applied to this embodiment to reduce the power consumption and reduce the power consumption. The amount can be made equal regardless of which memory cell is selected. In FIG. 20, A indicates an address signal and RWC indicates a read / write control circuit.

Although some embodiments of the present invention have been described above, it goes without saying that the scope of application of the present invention is not limited to the embodiments described here, and various modifications can be made without departing from the spirit of the invention. For example, although the case where the n-channel MOS transistor is used has been described here, it is also possible to use the P-channel MOS transistor by reversing the potential relationships of the signals used. In addition, CMOS (Comple
(mentary MOS) is also applicable to the memory configured. Further, although the one-transistor MOS memory has been described here as an example, a so-called static memory (eg, a flip-flop type memory cell) (for example,
ISSCC83 Technical Digest P.66) and R
The power consumption of the OM (for example, the EEPROM described in ISSCC83 Technical Digest P.168) or a microprocessor equipped with these memories in the same chip can be reduced by the present invention. As an example, FIG. 21 shows an embodiment of the present invention for a static memory. As shown in the figure, a data pair line to which a large number of flip-flop memory cells are connected is divided by a switch SW controlled by a signal line GC, and a memory cell MC _k is selected by a word line W _k . If the switch is OFF
State, and when memory cell MC _i is selected, set SW to O
By setting the N state, it is possible to reduce power consumption as in the one-transistor MOS memory.

〔The invention's effect〕

As described above, according to the present invention, a memory with low power consumption can be realized despite high integration.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional semiconductor memory device, and FIGS.
FIG. 21 is a diagram for explaining an embodiment of the present invention. MC …… Memory cell, DM …… Dummy cell, d ,, D, ……
Data line, W ... Word line, DW ... Dummy word line, XD
…… X decoder, X driver, YD …… Y decoder, Y driver, I / O, ▲ ▼ …… Input / output line (I / O line), YC …… Y
Driver output line, SA ... Differential amplifier circuit, RC ... Data line precharge circuit, RST ... Data line high potential compensation circuit, S
C …… Short circuit, YG …… I / O line connection switch, SW, XG
...... Switch, GC …… Switch control line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ryoichi Hori 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-51-147931 (JP, A) JP-A-55-58891 (JP, A) JP-A-57-141096 (JP, A)

Claims (5)

[Claims] 1. A plurality of data lines, a plurality of word lines arranged so as to intersect with them, a memory cell arranged at a desired intersection thereof, and a common data line common to the plurality of data lines. And an even number of memory arrays each including a first switch for connecting the common data line to the data line and a plurality of differential amplifier circuits for amplifying a signal read on the data line. In a semiconductor memory device in which at least two or more even number memory arrays are activated at the same time, n−1 second switches for dividing the data lines into n (n ≧ 2) partial data lines are provided. Half of the even number of memory arrays that are provided for each of the data lines and that have n-1 switch control lines that control the second switch for each of the memory arrays and that are simultaneously activated Memorial Then, the memory cell connected to the m-th partial data line viewed from the first switch is selected, and the memory cell connected to the (n + 1-m) -th partial data line is selected in the remaining half of the memory array. Means and a first partial data line group that connects the selected memory cell in each of the memory arrays and the common data line to a second partial data line group that does not participate in the connection. A semiconductor memory device having means for separating by. 2. The semiconductor memory device according to claim 1, wherein the differential amplifier circuit is provided only between the first switch and the second switch. 3. The semiconductor memory device according to claim 1, wherein the pair of adjacent data lines form a pair of data battles. 4. The n is 3 or more, and the differential amplifier circuit is provided between the first switch and the second switch which are the second switch as viewed from the first switch. The semiconductor memory device according to claim 3. 5. The semiconductor memory device according to claim 1, wherein the memory cell comprises one transistor and one capacitor.